From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Conor Dooley" <conor.dooley@microchip.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 07/19] riscv: Optimize riscv_cpu_isa_extension_(un)likely()
Date: Fri, 12 Apr 2024 21:33:20 +0100 [thread overview]
Message-ID: <20240412-eccentric-prune-a19dfc485748@spud> (raw)
In-Reply-To: <ZhlwpKuqVkQCr6u+@ghost>
[-- Attachment #1: Type: text/plain, Size: 2253 bytes --]
On Fri, Apr 12, 2024 at 10:34:28AM -0700, Charlie Jenkins wrote:
> On Fri, Apr 12, 2024 at 11:40:38AM +0100, Conor Dooley wrote:
> > On Thu, Apr 11, 2024 at 09:11:13PM -0700, Charlie Jenkins wrote:
> > > When alternatives are disabled, riscv_cpu_isa_extension_(un)likely()
> > > checks if the current cpu supports the selected extension if not all
> > > cpus support the extension. It is sufficient to only check if the
> > > current cpu supports the extension.
> > >
> > > The alternatives code to handle if all cpus support an extension is
> > > factored out into a new function to support this.
> > >
> > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > > ---
> >
> > > static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
> > > {
> > > - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
> > > - return true;
> > > + compiletime_assert(ext < RISCV_ISA_EXT_MAX,
> > > + "ext must be < RISCV_ISA_EXT_MAX");
> > >
> > > - return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
> > > + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && __riscv_has_extension_unlikely_alternatives(ext))
> > > + return true;
> > > + else
> > > + return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
> > > }
> >
> > static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
> > {
> > if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
> > return true;
> >
> > return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
> > }
> >
> > This is the code as things stand. If alternatives are disabled, the if
> > statement becomes if (0 && foo) which will lead to the function call
> > getting constant folded away and all you end up with is the call to
> > __riscv_isa_extension_available(). Unless I am missing something, I don't
> > think this patch has any affect?
>
> Yeah I fumbled this one it appears. I got thrown off by the nested
> IS_ENABLED(CONFIG_RISCV_ALTERNATIVE). This patch eliminates the need for
> this and maybe can avoid avoid confusion in the future.
I think it just creates unneeded functions and can/should be dropped.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2024-04-12 20:33 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 4:11 [PATCH 00/19] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-12 4:11 ` [PATCH 01/19] dt-bindings: riscv: Add vendorid and archid Charlie Jenkins
2024-04-12 9:57 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 02/19] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-12 10:25 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:38 ` Conor Dooley
2024-04-12 18:46 ` Charlie Jenkins
2024-04-12 19:26 ` Conor Dooley
2024-04-12 20:34 ` Charlie Jenkins
2024-04-12 20:42 ` Conor Dooley
2024-04-12 17:12 ` Charlie Jenkins
2024-04-12 18:47 ` Conor Dooley
2024-04-12 20:48 ` Charlie Jenkins
2024-04-12 21:27 ` Conor Dooley
2024-04-12 21:31 ` Charlie Jenkins
2024-04-12 23:40 ` Conor Dooley
2024-04-16 3:34 ` Charlie Jenkins
2024-04-16 7:36 ` Conor Dooley
2024-04-17 4:25 ` Charlie Jenkins
2024-04-17 16:02 ` Evan Green
2024-04-17 22:02 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 03/19] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-12 10:27 ` Conor Dooley
2024-04-12 17:13 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 04/19] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-12 4:11 ` [PATCH 05/19] riscv: Fix extension subset checking Charlie Jenkins
2024-04-12 11:25 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-12 12:30 ` Conor Dooley
2024-04-12 16:58 ` Charlie Jenkins
2024-04-12 18:59 ` Conor Dooley
2024-04-12 14:44 ` kernel test robot
2024-04-13 22:10 ` kernel test robot
2024-04-12 4:11 ` [PATCH 07/19] riscv: Optimize riscv_cpu_isa_extension_(un)likely() Charlie Jenkins
2024-04-12 10:40 ` Conor Dooley
2024-04-12 17:34 ` Charlie Jenkins
2024-04-12 20:33 ` Conor Dooley [this message]
2024-04-12 4:11 ` [PATCH 08/19] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-12 11:49 ` Conor Dooley
2024-04-12 17:43 ` Charlie Jenkins
2024-04-12 20:40 ` Conor Dooley
2024-04-12 21:03 ` Charlie Jenkins
2024-04-12 21:34 ` Conor Dooley
2024-04-12 21:56 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 09/19] riscv: uaccess: Add alternative for xtheadvector uaccess Charlie Jenkins
2024-04-12 4:11 ` [PATCH 10/19] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-12 11:27 ` Conor Dooley
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 11/19] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-12 4:11 ` [PATCH 12/19] riscv: Create xtheadvector file Charlie Jenkins
2024-04-12 11:30 ` Conor Dooley
2024-04-12 18:24 ` Charlie Jenkins
2024-04-12 19:00 ` Conor Dooley
2024-04-12 20:53 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 13/19] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-12 4:11 ` [PATCH 14/19] riscv: hwprobe: Disambiguate vector and xtheadvector in hwprobe Charlie Jenkins
2024-04-12 11:34 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 22:08 ` Evan Green
2024-04-12 22:37 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector enabled Charlie Jenkins
2024-04-12 11:37 ` Conor Dooley
2024-04-12 18:26 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 16/19] riscv: hwprobe: Add vendor extension probing Charlie Jenkins
2024-04-12 11:39 ` Conor Dooley
2024-04-12 17:05 ` Evan Green
2024-04-12 18:16 ` Charlie Jenkins
2024-04-12 19:07 ` Evan Green
2024-04-12 20:20 ` Charlie Jenkins
2024-04-12 21:43 ` Evan Green
2024-04-12 22:21 ` Charlie Jenkins
2024-04-12 22:50 ` Evan Green
2024-04-12 23:12 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 17/19] riscv: hwprobe: Document vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-12 4:11 ` [PATCH 18/19] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-12 4:11 ` [PATCH 19/19] selftests: riscv: Support xtheadvector in " Charlie Jenkins
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240412-eccentric-prune-a19dfc485748@spud \
--to=conor@kernel.org \
--cc=aou@eecs.berkeley.edu \
--cc=charlie@rivosinc.com \
--cc=cleger@rivosinc.com \
--cc=conor+dt@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=evan@rivosinc.com \
--cc=guoren@kernel.org \
--cc=jernej.skrabec@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-sunxi@lists.linux.dev \
--cc=palmer@dabbelt.com \
--cc=palmer@rivosinc.com \
--cc=paul.walmsley@sifive.com \
--cc=robh@kernel.org \
--cc=samuel@sholland.org \
--cc=shuah@kernel.org \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).