From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96DBD208A1; Mon, 15 Apr 2024 06:34:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713162850; cv=none; b=pQIa7lbk3f8WlvsLdr8pWQ7efjUMh4sNI/fNqdvpvAZjvq9UTtW2bqalOPVqC6UfnWivNr/E9/ed81q0qddmS7CIw2ve8+TM7MqdfO4rClM3TGdedTV/Woey13FaBkHYlARnWp9/n8V26Jyzo/ObbgD7p8zOY4MJ6MJk97h/0zM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713162850; c=relaxed/simple; bh=to8JE1W8kGTeSceWPJotprZ+r6Q4OT7r5l9YqADML6Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BITgGbwq6145RdB35hlg6OzbCiTzT9vxzhKX99qv4RWpeNXFloYM2/utp+sQDiOkbw3EKmaRMKFyAIA5k1roU9xPlr/eZ+MyYVa31MWtdZwYTE3W2zHTAm1vx1wx767l2TJ8axDmTLMhHJyU1DVrSsfW5AmLZoBaEaYB89XCOMk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=n7SfMYTx; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="n7SfMYTx" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43F6Y1WK075646; Mon, 15 Apr 2024 01:34:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1713162841; bh=v8VJDBC4AtMQTX+MfUtSZs9n3h8WKP6gM1PX/0ljELE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=n7SfMYTxgjmZn+azpLV/vyJepreAgUNpNPl0mLletyAdPUA8nljelC1UQ+NExOzC1 WY/LSs9RvS+NYBpMcRAVhYDNO3BgTh6lIvD5Lw5vdiHNgOYKdz59HxbRGjzODIZZGc +uqPDk+ReFIBMX2q5STL6WU509bjWCCMqkkh69T0= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43F6Y15p075983 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Apr 2024 01:34:01 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Apr 2024 01:34:00 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Apr 2024 01:34:00 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (udit-hp-z2-tower-g9-workstation-desktop-pc.dhcp.ti.com [172.24.227.18]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43F6Xidf065992; Mon, 15 Apr 2024 01:33:58 -0500 From: Udit Kumar To: , , , CC: , , , , , Udit Kumar Subject: [PATCH 4/4] arm64: dts: ti: k3-j721s2: Arranging pin mux in order Date: Mon, 15 Apr 2024 12:03:29 +0530 Message-ID: <20240415063329.3286600-5-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240415063329.3286600-1-u-kumar1@ti.com> References: <20240415063329.3286600-1-u-kumar1@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Arranging pin mux in order of main_pmx0/1, wkup_pmx0/1/2/3. Signed-off-by: Udit Kumar --- .../dts/ti/k3-j721s2-common-proc-board.dts | 30 ++++++++--------- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 32 +++++++++---------- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c5a0b7cbb14f..55b2087117db 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -194,6 +194,21 @@ J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ }; }; +&wkup_pmx1 { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; +}; + &wkup_pmx2 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < @@ -289,21 +304,6 @@ J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ }; }; -&wkup_pmx1 { - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ - J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ - J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ - J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ - J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ - J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ - >; - }; -}; - &main_gpio0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 623c8421525d..14f1d2020f57 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -153,6 +153,22 @@ transceiver0: can-phy0 { }; }; +&main_pmx0 { + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ + >; + }; +}; + &wkup_pmx0 { mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < @@ -190,22 +206,6 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ }; }; -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ - >; - }; - - main_mcan16_pins_default: main-mcan16-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ - J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ - >; - }; -}; - &wkup_i2c0 { status = "okay"; pinctrl-names = "default"; -- 2.34.1