From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
devicetree@vger.kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
conor.dooley@microchip.com, anup@brainfault.org,
atishp@atishpatra.org, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
christoph.muellner@vrull.eu, heiko@sntech.de,
charlie@rivosinc.com, David.Laight@aculab.com,
parri.andrea@gmail.com, luxu.kernel@bytedance.com
Subject: Re: [PATCH v2 2/6] dt-bindings: riscv: Add Zawrs ISA extension description
Date: Fri, 19 Apr 2024 15:45:46 +0100 [thread overview]
Message-ID: <20240419-chafe-leotard-e5daee19b1c8@spud> (raw)
In-Reply-To: <20240419135321.70781-10-ajones@ventanamicro.com>
[-- Attachment #1: Type: text/plain, Size: 2348 bytes --]
On Fri, Apr 19, 2024 at 03:53:24PM +0200, Andrew Jones wrote:
> Add description for the Zawrs (Wait-on-Reservation-Set) ISA extension
> which was ratified in commit 98918c844281 of riscv-isa-manual.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 468c646247aa..584da2f539e5 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -177,6 +177,18 @@ properties:
> is supported as ratified at commit 5059e0ca641c ("update to
> ratified") of the riscv-zacas.
>
> + - const: zawrs
> + description: |
> + The Zawrs extension for entering a low-power state or for trapping
> + to a hypervisor while waiting on a store to a memory location, as
> + ratified in commit 98918c844281 ("Merge pull request #1217 from
> + riscv/zawrs") of riscv-isa-manual.
This part is fine...
> Linux assumes that WRS.NTO will
> + either always eventually terminate the stall due to the reservation
> + set becoming invalid, implementation-specific other reasons, or
> + because a higher privilege level has configured it to cause an
> + illegal instruction exception after an implementation-specific
> + bounded time limit.
...but I don't like this bit. The binding should just describe what the
property means for the hardware, not discuss specifics about a
particular OS.
And with my dt-bindings hat off and my kernel hat on, I think that if we
want to have more specific requirements than the extension provides we
either need to a) document that zawrs means that it will always
terminate or b) additionally document a "zawrs-always-terminates" that
has that meaning and look for it to enable the behaviour.
Documenting something and immediately turning around and saying "this
isn't sufficient, let's assume it means more than it does" just seems
like we should make firmware tell us exactly what we want.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2024-04-19 14:45 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-19 13:53 [PATCH v2 0/6] riscv: Apply Zawrs when available Andrew Jones
2024-04-19 13:53 ` [PATCH v2 1/6] riscv: Provide a definition for 'pause' Andrew Jones
2024-04-19 13:53 ` [PATCH v2 2/6] dt-bindings: riscv: Add Zawrs ISA extension description Andrew Jones
2024-04-19 14:45 ` Conor Dooley [this message]
2024-04-19 15:16 ` Andrew Jones
2024-04-19 15:19 ` Conor Dooley
2024-04-19 16:40 ` Charlie Jenkins
2024-04-21 10:20 ` Andrew Jones
2024-04-22 22:36 ` Charlie Jenkins
2024-04-23 8:46 ` Andrew Jones
2024-04-23 9:05 ` Conor Dooley
2024-04-23 18:00 ` Charlie Jenkins
2024-04-23 19:42 ` Charlie Jenkins
2024-04-24 7:34 ` Andrew Jones
2024-04-24 9:23 ` Christoph Müllner
2024-04-24 10:32 ` Andrew Jones
2024-04-19 13:53 ` [PATCH v2 3/6] riscv: Add Zawrs support for spinlocks Andrew Jones
2024-04-19 15:22 ` Conor Dooley
2024-04-21 21:16 ` Andrea Parri
2024-04-22 8:36 ` Andrew Jones
2024-04-19 13:53 ` [PATCH v2 4/6] riscv: hwprobe: export Zawrs ISA extension Andrew Jones
2024-04-19 13:53 ` [PATCH v2 5/6] KVM: riscv: Support guest wrs.nto Andrew Jones
2024-04-19 13:53 ` [PATCH v2 6/6] KVM: riscv: selftests: Add Zawrs extension to get-reg-list test Andrew Jones
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240419-chafe-leotard-e5daee19b1c8@spud \
--to=conor@kernel.org \
--cc=David.Laight@aculab.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@atishpatra.org \
--cc=charlie@rivosinc.com \
--cc=christoph.muellner@vrull.eu \
--cc=conor+dt@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=heiko@sntech.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kvm-riscv@lists.infradead.org \
--cc=linux-riscv@lists.infradead.org \
--cc=luxu.kernel@bytedance.com \
--cc=palmer@dabbelt.com \
--cc=parri.andrea@gmail.com \
--cc=paul.walmsley@sifive.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).