From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA10C84DFC; Thu, 25 Apr 2024 11:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714046146; cv=none; b=ICm4epltX3gkjMWnFDOxl2mlET1kioleca5KxUR+bfXBEgso38sWAg/1rPiMBfDsQjwsllGWwpSoHfYB7m7J7Hrkap7QtTLTJDpX9d1nhGGI+FJ6bjI5shh0FuOIHDZFVTFL5dvESPNdX6OVDmx38amHDuIf1XwmprCIwUPB8OI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714046146; c=relaxed/simple; bh=mrhbsWvjw9WjbY78WNFDe7QFwDa7DRmw3Yr+H2lGTrI=; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rWWUfWXp+ebMu7p51plSLDEvKoZNtzD8bDixv2kDnJCIdb6xDd8E/owQu+eAJcCZGnXhVOHP6DIFd/fRiJwxNhSMv5BQ3+h7+71DYU87hZ4HzLOS7xk+Jnf0Z50zC3rxxM5V4VTRRsv8xZVsbK4ea4MU5CAKRyFeQJCQUVagz2I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=EVSbkw1t; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EVSbkw1t" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43PBtaFs038060; Thu, 25 Apr 2024 06:55:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1714046136; bh=iOU+avJrKvUWtXP1CGKiTBvYB32jtXSfF4Jg8nrLDRE=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=EVSbkw1t85f4NY8CKO4PBGoa7riJU+Utt9tTF0d2lhDR32YTI8ZG9k5qD+a0nnttR +96YknTQ5pKywUERdeK6cdkCdbErWz5j4lLgMk/dm47Ci22X3CNwbWwi41zBp2gHUS 4ALIXXXPBFyBlCtlt8O1vkcN5MTZF+aazxjiq8mY= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43PBtZEZ028435 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 25 Apr 2024 06:55:35 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 25 Apr 2024 06:55:35 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 25 Apr 2024 06:55:35 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43PBtZDq036136; Thu, 25 Apr 2024 06:55:35 -0500 Date: Thu, 25 Apr 2024 06:55:35 -0500 From: Nishanth Menon To: Chintan Vankar CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , , , , Subject: Re: [PATCH] arm64: dts: ti: k3-am62-main: Add bootph-all property in phy_gmii_sel node Message-ID: <20240425115535.t6bpcfhddacqfrbr@during> References: <20240425095448.1946293-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240425095448.1946293-1-c-vankar@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 15:24-20240425, Chintan Vankar wrote: > Add missing bootph-all property for CPSW MAC's PHY node > phy_gmii_sel. > > Signed-off-by: Chintan Vankar > --- > > This patch is based on linux-next tagged next-20240424. > > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > index e9cffca073ef..7a6f7cdc4cbe 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > @@ -52,6 +52,7 @@ phy_gmii_sel: phy@4044 { > compatible = "ti,am654-phy-gmii-sel"; > reg = <0x4044 0x8>; > #phy-cells = <1>; > + bootph-all; Do not do this at SoC level for peripherals that may or maynot be used at various boards. > }; > > epwm_tbclk: clock-controller@4130 { > -- > 2.34.1 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D