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Source clock selection for timer tick 0x0 = Bus clock (aclk) 0x1 = Function clock (mclk) Signed-off-by: Peter Griffin Acked-by: Krzysztof Kozlowski Tested-by: Will McVicker --- drivers/ufs/host/ufs-exynos.c | 9 +++++++++ drivers/ufs/host/ufs-exynos.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 66e52c3607e2..66093a905986 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -50,6 +50,8 @@ #define HCI_ERR_EN_N_LAYER 0x80 #define HCI_ERR_EN_T_LAYER 0x84 #define HCI_ERR_EN_DME_LAYER 0x88 +#define HCI_V2P1_CTRL 0x8C +#define IA_TICK_SEL BIT(16) #define HCI_CLKSTOP_CTRL 0xB0 #define REFCLKOUT_STOP BIT(4) #define MPHY_APBCLK_STOP BIT(3) @@ -1005,6 +1007,13 @@ static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) { u32 val; + /* Select function clock (mclk) for timer tick */ + if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { + val = hci_readl(ufs, HCI_V2P1_CTRL); + val |= IA_TICK_SEL; + hci_writel(ufs, val, HCI_V2P1_CTRL); + } + val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); } diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index 0fc21b6bbfcd..acf07cc54684 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -222,6 +222,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) #define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6) +#define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7) }; #define for_each_ufs_rx_lane(ufs, i) \ -- 2.44.0.769.g3c40516874-goog