From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BBDA770F2; Tue, 30 Apr 2024 15:40:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714491639; cv=none; b=XiG/smNoEsPZhMXbQTrPcsU1l+YgO+njy8KA/uGioWIF6vCUcaIYJoIaRL9EnlSb1/U+n0oB3AbqgVw9iOMjTDEWmmGLLBgcaMSJquwv/JkIAVY69ie1KW2ntt50TfXbZL6R9BzIL5beSxZg5lON9m1vcmtyqNUv3qE2DOKR/Xg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714491639; c=relaxed/simple; bh=3YMP6pSgBBioceZpWJJBMi0WiZgs2qMWAZjRqieBRIk=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VEfDCz78md7DoBYtkrBk5dAgVV8UhDcj25UxAULurhlQ6sZ6/QVO0yg2Gh7X8LjYp4SgwNRVh2YzwFv7jB1XYaYfDVvpqYfv8ZLL4AiSJJa5YCnDcNrwpk6w80XT13NrtAafn4B5PpSwE2GVCrtsIVbjr/m8HoIwklNXuomM+BY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Asu18Cpb; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Asu18Cpb" Received: by mail.gandi.net (Postfix) with ESMTPSA id C3CD71BF207; Tue, 30 Apr 2024 15:40:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1714491629; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=o+cbSiCWqxupPEH7bg78CMjuOeT84VG73wF/YcMcoBg=; b=Asu18CpbZFU7KZq8qT6sXy2TVSu2PEKElKdAxkrvGU3+Z/X9VRq3ii8G/8YyictrIDuCTh rlTz5HRbXlhZPOLHfVNMEksHnkfieaypj8/AVwsMiLK/BmeUsNsfXIq3vqYsGEYchIt1qD kwf5Xe8qWczC40Ddi/DM1Y+MVw0Yu8VQBPxeoDamtNuhTkHXE9LQTjUSPcZL/Nt6+KFt2B avZf/aImihbeaH8tv20TcLrpTthuxQrrvI9JuUm/BOZReJ4bTW1mQj38LWUDCSIHvZr6F3 UXgL+HJGWG1b5kPauMm+s/BvrMiEPwVrx2HGSWaEsExoHbCsMDET/JPmX/Ty7A== Date: Tue, 30 Apr 2024 17:40:23 +0200 From: Herve Codina To: Andrew Lunn Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lee Jones , Arnd Bergmann , Horatiu Vultur , UNGLinuxDriver@microchip.com, Heiner Kallweit , Russell King , Saravana Kannan , Bjorn Helgaas , Philipp Zabel , Lars Povlsen , Steen Hegelund , Daniel Machon , Alexandre Belloni , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Allan Nielsen , Luca Ceresoli , Thomas Petazzoni Subject: Re: [PATCH 06/17] dt-bindings: net: mscc-miim: Add resets property Message-ID: <20240430174023.4d15a8a4@bootlin.com> In-Reply-To: <5d899584-38ed-4eee-9ba5-befdedbc5734@lunn.ch> References: <20240430083730.134918-1-herve.codina@bootlin.com> <20240430083730.134918-7-herve.codina@bootlin.com> <5d899584-38ed-4eee-9ba5-befdedbc5734@lunn.ch> Organization: Bootlin X-Mailer: Claws Mail 4.2.0 (GTK 3.24.41; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-GND-Sasl: herve.codina@bootlin.com Hi Andrew, On Tue, 30 Apr 2024 15:55:58 +0200 Andrew Lunn wrote: > On Tue, Apr 30, 2024 at 10:37:15AM +0200, Herve Codina wrote: > > Add the (optional) resets property. > > The mscc-miim device is impacted by the switch reset especially when the > > mscc-miim device is used as part of the LAN966x PCI device. > > > > Signed-off-by: Herve Codina > > --- > > Documentation/devicetree/bindings/net/mscc,miim.yaml | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/net/mscc,miim.yaml b/Documentation/devicetree/bindings/net/mscc,miim.yaml > > index 5b292e7c9e46..a8c92cec85a6 100644 > > --- a/Documentation/devicetree/bindings/net/mscc,miim.yaml > > +++ b/Documentation/devicetree/bindings/net/mscc,miim.yaml > > @@ -38,6 +38,14 @@ properties: > > > > clock-frequency: true > > > > + resets: > > + items: > > + - description: Reset controller used for switch core reset (soft reset) > > A follow up to the comment on the next patch. I think it should be > made clear in the patch and the binding, the aim is to reset the MDIO > bus master, not the switch. It just happens that the MDIO bus master > is within the domain of the switch core, and so the switch core reset > also resets the MDIO bus master. Exactly. > > Architecturally, this is important. I would not expect the MDIO driver > to be resetting the switch, the switch driver should be doing > that. But we have seen some odd Qualcomm patches where the MDIO driver > has been doing things outside the scope of MDIO, playing with resets > and clocks which are not directly related to the MDIO bus master. I > want to avoid any confusion here, especially when Qualcomm tries > again, and maybe points at this code. > Sure. We have the same construction with the pinctrl driver used in the LAN966x Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml The reset name is 'switch' in the pinctrl binding. I can use the same description here as the one present in the pinctrl binding: description: Optional shared switch reset. and keep 'switch' as reset name here (consistent with pinctrl reset name). What do you think about that ? Best regards, Hervé -- Hervé Codina, Bootlin Embedded Linux and Kernel engineering https://bootlin.com