Re: [PATCH v4 1/4] mips: bmips: rework and cache CBR addr handling

Florian Fainelli
2024-05-09T21:39:00Z

[-- Attachment #1: Type: text/plain, Size: 557 bytes --]

On 5/9/24 13:47, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
>
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
>
> bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with
> legacy brcm47xx/brcm63xx and generic BMIPS target.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
--
Florian

[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4221 bytes --]