From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Luca Weiss <luca.weiss@fairphone.com>
Subject: [PATCH v4 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks
Date: Sun, 12 May 2024 01:04:07 +0300 [thread overview]
Message-ID: <20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.org> (raw)
In-Reply-To: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org>
On the affected Qualcomm platforms the display clock controller has
additional DP input clocks, describe them in DT schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
index 59cc88a52f6b..5831579b572e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sm8350-dispcc
clocks:
+ minItems: 7
items:
- description: Board XO source
- description: Byte clock from DSI PHY0
@@ -35,8 +36,15 @@ properties:
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
+ - description: Link clock from eDP PHY
+ - description: VCO DIV clock from eDP PHY
+ - description: Link clock from DP1 PHY
+ - description: VCO DIV clock from DP1 PHY
+ - description: Link clock from DP2 PHY
+ - description: VCO DIV clock from DP2 PHY
clock-names:
+ minItems: 7
items:
- const: bi_tcxo
- const: dsi0_phy_pll_out_byteclk
@@ -45,6 +53,12 @@ properties:
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
+ - const: edp_phy_pll_link_clk
+ - const: edp_phy_pll_vco_div_clk
+ - const: dptx1_phy_pll_link_clk
+ - const: dptx1_phy_pll_vco_div_clk
+ - const: dptx2_phy_pll_link_clk
+ - const: dptx2_phy_pll_vco_div_clk
'#clock-cells':
const: 1
@@ -68,6 +82,20 @@ properties:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc8180x-dispcc
+ then:
+ properties:
+ clocks:
+ maxItems: 7
+ clock-names:
+ maxItems: 7
+
required:
- compatible
- reg
--
2.39.2
next prev parent reply other threads:[~2024-05-11 22:04 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-11 22:04 [PATCH v4 0/9] arm64: dts: qcom: fix description of the Type-C signals Dmitry Baryshkov
2024-05-11 22:04 ` Dmitry Baryshkov [this message]
2024-05-13 9:08 ` [PATCH v4 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks Krzysztof Kozlowski
2024-05-11 22:04 ` [PATCH v4 2/9] arm64: dts: qcom: sc8180x: correct dispcc clocks Dmitry Baryshkov
2024-05-11 22:04 ` [PATCH v4 3/9] arm64: dts: qcom: sm8250: describe HS signals properly Dmitry Baryshkov
2024-05-11 22:04 ` [PATCH v4 4/9] arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY Dmitry Baryshkov
2024-05-11 22:04 ` [PATCH v4 5/9] arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings Dmitry Baryshkov
2024-05-11 22:04 ` [PATCH v4 6/9] arm64: dts: qcom: sc8180x: describe USB signals properly Dmitry Baryshkov
2024-05-11 22:04 ` [PATCH v4 7/9] arm64: dts: qcom: sc8280xp: " Dmitry Baryshkov
2024-05-11 22:04 ` [PATCH v4 8/9] arm64: dts: qcom: x1e80100: " Dmitry Baryshkov
2024-05-11 22:04 ` [PATCH v4 9/9] arm64: dts: qcom: sm8150-hdk: rename Type-C HS endpoints Dmitry Baryshkov
2024-05-28 3:32 ` (subset) [PATCH v4 0/9] arm64: dts: qcom: fix description of the Type-C signals Bjorn Andersson
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