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Date: Mon, 13 May 2024 14:37:20 +0200
From: Herve Codina <herve.codina@bootlin.com>
To: Rob Herring <robh@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>, Krzysztof Kozlowski
 <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, "David S. Miller"
 <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski
 <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Lee Jones
 <lee@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Horatiu Vultur
 <horatiu.vultur@microchip.com>, UNGLinuxDriver@microchip.com, Andrew Lunn
 <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>, Russell King
 <linux@armlinux.org.uk>, Saravana Kannan <saravanak@google.com>, Bjorn
 Helgaas <bhelgaas@google.com>, Philipp Zabel <p.zabel@pengutronix.de>, Lars
 Povlsen <lars.povlsen@microchip.com>, Steen Hegelund
 <Steen.Hegelund@microchip.com>, Daniel Machon
 <daniel.machon@microchip.com>, Alexandre Belloni
 <alexandre.belloni@bootlin.com>, linux-kernel@vger.kernel.org,
 devicetree@vger.kernel.org, netdev@vger.kernel.org,
 linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Allan
 Nielsen <allan.nielsen@microchip.com>, Luca Ceresoli
 <luca.ceresoli@bootlin.com>, Thomas Petazzoni
 <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH 09/17] dt-bindings: interrupt-controller: Add support
 for Microchip LAN966x OIC
Message-ID: <20240513143720.1174306a@bootlin.com>
In-Reply-To: <20240507152806.GA505222-robh@kernel.org>
References: <20240430083730.134918-1-herve.codina@bootlin.com>
	<20240430083730.134918-10-herve.codina@bootlin.com>
	<20240507152806.GA505222-robh@kernel.org>
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X-GND-Sasl: herve.codina@bootlin.com

Hi Rob,

On Tue, 7 May 2024 10:28:06 -0500
Rob Herring <robh@kernel.org> wrote:

...
> > +examples:
> > +  - |
> > +    interrupt-controller@e00c0120 {
> > +        compatible = "microchip,lan966x-oic";
> > +        reg = <0xe00c0120 0x190>;  
> 
> Looks like this is part of some larger block?
> 

According to the registers information document:
  https://microchip-ung.github.io/lan9662_reginfo/reginfo_LAN9662.html?select=cpu,intr

The interrupt controller is mapped at offset 0x48 (offset in number of
32bit words).
-> Address offset: 0x48 * 4 = 0x120
-> size: (0x63 + 1) *  4 = 0x190

IMHO, the reg property value looks correct.

Best regards,
Hervé