From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64EAD15ADB6; Wed, 15 May 2024 18:52:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715799164; cv=none; b=tr65Eq+880gIHVyMZ+MUp4plhOEQIjlSbjfb1rK72DCCH3V+wz86q/eb+5m1fmCPRskJlL6V+ShjczNzu8yAM+jIoeceIYQaTuAlA8xa/jAZT8sUT+JWos0zt0kpcbyBlReDegucaAbiwuzoiSlGLV8F7kZZk/+5fYzeOGI7hLg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715799164; c=relaxed/simple; bh=oXhqMtB1Q9CCQXQJ3USVFEUF5oXFqNdWxV7yheTzfmE=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=oyJ4KbTX4L1GMl9kmij6V6vMovZljPQpHrGO8czyEIHbTTnTaS1WEVPukCW473jT0Lt5lhmUB9ndEFa+1Sl4gMtx1OZUySZIpi503oINme/QQE9lB9JrK2tsLkgHefZ6BBYih5PYShPR7igC5ZSy2epIBTUBCYHZBaCLMOVZJN0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gdtro8IG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gdtro8IG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A21DFC116B1; Wed, 15 May 2024 18:52:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715799163; bh=oXhqMtB1Q9CCQXQJ3USVFEUF5oXFqNdWxV7yheTzfmE=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=Gdtro8IGeuHC3mbYxSLKA/eOoXeVh3Pl94ZwCw5Fy55FkfL614rRhNtB4fWjrNolB 8YVaQRmpK855pYgzJmHA8biFzXZOpdgVnWl61xSGwAnq9Y+1k8AHZwWl1my8g4We6E jql3CJ6jIGnTNgMgDFVTcosMDmaCkDmimEj2ZItZ12vKc1XGKp+jZmhOHFaG3lmio4 KtIQsxUzrBwD8//aYNeYVXkeLla0qHtSKP+GnT+zwKTMcnf18sXfW+Ir6AydDwI9aD IgFu07RZLuTo5GmzXDXgMDUmHnWOFikXSpwD9vyOFF7caPRbf0WNZBR5i2QO95qsM6 widVINxqKxP4w== Date: Wed, 15 May 2024 13:52:41 -0500 From: Bjorn Helgaas To: Vidya Sagar Cc: Jean-Philippe Brucker , "will@kernel.org" , "lpieralisi@kernel.org" , "kw@linux.com" , "robh@kernel.org" , "bhelgaas@google.com" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "liviu.dudau@arm.com" , "sudeep.holla@arm.com" , "joro@8bytes.org" , "robin.murphy@arm.com" , Nicolin Chen , Ketan Patil , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "devicetree@vger.kernel.org" Subject: Re: [PATCH 0/3] Enable PCIe ATS for devicetree boot Message-ID: <20240515185241.GA2131384@bhelgaas> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, May 15, 2024 at 06:28:15PM +0000, Vidya Sagar wrote: > Thanks, Jean for this series. > May I know the current status of it? > Although it was actively reviewed, I see that its current status is set to > 'Handled Elsewhere' in https://patchwork.kernel.org/project/linux-pci/list/?series=848836&state=* > What is the plan to get this series accepted? I probably marked it "handled elsewhere" in the PCI patchwork because it doesn't touch PCI files (the binding has already been reviewed by Rob and Liviu), so I assumed the iommu folks would take the series. I don't know how they track patches. The merge window is open now, so likely they would wait until the next cycle so it would have some time in linux-next, but that's up to them. > > -----Original Message----- > > From: Jean-Philippe Brucker > > Sent: Monday, April 29, 2024 5:10 PM > > To: will@kernel.org; lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; > > bhelgaas@google.com; krzk+dt@kernel.org; conor+dt@kernel.org; > > liviu.dudau@arm.com; sudeep.holla@arm.com; joro@8bytes.org > > Cc: robin.murphy@arm.com; Nicolin Chen ; Ketan Patil > > ; linux-pci@vger.kernel.org; linux-arm- > > kernel@lists.infradead.org; iommu@lists.linux.dev; devicetree@vger.kernel.org; > > Jean-Philippe Brucker > > Subject: [PATCH 0/3] Enable PCIe ATS for devicetree boot > > > > External email: Use caution opening links or attachments > > > > > > Before enabling Address Translation Support (ATS) in endpoints, the OS needs to > > confirm that the Root Complex supports it. Obtain this information from the > > firmware description since there is no architected method. ACPI provides a bit via > > IORT tables, so add the devicetree equivalent. > > > > It was discussed a while ago [1], but at the time only a software model supported > > it. Respin it now that hardware is available [2]. > > > > To test this with the Arm RevC model, enable ATS in the endpoint and note that > > ATS is enabled. Address translation is transparent to the OS. > > > > -C pci.pcie_rc.ahci0.endpoint.ats_supported=1 > > > > $ lspci -s 00:1f.0 -vv > > Capabilities: [100 v1] Address Translation Service (ATS) > > ATSCap: Invalidate Queue Depth: 00 > > ATSCtl: Enable+, Smallest Translation Unit: 00 > > > > > > [1] https://lore.kernel.org/linux-iommu/20200213165049.508908-1-jean- > > philippe@linaro.org/ > > [2] https://lore.kernel.org/linux-arm-kernel/ZeJP6CwrZ2FSbTYm@Asurada- > > Nvidia/ > > > > Jean-Philippe Brucker (3): > > dt-bindings: PCI: generic: Add ats-supported property > > iommu/of: Support ats-supported device-tree property > > arm64: dts: fvp: Enable PCIe ATS for Base RevC FVP > > > > .../devicetree/bindings/pci/host-generic-pci.yaml | 6 ++++++ > > drivers/iommu/of_iommu.c | 9 +++++++++ > > arch/arm64/boot/dts/arm/fvp-base-revc.dts | 1 + > > 3 files changed, 16 insertions(+) > > > > -- > > 2.44.0 > > >