* [PATCH v1 0/3] Add the core reset for UARTs of StarFive JH7110
@ 2024-05-17 6:17 Hal Feng
2024-05-17 6:17 ` [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC Hal Feng
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Hal Feng @ 2024-05-17 6:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, Jiri Slaby,
Ilpo Järvinen, Philipp Zabel, Conor Dooley, Palmer Dabbelt,
Paul Walmsley, Albert Ou
Cc: Emil Renner Berthing, Hal Feng, devicetree, linux-serial,
linux-riscv, linux-kernel
The UART of StarFive JH7110 needs two reset signals (apb, core) to
initialize. This patch series adds the missing core reset.
Hal Feng (3):
dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for
StarFive JH7110 SoC
serial: 8250_dw: Use reset array API to get resets
riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible
for uarts
.../bindings/serial/snps-dw-apb-uart.yaml | 14 ++++++++-
arch/riscv/boot/dts/starfive/jh7110.dtsi | 30 +++++++++++--------
drivers/tty/serial/8250/8250_dw.c | 2 +-
3 files changed, 32 insertions(+), 14 deletions(-)
base-commit: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6
--
2.43.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC
2024-05-17 6:17 [PATCH v1 0/3] Add the core reset for UARTs of StarFive JH7110 Hal Feng
@ 2024-05-17 6:17 ` Hal Feng
2024-05-17 16:16 ` Conor Dooley
2024-05-17 6:17 ` [PATCH v1 2/3] serial: 8250_dw: Use reset array API to get resets Hal Feng
2024-05-17 6:17 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts Hal Feng
2 siblings, 1 reply; 6+ messages in thread
From: Hal Feng @ 2024-05-17 6:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, Jiri Slaby,
Ilpo Järvinen, Philipp Zabel, Conor Dooley, Palmer Dabbelt,
Paul Walmsley, Albert Ou
Cc: Emil Renner Berthing, Hal Feng, devicetree, linux-serial,
linux-riscv, linux-kernel
The UART of StarFive JH7110 has two reset signals.
Both of them are necessary for JH7110 to initialize UART.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../bindings/serial/snps-dw-apb-uart.yaml | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 1001d2a6ace8..a6396c5cbfb1 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -13,6 +13,16 @@ allOf:
- $ref: serial.yaml#
- $ref: rs485.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-uart
+ then:
+ properties:
+ resets:
+ minItems: 2
+
properties:
compatible:
oneOf:
@@ -48,6 +58,7 @@ properties:
- enum:
- starfive,jh7100-hsuart
- starfive,jh7100-uart
+ - starfive,jh7110-uart
- const: snps,dw-apb-uart
- const: snps,dw-apb-uart
@@ -82,7 +93,8 @@ properties:
type: boolean
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reg-shift: true
--
2.43.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 2/3] serial: 8250_dw: Use reset array API to get resets
2024-05-17 6:17 [PATCH v1 0/3] Add the core reset for UARTs of StarFive JH7110 Hal Feng
2024-05-17 6:17 ` [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC Hal Feng
@ 2024-05-17 6:17 ` Hal Feng
2024-05-17 6:17 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts Hal Feng
2 siblings, 0 replies; 6+ messages in thread
From: Hal Feng @ 2024-05-17 6:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, Jiri Slaby,
Ilpo Järvinen, Philipp Zabel, Conor Dooley, Palmer Dabbelt,
Paul Walmsley, Albert Ou
Cc: Emil Renner Berthing, Hal Feng, devicetree, linux-serial,
linux-riscv, linux-kernel
Some SoCs like StarFive JH7110 require two or more resets.
So change to use the reset array API to get resets.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/tty/serial/8250/8250_dw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 1300c92b8702..425a63b67f1d 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -597,7 +597,7 @@ static int dw8250_probe(struct platform_device *pdev)
if (IS_ERR(data->pclk))
return PTR_ERR(data->pclk);
- data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
+ data->rst = devm_reset_control_array_get_optional_exclusive(dev);
if (IS_ERR(data->rst))
return PTR_ERR(data->rst);
--
2.43.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts
2024-05-17 6:17 [PATCH v1 0/3] Add the core reset for UARTs of StarFive JH7110 Hal Feng
2024-05-17 6:17 ` [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC Hal Feng
2024-05-17 6:17 ` [PATCH v1 2/3] serial: 8250_dw: Use reset array API to get resets Hal Feng
@ 2024-05-17 6:17 ` Hal Feng
2 siblings, 0 replies; 6+ messages in thread
From: Hal Feng @ 2024-05-17 6:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, Jiri Slaby,
Ilpo Järvinen, Philipp Zabel, Conor Dooley, Palmer Dabbelt,
Paul Walmsley, Albert Ou
Cc: Emil Renner Berthing, Hal Feng, devicetree, linux-serial,
linux-riscv, linux-kernel
Add the core reset for uarts, which is necessary for uarts to work.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 30 ++++++++++++++----------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4a5708f7fcf7..872f52253a2e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -387,12 +387,13 @@ plic: interrupt-controller@c000000 {
};
uart0: serial@10000000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x10000000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
<&syscrg JH7110_SYSCLK_UART0_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART0_APB>,
+ <&syscrg JH7110_SYSRST_UART0_CORE>;
interrupts = <32>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -400,12 +401,13 @@ uart0: serial@10000000 {
};
uart1: serial@10010000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x10010000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
<&syscrg JH7110_SYSCLK_UART1_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART1_APB>,
+ <&syscrg JH7110_SYSRST_UART1_CORE>;
interrupts = <33>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -413,12 +415,13 @@ uart1: serial@10010000 {
};
uart2: serial@10020000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x10020000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
<&syscrg JH7110_SYSCLK_UART2_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART2_APB>,
+ <&syscrg JH7110_SYSRST_UART2_CORE>;
interrupts = <34>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -642,12 +645,13 @@ stg_syscon: syscon@10240000 {
};
uart3: serial@12000000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
<&syscrg JH7110_SYSCLK_UART3_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART3_APB>,
+ <&syscrg JH7110_SYSRST_UART3_CORE>;
interrupts = <45>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -655,12 +659,13 @@ uart3: serial@12000000 {
};
uart4: serial@12010000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x12010000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
<&syscrg JH7110_SYSCLK_UART4_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART4_APB>,
+ <&syscrg JH7110_SYSRST_UART4_CORE>;
interrupts = <46>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -668,12 +673,13 @@ uart4: serial@12010000 {
};
uart5: serial@12020000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x12020000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
<&syscrg JH7110_SYSCLK_UART5_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART5_APB>,
+ <&syscrg JH7110_SYSRST_UART5_CORE>;
interrupts = <47>;
reg-io-width = <4>;
reg-shift = <2>;
--
2.43.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC
2024-05-17 6:17 ` [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC Hal Feng
@ 2024-05-17 16:16 ` Conor Dooley
2024-05-20 2:06 ` Hal Feng
0 siblings, 1 reply; 6+ messages in thread
From: Conor Dooley @ 2024-05-17 16:16 UTC (permalink / raw)
To: Hal Feng
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, Jiri Slaby,
Ilpo Järvinen, Philipp Zabel, Conor Dooley, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Emil Renner Berthing, devicetree,
linux-serial, linux-riscv, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1753 bytes --]
On Fri, May 17, 2024 at 02:17:11PM +0800, Hal Feng wrote:
> The UART of StarFive JH7110 has two reset signals.
> Both of them are necessary for JH7110 to initialize UART.
>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../bindings/serial/snps-dw-apb-uart.yaml | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> index 1001d2a6ace8..a6396c5cbfb1 100644
> --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> @@ -13,6 +13,16 @@ allOf:
> - $ref: serial.yaml#
> - $ref: rs485.yaml#
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-uart
> + then:
> + properties:
> + resets:
> + minItems: 2
else:
properties:
resets:
maxItems: 1
Thanks,
Conor.
> +
> properties:
> compatible:
> oneOf:
> @@ -48,6 +58,7 @@ properties:
> - enum:
> - starfive,jh7100-hsuart
> - starfive,jh7100-uart
> + - starfive,jh7110-uart
> - const: snps,dw-apb-uart
> - const: snps,dw-apb-uart
>
> @@ -82,7 +93,8 @@ properties:
> type: boolean
>
> resets:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> reg-shift: true
>
> --
> 2.43.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC
2024-05-17 16:16 ` Conor Dooley
@ 2024-05-20 2:06 ` Hal Feng
0 siblings, 0 replies; 6+ messages in thread
From: Hal Feng @ 2024-05-20 2:06 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman, Jiri Slaby,
Ilpo Järvinen, Philipp Zabel, Conor Dooley, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Emil Renner Berthing,
devicetree@vger.kernel.org, linux-serial@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
> On 18.05.24 00:17, Conor Dooley wrote:
> On Fri, May 17, 2024 at 02:17:11PM +0800, Hal Feng wrote:
> > The UART of StarFive JH7110 has two reset signals.
> > Both of them are necessary for JH7110 to initialize UART.
> >
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > .../bindings/serial/snps-dw-apb-uart.yaml | 14 +++++++++++++-
> > 1 file changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> > index 1001d2a6ace8..a6396c5cbfb1 100644
> > --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> > +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> > @@ -13,6 +13,16 @@ allOf:
> > - $ref: serial.yaml#
> > - $ref: rs485.yaml#
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: starfive,jh7110-uart
> > + then:
> > + properties:
> > + resets:
> > + minItems: 2
>
> else:
> properties:
> resets:
> maxItems: 1
Will fix it later. Thanks for your review.
Best regards,
Hal
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-05-20 2:21 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2024-05-17 6:17 [PATCH v1 0/3] Add the core reset for UARTs of StarFive JH7110 Hal Feng
2024-05-17 6:17 ` [PATCH v1 1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC Hal Feng
2024-05-17 16:16 ` Conor Dooley
2024-05-20 2:06 ` Hal Feng
2024-05-17 6:17 ` [PATCH v1 2/3] serial: 8250_dw: Use reset array API to get resets Hal Feng
2024-05-17 6:17 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts Hal Feng
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