From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-185.mta0.migadu.com (out-185.mta0.migadu.com [91.218.175.185]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8625C1369A7 for ; Mon, 20 May 2024 14:54:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.185 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716216858; cv=none; b=elKhvgx5vXBW9OyqRMhXnI9wbbO2i8fN4e8J0PPWmgmOAkWz9P/u75riFWc8fCHJwVa3ZDBUCdjDdzIooSrnizduDLwMDzLdIQXZUKeKbENexuIT0zWWLwuTW9qKmxFbFnlwAC8jSme6lX1cJAQfs61aJRn5sIx+PDuUzl8/TuY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716216858; c=relaxed/simple; bh=sHuVMqOOOz9XO4IshcQZEwhXzzhogGCT5T+bmtChve0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=E2vPohBP0LGEVdRW7/aricE/r1zJ25rsoLT7Ic1M+9wfN/6pnbWYxvTNuXyFwCtD6H/UnheW4v39+HmVw4Kiks64DuT3Nrz2bjlENuuu5nIbtSXwx1Zq6xC3YdvmfdVs6n/PPLx4WxzWT8LpBwKpAeaTiF5NeSvPKFqeT2DHvIo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=d09pMeOY; arc=none smtp.client-ip=91.218.175.185 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="d09pMeOY" X-Envelope-To: lpieralisi@kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1716216854; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0TZ3BGmEu8mVwpdyswgFBs/ct4xyk7TF2NGi7rztXsU=; b=d09pMeOYiWVnrY3txO33VLyO8lPiZDqCbW6nnx1MgKYzNfA7HqMxY6eRxGmcAVt+xvUuLr HJaMZwbY43vTCCVFZNqFMo0SGjrWVZyBsNQKtRnylcNqWD/4VhGRLaMgLvshkFuswYgckK JKBUlXWHl5h6LN9mcvgc7bixP3ltZMI= X-Envelope-To: kw@linux.com X-Envelope-To: robh@kernel.org X-Envelope-To: linux-pci@vger.kernel.org X-Envelope-To: michal.simek@amd.com X-Envelope-To: thippeswamy.havalige@amd.com X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: bhelgaas@google.com X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: sean.anderson@linux.dev X-Envelope-To: conor+dt@kernel.org X-Envelope-To: krzysztof.kozlowski+dt@linaro.org X-Envelope-To: devicetree@vger.kernel.org X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org Cc: Michal Simek , Thippeswamy Havalige , linux-arm-kernel@lists.infradead.org, Bjorn Helgaas , linux-kernel@vger.kernel.org, Sean Anderson , Conor Dooley , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: pci: xilinx-nwl: Add phys Date: Mon, 20 May 2024 10:53:56 -0400 Message-Id: <20240520145402.2526481-2-sean.anderson@linux.dev> In-Reply-To: <20240520145402.2526481-1-sean.anderson@linux.dev> References: <20240520145402.2526481-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Add phys properties so Linux can power-on/configure the GTR transcievers. Signed-off-by: Sean Anderson --- Changes in v3: - Document phys property Changes in v2: - Remove phy-names - Add an example Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 426f90a47f35..cc50795d170b 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -61,6 +61,11 @@ properties: interrupt-map: maxItems: 4 + phys: + minItems: 1 + maxItems: 4 + description: One phy per logical lane, in order + power-domains: maxItems: 1 @@ -110,6 +115,7 @@ examples: - | #include #include + #include #include soc { #address-cells = <2>; @@ -138,6 +144,7 @@ examples: <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; msi-parent = <&nwl_pcie>; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; power-domains = <&zynqmp_firmware PD_PCIE>; iommus = <&smmu 0x4d0>; pcie_intc: legacy-interrupt-controller { -- 2.35.1.1320.gc452695387.dirty