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Tue, 21 May 2024 13:30:47 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5238ec18fd2sm2538664e87.155.2024.05.21.13.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 13:30:47 -0700 (PDT) From: Dmitry Baryshkov Subject: [PATCH 0/2] phy: qcom: qmp-pcie: drop second clock-output-names entry Date: Tue, 21 May 2024 23:30:44 +0300 Message-Id: <20240521-fix-pcie-phy-compat-v1-0-8aa415b92308@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAHUETWYC/x2MywqAIBAAf0X23IKKdehXooOPrfaQikYU0b8nH Qdm5oFKhanCKB4odHLlFBuoToDfbFwJOTQGLbWRvVa48IXZM2HebvRpz/ZAJ5dgyJnBBQutzIW a9l+n+X0//fGiKGUAAAA= To: Vinod Koul , Kishon Vijay Abraham I , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1150; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=M+EhpWdi/uciO0AorqL0bUSVVqrzDF3BrW557EWnWVE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmTQR2U2rXolmbrWdg8e6wAttQMImRrg1Pyc9ok rA28n9AO4aJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZk0EdgAKCRCLPIo+Aiko 1SnkB/9cgUDX95JWEa0NHEJK8aRFtxpKZu8Khyq4djF+wMNkIMUC5ekxB3tsfX3XFRIPOWnRVae /8vFprf0JoufRr0eGnI8wUGaHk8IiUnTaG3+sQEO9Keeb9XtID/F1vKtdDnLIKaLB7z8jlv1QRS ycPHorVLVHnIDpaSv17XxpgHH2VQACIq+hCq3ZfirI+Ls15bXa7DChLR4UuE6tO1bBaQ7OTcxIv TKfS5ZNss0NebfRxaO1SgSAHEWKnXZUg3z5VuXM+FAQ580TdP3G0BuqL8/joVgCNG0FwodhUxWu 0VtEBDMKL8Hul34ot1vmadPpod5f9PYtGaHh+GqIdbZM1Bs1 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A While testing the linux-next on SM8450-HDK I noticed that one of the PCIe hosts stays in the deferred state, because the corresponding PHY isn't probed. A quick debug pointed out that while the patches that added support for the PIPE AUX clock to the PHY driver have landed, corresponding DT changes were not picked up for 6.10. Restore the compatibility with the existing DT files by dropping the second entry in the clock-output-names array and always generating the corresponding name on the fly. Signed-off-by: Dmitry Baryshkov --- Dmitry Baryshkov (2): phy: qcom: qmp-pcie: restore compatibility with existing DTs dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: drop second output clock name .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 +------ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------ 2 files changed, 4 insertions(+), 12 deletions(-) --- base-commit: 632483ea8004edfadd035de36e1ab2c7c4f53158 change-id: 20240521-fix-pcie-phy-compat-b0fd4eb46bda Best regards, -- Dmitry Baryshkov