[PATCH v2 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc

[PATCH v2 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc

[Kanak Shilledar]

This series of patches converts the RISC-V CPU interrupt controller to
the newer dt-schema binding.

Patch 1:
This patch is currently at v3 as it has been previously rolled out.
Contains the bindings for the interrupt controller.

Patch 2:
This patch is currently at v2.
Contains the reference to the above interrupt controller. Thus, making
all the RISC-V interrupt controller bindings in a centralized place.

These patches are interdependent.

Kanak Shilledar (2):
  dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
  dt-bindings: riscv: cpus: add ref to interrupt-controller

 .../interrupt-controller/riscv,cpu-intc.txt   | 52 -------------
 .../interrupt-controller/riscv,cpu-intc.yaml  | 73 +++++++++++++++++++
 .../devicetree/bindings/riscv/cpus.yaml       | 21 +-----
 3 files changed, 74 insertions(+), 72 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml


base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23
-- 
2.34.1

[PATCH v3 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema

[Kanak Shilledar]

Convert the RISC-V Hart-Level Interrupt Controller (HLIC) to newer
DT schema, Created DT schema based on the .txt file which had
`compatible`, `#interrupt-cells` and `interrupt-controller` as
required properties.
Changes made with respect to original file:
- Changed the example to just use interrupt-controller instead of
using the whole cpu block
- Changed the example compatible string.

Signed-off-by: Kanak Shilledar <kanakshilledar111@protonmail.com>
---
Changes in v3:
- Remove reference to `interrupt-controller` in `riscv/cpus.yaml`.
---
Changes in v2:
- Update the maintainers list.
- Add reference to `interrupt-controller` in `riscv/cpus.yaml`.
- Update compatible property with the reference in `cpus.yaml`.
- Include description for '#interrupt-cells' property.
- Change '#interrupt-cells' property to have `const: 1` as per the
text binding.
- Fixed the warning thrown by `/renesas/r9a07g043f01-smarc.dtb`.
---
 .../interrupt-controller/riscv,cpu-intc.txt   | 52 -------------
 .../interrupt-controller/riscv,cpu-intc.yaml  | 73 +++++++++++++++++++
 2 files changed, 73 insertions(+), 52 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
deleted file mode 100644
index 265b223cd978..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-RISC-V Hart-Level Interrupt Controller (HLIC)
----------------------------------------------
-
-RISC-V cores include Control Status Registers (CSRs) which are local to each
-CPU core (HART in RISC-V terminology) and can be read or written by software.
-Some of these CSRs are used to control local interrupts connected to the core.
-Every interrupt is ultimately routed through a hart's HLIC before it
-interrupts that hart.
-
-The RISC-V supervisor ISA manual specifies three interrupt sources that are
-attached to every HLIC: software interrupts, the timer interrupt, and external
-interrupts.  Software interrupts are used to send IPIs between cores.  The
-timer interrupt comes from an architecturally mandated real-time timer that is
-controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External
-interrupts connect all other device interrupts to the HLIC, which are routed
-via the platform-level interrupt controller (PLIC).
-
-All RISC-V systems that conform to the supervisor ISA specification are
-required to have a HLIC with these three interrupt sources present.  Since the
-interrupt map is defined by the ISA it's not listed in the HLIC's device tree
-entry, though external interrupt controllers (like the PLIC, for example) will
-need to define how their interrupts map to the relevant HLICs.  This means
-a PLIC interrupt property will typically list the HLICs for all present HARTs
-in the system.
-
-Required properties:
-- compatible : "riscv,cpu-intc"
-- #interrupt-cells : should be <1>.  The interrupt sources are defined by the
-  RISC-V supervisor ISA manual, with only the following three interrupts being
-  defined for supervisor mode:
-    - Source 1 is the supervisor software interrupt, which can be sent by an SBI
-      call and is reserved for use by software.
-    - Source 5 is the supervisor timer interrupt, which can be configured by
-      SBI calls and implements a one-shot timer.
-    - Source 9 is the supervisor external interrupt, which chains to all other
-      device interrupts.
-- interrupt-controller : Identifies the node as an interrupt controller
-
-Furthermore, this interrupt-controller MUST be embedded inside the cpu
-definition of the hart whose CSRs control these local interrupts.
-
-An example device tree entry for a HLIC is show below.
-
-	cpu1: cpu@1 {
-		compatible = "riscv";
-		...
-		cpu1-intc: interrupt-controller {
-			#interrupt-cells = <1>;
-			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
-			interrupt-controller;
-		};
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
new file mode 100644
index 000000000000..c9c79e0870ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Hart-Level Interrupt Controller (HLIC)
+
+description:
+  RISC-V cores include Control Status Registers (CSRs) which are local to
+  each CPU core (HART in RISC-V terminology) and can be read or written by
+  software. Some of these CSRs are used to control local interrupts connected
+  to the core. Every interrupt is ultimately routed through a hart's HLIC
+  before it interrupts that hart.
+
+  The RISC-V supervisor ISA manual specifies three interrupt sources that are
+  attached to every HLIC namely software interrupts, the timer interrupt, and
+  external interrupts. Software interrupts are used to send IPIs between
+  cores.  The timer interrupt comes from an architecturally mandated real-
+  time timer that is controlled via Supervisor Binary Interface (SBI) calls
+  and CSR reads. External interrupts connect all other device interrupts to
+  the HLIC, which are routed via the platform-level interrupt controller
+  (PLIC).
+
+  All RISC-V systems that conform to the supervisor ISA specification are
+  required to have a HLIC with these three interrupt sources present.  Since
+  the interrupt map is defined by the ISA it's not listed in the HLIC's device
+  tree entry, though external interrupt controllers (like the PLIC, for
+  example) will need to define how their interrupts map to the relevant HLICs.
+  This means a PLIC interrupt property will typically list the HLICs for all
+  present HARTs in the system.
+
+maintainers:
+  - Palmer Dabbelt <palmer@dabbelt.com>
+  - Paul Walmsley <paul.walmsley@sifive.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: andestech,cpu-intc
+          - const: riscv,cpu-intc
+      - const: riscv,cpu-intc
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 1
+    description: |
+      The interrupt sources are defined by the RISC-V supervisor ISA manual,
+      with only the following three interrupts being defined for
+      supervisor mode:
+        - Source 1 is the supervisor software interrupt, which can be sent by
+          an SBI call and is reserved for use by software.
+        - Source 5 is the supervisor timer interrupt, which can be configured
+          by SBI calls and implements a one-shot timer.
+        - Source 9 is the supervisor external interrupt, which chains to all
+          other device interrupts.
+
+required:
+  - compatible
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+examples:
+  - |
+    interrupt-controller {
+        #interrupt-cells = <1>;
+        compatible = "riscv,cpu-intc";
+        interrupt-controller;
+    };
-- 
2.34.1

[PATCH v2 2/2] dt-bindings: riscv: cpus: add ref to interrupt-controller

[Kanak Shilledar]

removed the redundant properties for interrupt-controller
and provide reference to the riscv,cpu-intc.yaml which defines
the interrupt-controller. making the properties for riscv
interrupt-controller at a central place.

Signed-off-by: Kanak Shilledar <kanakshilledar111@protonmail.com>
---
Changes in v2:
- Fix warning of `type` is a required property during `make
dt_bindings_check`.
---
 .../devicetree/bindings/riscv/cpus.yaml       | 21 +------------------
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d87dd50f1a4b..f1241e5e8753 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -102,26 +102,7 @@ properties:
 
   interrupt-controller:
     type: object
-    additionalProperties: false
-    description: Describes the CPU's local interrupt controller
-
-    properties:
-      '#interrupt-cells':
-        const: 1
-
-      compatible:
-        oneOf:
-          - items:
-              - const: andestech,cpu-intc
-              - const: riscv,cpu-intc
-          - const: riscv,cpu-intc
-
-      interrupt-controller: true
-
-    required:
-      - '#interrupt-cells'
-      - compatible
-      - interrupt-controller
+    $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
 
   cpu-idle-states:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-- 
2.34.1

Re: [PATCH v2 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc

[Conor Dooley]

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On Wed, May 22, 2024 at 09:08:34PM +0530, Kanak Shilledar wrote:
> This series of patches converts the RISC-V CPU interrupt controller to
> the newer dt-schema binding.
> 
> Patch 1:
> This patch is currently at v3 as it has been previously rolled out.
> Contains the bindings for the interrupt controller.
> 
> Patch 2:
> This patch is currently at v2.
> Contains the reference to the above interrupt controller. Thus, making
> all the RISC-V interrupt controller bindings in a centralized place.o

Don't do this, it breaks tooling:

	b4 shazam 20240522153835.22712-2-kanakshilledar111@protonmail.com
	Grabbing thread from lore.kernel.org/all/20240522153835.22712-2-kanakshilledar111@protonmail.com/t.mbox.gz
	Checking for newer revisions
	Grabbing search results from lore.kernel.org
	Analyzing 3 messages in the thread
	Looking for additional code-review trailers on lore.kernel.org
	Will use the latest revision: v3
	You can pick other revisions using the -vN flag
	Checking attestation on all messages, may take a moment...
	Retrieving CI status, may take a moment...
	---
	  ✓ [PATCH v3 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
	    ✓ Signed: DKIM/gmail.com
	    + Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
	  ERROR: missing [2/2]!
	---
	Total patches: 1
	---
	WARNING: Thread incomplete!
	 Base: using specified base-commit 20cb38a7af88dc40095da7c2c9094da3873fea23
	Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema

If you change one patch in a series, the whole series gets a new version.
Just let git format-patch do that for you with the "-v N" argument and
you'll not have to worry about breaking people's tooling.

Patches themselves are
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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Re: [PATCH v2 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc

[Kanak Shilledar]

Hi Conor,

On Wed, May 22, 2024 at 9:34 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Wed, May 22, 2024 at 09:08:34PM +0530, Kanak Shilledar wrote:
> > This series of patches converts the RISC-V CPU interrupt controller to
> > the newer dt-schema binding.
> >
> > Patch 1:
> > This patch is currently at v3 as it has been previously rolled out.
> > Contains the bindings for the interrupt controller.
> >
> > Patch 2:
> > This patch is currently at v2.
> > Contains the reference to the above interrupt controller. Thus, making
> > all the RISC-V interrupt controller bindings in a centralized place.o
>
> Don't do this, it breaks tooling:
>
>         b4 shazam 20240522153835.22712-2-kanakshilledar111@protonmail.com
>         Grabbing thread from lore.kernel.org/all/20240522153835.22712-2-kanakshilledar111@protonmail.com/t.mbox.gz
>         Checking for newer revisions
>         Grabbing search results from lore.kernel.org
>         Analyzing 3 messages in the thread
>         Looking for additional code-review trailers on lore.kernel.org
>         Will use the latest revision: v3
>         You can pick other revisions using the -vN flag
>         Checking attestation on all messages, may take a moment...
>         Retrieving CI status, may take a moment...
>         ---
>           ✓ [PATCH v3 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
>             ✓ Signed: DKIM/gmail.com
>             + Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>           ERROR: missing [2/2]!
>         ---
>         Total patches: 1
>         ---
>         WARNING: Thread incomplete!
>          Base: using specified base-commit 20cb38a7af88dc40095da7c2c9094da3873fea23
>         Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
>
> If you change one patch in a series, the whole series gets a new version.
> Just let git format-patch do that for you with the "-v N" argument and
> you'll not have to worry about breaking people's tooling.

Sorry for the tooling breaking. I used the "-v N" argument to make the
v2 patches but I bumped up the "riscv,cpu-intc"patch
to v3 due to it being in v3 already and it gave errors in the previous
patchset and you mentioned that I missed the v3 in subject line.
How shall I proceed with this version mismatch? Shall I make the
patchset as v3 and have both the patches at v3?

> Patches themselves are
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

I shall include this in my commit message. Is it required to bump the
version of the patch just for the reviewed flag?

> Cheers,
> Conor.

Thanks and Regards,
Kanak Shilledar

Re: [PATCH v2 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3069 bytes --]

On Wed, May 22, 2024 at 10:11:20PM +0530, Kanak Shilledar wrote:
> Hi Conor,
> 
> On Wed, May 22, 2024 at 9:34 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, May 22, 2024 at 09:08:34PM +0530, Kanak Shilledar wrote:
> > > This series of patches converts the RISC-V CPU interrupt controller to
> > > the newer dt-schema binding.
> > >
> > > Patch 1:
> > > This patch is currently at v3 as it has been previously rolled out.
> > > Contains the bindings for the interrupt controller.
> > >
> > > Patch 2:
> > > This patch is currently at v2.
> > > Contains the reference to the above interrupt controller. Thus, making
> > > all the RISC-V interrupt controller bindings in a centralized place.o
> >
> > Don't do this, it breaks tooling:
> >
> >         b4 shazam 20240522153835.22712-2-kanakshilledar111@protonmail.com
> >         Grabbing thread from lore.kernel.org/all/20240522153835.22712-2-kanakshilledar111@protonmail.com/t.mbox.gz
> >         Checking for newer revisions
> >         Grabbing search results from lore.kernel.org
> >         Analyzing 3 messages in the thread
> >         Looking for additional code-review trailers on lore.kernel.org
> >         Will use the latest revision: v3
> >         You can pick other revisions using the -vN flag
> >         Checking attestation on all messages, may take a moment...
> >         Retrieving CI status, may take a moment...
> >         ---
> >           ✓ [PATCH v3 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
> >             ✓ Signed: DKIM/gmail.com
> >             + Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >           ERROR: missing [2/2]!
> >         ---
> >         Total patches: 1
> >         ---
> >         WARNING: Thread incomplete!
> >          Base: using specified base-commit 20cb38a7af88dc40095da7c2c9094da3873fea23
> >         Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
> >
> > If you change one patch in a series, the whole series gets a new version.
> > Just let git format-patch do that for you with the "-v N" argument and
> > you'll not have to worry about breaking people's tooling.
> 
> Sorry for the tooling breaking. I used the "-v N" argument to make the
> v2 patches but I bumped up the "riscv,cpu-intc"patch
> to v3 due to it being in v3 already and it gave errors in the previous
> patchset and you mentioned that I missed the v3 in subject line.
> How shall I proceed with this version mismatch? Shall I make the
> patchset as v3 and have both the patches at v3?

I would make it "RESEND v3".

> > Patches themselves are
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> I shall include this in my commit message. Is it required to bump the
> version of the patch just for the reviewed flag?

Usually there's no need to resend patches for tags alone. Some people
treat tag-only resubmissions as a "RESEND vN" and others as "vN+1". The
latter is less likely to upset anyone.

Cheers,
Conor.

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