Re: [PATCH 3/3] dt-bindings: display: vop2: Add VP clock resets

Conor Dooley
2024-05-15T16:19:36Z

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On Tue, May 14, 2024 at 11:19:47AM -0400, Detlev Casanova wrote:
> Add the documentation for VOP2 video ports reset clocks.
> One reset can be set per video port.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>

Are these resets valid for all VOPs or just the one on 3588?

> ---
> .../display/rockchip/rockchip-vop2.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> index 2531726af306b..941fd059498d4 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> @@ -65,6 +65,22 @@ properties:
> - const: dclk_vp3
> - const: pclk_vop
>
> + resets:
> + minItems: 3
> + items:
> + - description: Pixel clock reset for video port 0.
> + - description: Pixel clock reset for video port 1.
> + - description: Pixel clock reset for video port 2.
> + - description: Pixel clock reset for video port 3.
> +
> + reset-names:
> + minItems: 3
> + items:
> + - const: dclk_vp0
> + - const: dclk_vp1
> + - const: dclk_vp2
> + - const: dclk_vp3
> +
> rockchip,grf:
> $ref: /schemas/types.yaml#/definitions/phandle
> description:
> @@ -128,6 +144,11 @@ allOf:
> clock-names:
> minItems: 7
>
> + resets:
> + minItems: 4
> + reset-names:
> + minItems: 4
> +
> ports:
> required:
> - port@0
> @@ -183,6 +204,12 @@ examples:
> "dclk_vp0",
> "dclk_vp1",
> "dclk_vp2";
> + resets = <&cru SRST_VOP0>,
> + <&cru SRST_VOP1>,
> + <&cru SRST_VOP2>;
> + reset-names = "dclk_vp0",
> + "dclk_vp1",
> + "dclk_vp2";
> power-domains = <&power RK3568_PD_VO>;
> iommus = <&vop_mmu>;
> vop_out: ports {
> --
> 2.43.2
>

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