From: Andrew Jones <ajones@ventanamicro.com>
To: Tomasz Jeznach <tjeznach@rivosinc.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <apatel@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Nick Kossifidis <mick@ics.forth.gr>,
Sebastien Boeuf <seb@rivosinc.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, iommu@lists.linux.dev,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux@rivosinc.com, Lu Baolu <baolu.lu@linux.intel.com>
Subject: Re: [PATCH v6 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver
Date: Thu, 30 May 2024 10:20:18 +0200 [thread overview]
Message-ID: <20240530-af20943d2b372faa7b11ed41@orel> (raw)
In-Reply-To: <CAH2o1u7DmywajQWRnQEW2Zjw95EzruM3_Mb5Z-K4zJChh8pGLQ@mail.gmail.com>
On Wed, May 29, 2024 at 10:59:58AM GMT, Tomasz Jeznach wrote:
> On Wed, May 29, 2024 at 8:15 AM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > Hi Tomasz,
> >
> > I reviewed iommu-bits.h to the spec. Most naming matches exactly, which
> > is nice, but I've pointed out a few which don't.
> >
> > Thanks,
> > drew
> >
>
> Thanks for looking into this a bit boring file.
No problem. I also meant to point out that I checked all bits/offsets as
well. They all looked good to me.
...
> > > +enum riscv_iommu_fq_ttypes {
> > > + RISCV_IOMMU_FQ_TTYPE_NONE = 0,
> > > + RISCV_IOMMU_FQ_TTYPE_UADDR_INST_FETCH = 1,
> > > + RISCV_IOMMU_FQ_TTYPE_UADDR_RD = 2,
> > > + RISCV_IOMMU_FQ_TTYPE_UADDR_WR = 3,
> > > + RISCV_IOMMU_FQ_TTYPE_TADDR_INST_FETCH = 5,
> > > + RISCV_IOMMU_FQ_TTYPE_TADDR_RD = 6,
> > > + RISCV_IOMMU_FQ_TTYPE_TADDR_WR = 7,
> > > + RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ = 8,
> > > + RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9,
> > > +};
> >
> > RISCV_IOMMU_FW_TTYP_* for all above
> >
>
> I guess RISCV_IOMMU_FQ_TTYP_* to match _FQ_ acronym.
Oh yeah. I guess my eyes had glazed over at this point because I didn't
notice the 'FW' vs. 'FQ'. So, yeah, we want RISCV_IOMMU_FQ_TTYP_* for all
above, including RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ.
Thanks,
drew
next prev parent reply other threads:[~2024-05-30 8:20 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-24 19:34 [PATCH v6 0/7] Linux RISC-V IOMMU Support Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver Tomasz Jeznach
2024-05-29 15:15 ` Andrew Jones
2024-05-29 17:59 ` Tomasz Jeznach
2024-05-30 8:20 ` Andrew Jones [this message]
2024-06-03 12:53 ` Andrew Jones
2024-06-05 18:58 ` Tomasz Jeznach
2024-06-06 6:54 ` Andrew Jones
2024-06-03 12:59 ` Andrew Jones
2024-06-05 19:41 ` Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 3/7] iommu/riscv: Add RISC-V IOMMU PCIe " Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 4/7] iommu/riscv: Enable IOMMU registration and device probe Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 5/7] iommu/riscv: Device directory management Tomasz Jeznach
2024-05-31 6:25 ` Zong Li
2024-06-10 17:49 ` Jason Gunthorpe
2024-06-10 18:48 ` Tomasz Jeznach
2024-06-10 22:20 ` Jason Gunthorpe
2024-06-11 2:00 ` Tomasz Jeznach
2024-06-11 12:12 ` Jason Gunthorpe
2024-05-24 19:34 ` [PATCH v6 6/7] iommu/riscv: Command and fault queue support Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 7/7] iommu/riscv: Paging domain support Tomasz Jeznach
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