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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4212708a6fbsm17283305e9.44.2024.05.30.01.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 01:20:19 -0700 (PDT) Date: Thu, 30 May 2024 10:20:18 +0200 From: Andrew Jones To: Tomasz Jeznach Cc: Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Sunil V L , Nick Kossifidis , Sebastien Boeuf , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com, Lu Baolu Subject: Re: [PATCH v6 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver Message-ID: <20240530-af20943d2b372faa7b11ed41@orel> References: <7dcd9a154625704cbf9adc4b4ac07ca0b9753b31.1716578450.git.tjeznach@rivosinc.com> <20240529-08fd52a8e703418142bdfa84@orel> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, May 29, 2024 at 10:59:58AM GMT, Tomasz Jeznach wrote: > On Wed, May 29, 2024 at 8:15 AM Andrew Jones wrote: > > > > Hi Tomasz, > > > > I reviewed iommu-bits.h to the spec. Most naming matches exactly, which > > is nice, but I've pointed out a few which don't. > > > > Thanks, > > drew > > > > Thanks for looking into this a bit boring file. No problem. I also meant to point out that I checked all bits/offsets as well. They all looked good to me. ... > > > +enum riscv_iommu_fq_ttypes { > > > + RISCV_IOMMU_FQ_TTYPE_NONE = 0, > > > + RISCV_IOMMU_FQ_TTYPE_UADDR_INST_FETCH = 1, > > > + RISCV_IOMMU_FQ_TTYPE_UADDR_RD = 2, > > > + RISCV_IOMMU_FQ_TTYPE_UADDR_WR = 3, > > > + RISCV_IOMMU_FQ_TTYPE_TADDR_INST_FETCH = 5, > > > + RISCV_IOMMU_FQ_TTYPE_TADDR_RD = 6, > > > + RISCV_IOMMU_FQ_TTYPE_TADDR_WR = 7, > > > + RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ = 8, > > > + RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9, > > > +}; > > > > RISCV_IOMMU_FW_TTYP_* for all above > > > > I guess RISCV_IOMMU_FQ_TTYP_* to match _FQ_ acronym. Oh yeah. I guess my eyes had glazed over at this point because I didn't notice the 'FW' vs. 'FQ'. So, yeah, we want RISCV_IOMMU_FQ_TTYP_* for all above, including RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ. Thanks, drew