From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 734A118509C for ; Thu, 30 May 2024 23:39:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717112372; cv=none; b=KzmPv2ygQ2r4+NlwbHsCxwNAZchj5QGizkCYS3n2j7EUGK1oRaxQ0xQyNzFZlbTdeYehfI/NSLaLuWxQ/NXaqjHF4Xp62c47hS1oqS5Em+PH0aW1/ONmsCorUomp/IKlk9qGrcnjobvQ+tAeohgNpPxuZB7M7FULkPWBggONNbA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717112372; c=relaxed/simple; bh=T1uKfbYpHJ7+XTHkl/ASSB7eVsQaHdpCr7z9RC1Lp9I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XLW9YFVU4TCpLeuG2VAWjnWZT/mJEOWqNoN75dpGgvnVLk5JnAlw18wR9kil+a0z4yZDiO3MTYpe9Ja5WLK+9VYsgCuoXOPdnJL+HiEnhTXkt5/aYEtD2jQlPXnpW0KsNCv+8dMLluqonSc5UQvvnHMD6m7RfJutH+MP6Kiy7ME= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2D15A1655; Thu, 30 May 2024 16:39:54 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AA74D3F792; Thu, 30 May 2024 16:39:27 -0700 (PDT) From: Andre Przywara To: Joerg Roedel , Will Deacon , Robin Murphy , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Krzysztof Kozlowski , Conor Dooley , Rob Herring Cc: Chris Morgan , Ryan Walklin , iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/5] iommu: sun50i: clear bypass register Date: Fri, 31 May 2024 00:37:56 +0100 Message-Id: <20240530233800.27705-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20240530233800.27705-1-andre.przywara@arm.com> References: <20240530233800.27705-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Jernej Skrabec The Allwinner H6 IOMMU has a bypass register, which allows to circumvent the page tables for each possible master. The reset value for this register is 0, which disables the bypass. The Allwinner H616 IOMMU resets this register to 0x7f, which activates the bypass for all masters, which is not what we want. Always clear this register to 0, to enforce the usage of page tables, and make this driver compatible with the H616 in this respect. Signed-off-by: Jernej Skrabec Signed-off-by: Andre Przywara --- drivers/iommu/sun50i-iommu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index c519b991749d7..dd3f07384624c 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -452,6 +452,7 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu) IOMMU_TLB_PREFETCH_MASTER_ENABLE(3) | IOMMU_TLB_PREFETCH_MASTER_ENABLE(4) | IOMMU_TLB_PREFETCH_MASTER_ENABLE(5)); + iommu_write(iommu, IOMMU_BYPASS_REG, 0); iommu_write(iommu, IOMMU_INT_ENABLE_REG, IOMMU_INT_MASK); iommu_write(iommu, IOMMU_DM_AUT_CTRL_REG(SUN50I_IOMMU_ACI_NONE), IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 0) | -- 2.35.8