[PATCH v4 0/7] PCI: xilinx-nwl: Add phy support

[PATCH v4 0/7] PCI: xilinx-nwl: Add phy support

[Sean Anderson]

Add phy subsystem support for the xilinx-nwl PCIe controller. This
series also includes several small fixes and improvements.

Changes in v4:
- Clarify dt-bindings commit subject/message
- Explain likely effects of the off-by-one error
- Trim down UBSAN backtrace
- Move if to after pci_host_probe
- Remove if in err_phy
- Fix error path in phy_enable skipping the first phy
- Disable phys in reverse order
- Use dev_err instead of WARN for errors

Changes in v3:
- Document phys property
- Expand off-by-one commit message

Changes in v2:
- Remove phy-names
- Add an example
- Get phys by index and not by name

Sean Anderson (7):
  dt-bindings: pci: xilinx-nwl: Add phys property
  PCI: xilinx-nwl: Fix off-by-one in IRQ handler
  PCI: xilinx-nwl: Fix register misspelling
  PCI: xilinx-nwl: Rate-limit misc interrupt messages
  PCI: xilinx-nwl: Clean up clock on probe failure/removal
  PCI: xilinx-nwl: Add phy support
  arm64: zynqmp: Add PCIe phys

 .../bindings/pci/xlnx,nwl-pcie.yaml           |   7 +
 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |   1 +
 drivers/pci/controller/pcie-xilinx-nwl.c      | 139 +++++++++++++++---
 3 files changed, 124 insertions(+), 23 deletions(-)

-- 
2.35.1.1320.gc452695387.dirty

[PATCH v4 1/7] dt-bindings: pci: xilinx-nwl: Add phys property

[Sean Anderson]

Add phys properties so Linux can power-on/configure the GTR
transceivers (xlnx,zynqmp-psgtr-v1.1).

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---

Changes in v4:
- Clarify commit subject/message

Changes in v3:
- Document phys property

Changes in v2:
- Remove phy-names
- Add an example

 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
index 426f90a47f35..cc50795d170b 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
@@ -61,6 +61,11 @@ properties:
   interrupt-map:
     maxItems: 4
 
+  phys:
+    minItems: 1
+    maxItems: 4
+    description: One phy per logical lane, in order
+
   power-domains:
     maxItems: 1
 
@@ -110,6 +115,7 @@ examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/phy/phy.h>
     #include <dt-bindings/power/xlnx-zynqmp-power.h>
     soc {
         #address-cells = <2>;
@@ -138,6 +144,7 @@ examples:
                             <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
                             <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
             msi-parent = <&nwl_pcie>;
+            phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
             power-domains = <&zynqmp_firmware PD_PCIE>;
             iommus = <&smmu 0x4d0>;
             pcie_intc: legacy-interrupt-controller {
-- 
2.35.1.1320.gc452695387.dirty

Re: [PATCH v4 0/7] PCI: xilinx-nwl: Add phy support

[Sean Anderson]

On 5/31/24 12:13, Sean Anderson wrote:
> Add phy subsystem support for the xilinx-nwl PCIe controller. This
> series also includes several small fixes and improvements.
> 
> Changes in v4:
> - Clarify dt-bindings commit subject/message
> - Explain likely effects of the off-by-one error
> - Trim down UBSAN backtrace
> - Move if to after pci_host_probe
> - Remove if in err_phy
> - Fix error path in phy_enable skipping the first phy
> - Disable phys in reverse order
> - Use dev_err instead of WARN for errors
> 
> Changes in v3:
> - Document phys property
> - Expand off-by-one commit message
> 
> Changes in v2:
> - Remove phy-names
> - Add an example
> - Get phys by index and not by name
> 
> Sean Anderson (7):
>   dt-bindings: pci: xilinx-nwl: Add phys property
>   PCI: xilinx-nwl: Fix off-by-one in IRQ handler
>   PCI: xilinx-nwl: Fix register misspelling
>   PCI: xilinx-nwl: Rate-limit misc interrupt messages
>   PCI: xilinx-nwl: Clean up clock on probe failure/removal
>   PCI: xilinx-nwl: Add phy support
>   arm64: zynqmp: Add PCIe phys
> 
>  .../bindings/pci/xlnx,nwl-pcie.yaml           |   7 +
>  .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |   1 +
>  drivers/pci/controller/pcie-xilinx-nwl.c      | 139 +++++++++++++++---
>  3 files changed, 124 insertions(+), 23 deletions(-)
> 

ping.

--Sean

Re: [PATCH v4 0/7] PCI: xilinx-nwl: Add phy support

[Bjorn Helgaas]

On Fri, May 31, 2024 at 12:13:30PM -0400, Sean Anderson wrote:
> Add phy subsystem support for the xilinx-nwl PCIe controller. This
> series also includes several small fixes and improvements.
> 
> Changes in v4:
> - Clarify dt-bindings commit subject/message
> - Explain likely effects of the off-by-one error
> - Trim down UBSAN backtrace
> - Move if to after pci_host_probe
> - Remove if in err_phy
> - Fix error path in phy_enable skipping the first phy
> - Disable phys in reverse order
> - Use dev_err instead of WARN for errors
> 
> Changes in v3:
> - Document phys property
> - Expand off-by-one commit message
> 
> Changes in v2:
> - Remove phy-names
> - Add an example
> - Get phys by index and not by name
> 
> Sean Anderson (7):
>   dt-bindings: pci: xilinx-nwl: Add phys property
>   PCI: xilinx-nwl: Fix off-by-one in IRQ handler
>   PCI: xilinx-nwl: Fix register misspelling
>   PCI: xilinx-nwl: Rate-limit misc interrupt messages
>   PCI: xilinx-nwl: Clean up clock on probe failure/removal
>   PCI: xilinx-nwl: Add phy support

Applied the above to pci/controller/xilinx for v6.12, thanks!

I assume the DTS update below should go via some other tree, but let
me know if I should pick it up.

>   arm64: zynqmp: Add PCIe phys
> 
>  .../bindings/pci/xlnx,nwl-pcie.yaml           |   7 +
>  .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |   1 +
>  drivers/pci/controller/pcie-xilinx-nwl.c      | 139 +++++++++++++++---
>  3 files changed, 124 insertions(+), 23 deletions(-)

Re: [PATCH v4 0/7] PCI: xilinx-nwl: Add phy support

[Michal Simek]

Hi Bjorn,

On 8/9/24 21:54, Bjorn Helgaas wrote:
> On Fri, May 31, 2024 at 12:13:30PM -0400, Sean Anderson wrote:
>> Add phy subsystem support for the xilinx-nwl PCIe controller. This
>> series also includes several small fixes and improvements.
>>
>> Changes in v4:
>> - Clarify dt-bindings commit subject/message
>> - Explain likely effects of the off-by-one error
>> - Trim down UBSAN backtrace
>> - Move if to after pci_host_probe
>> - Remove if in err_phy
>> - Fix error path in phy_enable skipping the first phy
>> - Disable phys in reverse order
>> - Use dev_err instead of WARN for errors
>>
>> Changes in v3:
>> - Document phys property
>> - Expand off-by-one commit message
>>
>> Changes in v2:
>> - Remove phy-names
>> - Add an example
>> - Get phys by index and not by name
>>
>> Sean Anderson (7):
>>    dt-bindings: pci: xilinx-nwl: Add phys property
>>    PCI: xilinx-nwl: Fix off-by-one in IRQ handler
>>    PCI: xilinx-nwl: Fix register misspelling
>>    PCI: xilinx-nwl: Rate-limit misc interrupt messages
>>    PCI: xilinx-nwl: Clean up clock on probe failure/removal
>>    PCI: xilinx-nwl: Add phy support
> 
> Applied the above to pci/controller/xilinx for v6.12, thanks!
> 
> I assume the DTS update below should go via some other tree, but let
> me know if I should pick it up.

Would be good if you can pick it up with the series together.
I have already acked that patch before.

Thanks,
Michal

Re: [PATCH v4 0/7] PCI: xilinx-nwl: Add phy support

[Bjorn Helgaas]

On Fri, Aug 30, 2024 at 04:08:08PM +0200, Michal Simek wrote:
> Hi Bjorn,
> 
> On 8/9/24 21:54, Bjorn Helgaas wrote:
> > On Fri, May 31, 2024 at 12:13:30PM -0400, Sean Anderson wrote:
> > > Add phy subsystem support for the xilinx-nwl PCIe controller. This
> > > series also includes several small fixes and improvements.
> > > 
> > > Changes in v4:
> > > - Clarify dt-bindings commit subject/message
> > > - Explain likely effects of the off-by-one error
> > > - Trim down UBSAN backtrace
> > > - Move if to after pci_host_probe
> > > - Remove if in err_phy
> > > - Fix error path in phy_enable skipping the first phy
> > > - Disable phys in reverse order
> > > - Use dev_err instead of WARN for errors
> > > 
> > > Changes in v3:
> > > - Document phys property
> > > - Expand off-by-one commit message
> > > 
> > > Changes in v2:
> > > - Remove phy-names
> > > - Add an example
> > > - Get phys by index and not by name
> > > 
> > > Sean Anderson (7):
> > >    dt-bindings: pci: xilinx-nwl: Add phys property
> > >    PCI: xilinx-nwl: Fix off-by-one in IRQ handler
> > >    PCI: xilinx-nwl: Fix register misspelling
> > >    PCI: xilinx-nwl: Rate-limit misc interrupt messages
> > >    PCI: xilinx-nwl: Clean up clock on probe failure/removal
> > >    PCI: xilinx-nwl: Add phy support
> > 
> > Applied the above to pci/controller/xilinx for v6.12, thanks!
> > 
> > I assume the DTS update below should go via some other tree, but let
> > me know if I should pick it up.
> 
> Would be good if you can pick it up with the series together.
> I have already acked that patch before.

Thanks, I picked up patch 7/7 "arm64: zynqmp: Add PCIe phys" as well!

Bjorn