From: Andrew Jones <ajones@ventanamicro.com>
To: Tomasz Jeznach <tjeznach@rivosinc.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <apatel@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Nick Kossifidis <mick@ics.forth.gr>,
Sebastien Boeuf <seb@rivosinc.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, iommu@lists.linux.dev,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux@rivosinc.com, Lu Baolu <baolu.lu@linux.intel.com>
Subject: Re: [PATCH v6 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver
Date: Mon, 3 Jun 2024 14:53:09 +0200 [thread overview]
Message-ID: <20240603-c4a8257697f83cd3bace6ce5@orel> (raw)
In-Reply-To: <20240529-08fd52a8e703418142bdfa84@orel>
...
> > +/* 5.19 Performance monitoring counter overflow status (32bits) */
> > +#define RISCV_IOMMU_REG_IOCOUNTOVF 0x0058
> > +#define RISCV_IOMMU_IOCOUNTOVF_CY BIT(0)
> > +#define RISCV_IOMMU_IOCOUNTOVF_HPM GENMASK_ULL(31, 1)
>
> RISCV_IOMMU_REG_IOCNTOVF* for all above. It looks like this
> got renamed and the header of the spec subsection still has
> the old name, but otherwise the new name is referenced.
>
> > +
> > +/* 5.20 Performance monitoring counter inhibits (32bits) */
> > +#define RISCV_IOMMU_REG_IOCOUNTINH 0x005C
> > +#define RISCV_IOMMU_IOCOUNTINH_CY BIT(0)
> > +#define RISCV_IOMMU_IOCOUNTINH_HPM GENMASK(31, 1)
>
> RISCV_IOMMU_IOCNTINH* for all above. Same header with old
> name spec issue.
>
Scratch these suggestions. Based on IOMMU spec PR#243 ("Clarification
updates to IOMMU v1.0.0") it looks like the iocnt* names are getting
fixed up to be iocount* names.
Thanks,
drew
next prev parent reply other threads:[~2024-06-03 12:53 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-24 19:34 [PATCH v6 0/7] Linux RISC-V IOMMU Support Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver Tomasz Jeznach
2024-05-29 15:15 ` Andrew Jones
2024-05-29 17:59 ` Tomasz Jeznach
2024-05-30 8:20 ` Andrew Jones
2024-06-03 12:53 ` Andrew Jones [this message]
2024-06-05 18:58 ` Tomasz Jeznach
2024-06-06 6:54 ` Andrew Jones
2024-06-03 12:59 ` Andrew Jones
2024-06-05 19:41 ` Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 3/7] iommu/riscv: Add RISC-V IOMMU PCIe " Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 4/7] iommu/riscv: Enable IOMMU registration and device probe Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 5/7] iommu/riscv: Device directory management Tomasz Jeznach
2024-05-31 6:25 ` Zong Li
2024-06-10 17:49 ` Jason Gunthorpe
2024-06-10 18:48 ` Tomasz Jeznach
2024-06-10 22:20 ` Jason Gunthorpe
2024-06-11 2:00 ` Tomasz Jeznach
2024-06-11 12:12 ` Jason Gunthorpe
2024-05-24 19:34 ` [PATCH v6 6/7] iommu/riscv: Command and fault queue support Tomasz Jeznach
2024-05-24 19:34 ` [PATCH v6 7/7] iommu/riscv: Paging domain support Tomasz Jeznach
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