From: kernel test robot <lkp@intel.com>
To: Sibi Sankar <quic_sibis@quicinc.com>,
sudeep.holla@arm.com, cristian.marussi@arm.com,
andersson@kernel.org, konrad.dybcio@linaro.org,
jassisinghbrar@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, dmitry.baryshkov@linaro.org
Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, quic_rgottimu@quicinc.com,
quic_kshivnan@quicinc.com, quic_sibis@quicinc.com,
conor+dt@kernel.org, quic_nkela@quicinc.com,
quic_psodagud@quicinc.com, abel.vesa@linaro.org
Subject: Re: [PATCH V5 2/5] mailbox: Add support for QTI CPUCP mailbox controller
Date: Tue, 4 Jun 2024 16:16:06 +0800 [thread overview]
Message-ID: <202406041546.kXkVH9Ww-lkp@intel.com> (raw)
In-Reply-To: <20240603205859.2212225-3-quic_sibis@quicinc.com>
Hi Sibi,
kernel test robot noticed the following build errors:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.10-rc2 next-20240604]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sibi-Sankar/dt-bindings-mailbox-qcom-Add-CPUCP-mailbox-controller-bindings/20240604-050256
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20240603205859.2212225-3-quic_sibis%40quicinc.com
patch subject: [PATCH V5 2/5] mailbox: Add support for QTI CPUCP mailbox controller
config: hexagon-allyesconfig (https://download.01.org/0day-ci/archive/20240604/202406041546.kXkVH9Ww-lkp@intel.com/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project d7d2d4f53fc79b4b58e8d8d08151b577c3699d4a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240604/202406041546.kXkVH9Ww-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406041546.kXkVH9Ww-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/mailbox/qcom-cpucp-mbox.c:7:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:11:
In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:548:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
548 | val = __raw_readb(PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:561:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
561 | val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
| ~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
37 | #define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
| ^
In file included from drivers/mailbox/qcom-cpucp-mbox.c:7:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:11:
In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:574:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
574 | val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
| ~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
35 | #define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
| ^
In file included from drivers/mailbox/qcom-cpucp-mbox.c:7:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:11:
In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:585:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
585 | __raw_writeb(value, PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:595:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
595 | __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:605:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
605 | __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
>> drivers/mailbox/qcom-cpucp-mbox.c:54:11: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
54 | status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
| ^
>> drivers/mailbox/qcom-cpucp-mbox.c:65:3: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
65 | writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
| ^
drivers/mailbox/qcom-cpucp-mbox.c:78:8: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
78 | val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
| ^
drivers/mailbox/qcom-cpucp-mbox.c:80:2: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
80 | writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
| ^
drivers/mailbox/qcom-cpucp-mbox.c:91:8: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
91 | val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
| ^
drivers/mailbox/qcom-cpucp-mbox.c:93:2: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
93 | writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
| ^
drivers/mailbox/qcom-cpucp-mbox.c:132:2: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
132 | writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
| ^
6 warnings and 7 errors generated.
vim +/readq +54 drivers/mailbox/qcom-cpucp-mbox.c
47
48 static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data)
49 {
50 struct qcom_cpucp_mbox *cpucp = data;
51 u64 status;
52 int i;
53
> 54 status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
55
56 for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORTED) {
57 u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF);
58 struct mbox_chan *chan = &cpucp->chans[i];
59 unsigned long flags;
60
61 /* Provide mutual exclusion with changes to chan->cl */
62 spin_lock_irqsave(&chan->lock, flags);
63 if (chan->cl)
64 mbox_chan_received_data(chan, &val);
> 65 writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
66 spin_unlock_irqrestore(&chan->lock, flags);
67 }
68
69 return IRQ_HANDLED;
70 }
71
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2024-06-04 8:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-03 20:58 [PATCH V5 0/5] qcom: x1e80100: Enable CPUFreq Sibi Sankar
2024-06-03 20:58 ` [PATCH V5 1/5] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings Sibi Sankar
2024-06-03 20:58 ` [PATCH V5 2/5] mailbox: Add support for QTI CPUCP mailbox controller Sibi Sankar
2024-06-04 8:16 ` kernel test robot [this message]
2024-06-04 9:10 ` kernel test robot
2024-06-03 20:58 ` [PATCH V5 3/5] arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region Sibi Sankar
2024-06-07 9:24 ` Konrad Dybcio
2024-06-03 20:58 ` [PATCH V5 4/5] arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes Sibi Sankar
2024-06-03 20:58 ` [PATCH V5 5/5] arm64: dts: qcom: x1e80100: Enable cpufreq Sibi Sankar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=202406041546.kXkVH9Ww-lkp@intel.com \
--to=lkp@intel.com \
--cc=abel.vesa@linaro.org \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=cristian.marussi@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=jassisinghbrar@gmail.com \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=llvm@lists.linux.dev \
--cc=oe-kbuild-all@lists.linux.dev \
--cc=quic_kshivnan@quicinc.com \
--cc=quic_nkela@quicinc.com \
--cc=quic_psodagud@quicinc.com \
--cc=quic_rgottimu@quicinc.com \
--cc=quic_sibis@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=sudeep.holla@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).