From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com,
greentime.hu@sifive.com, vincent.chen@sifive.com,
Yong-Xuan Wang <yongxuan.wang@sifive.com>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
devicetree@vger.kernel.org
Subject: [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
Date: Wed, 5 Jun 2024 20:15:08 +0800 [thread overview]
Message-ID: <20240605121512.32083-3-yongxuan.wang@sifive.com> (raw)
In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com>
Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
property.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 468c646247aa..1e30988826b9 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -153,6 +153,36 @@ properties:
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
+ - const: svade
+ description: |
+ The standard Svade supervisor-level extension for raising page-fault
+ exceptions when PTE A/D bits need be set as ratified in the 20240213
+ version of the privileged ISA specification.
+
+ Both Svade and Svadu extensions control the hardware behavior when
+ the PTE A/D bits need to be set. The default behavior for the four
+ possible combinations of these extensions in the device tree are:
+ 1. Neither svade nor svadu in DT: default to svade.
+ 2. Only svade in DT: use svade.
+ 3. Only svadu in DT: use svadu.
+ 4. Both svade and svadu in DT: default to svade (Linux can switch to
+ svadu once the SBI FWFT extension is available).
+
+ - const: svadu
+ description: |
+ The standard Svadu supervisor-level extension for hardware updating
+ of PTE A/D bits as ratified at commit c1abccf ("Merge pull request
+ #25 from ved-rivos/ratified") of riscv-svadu.
+
+ Both Svade and Svadu extensions control the hardware behavior when
+ the PTE A/D bits need to be set. The default behavior for the four
+ possible combinations of these extensions in the device tree are:
+ 1. Neither svade nor svadu in DT: default to svade.
+ 2. Only svade in DT: use svade.
+ 3. Only svadu in DT: use svadu.
+ 4. Both svade and svadu in DT: default to svade (Linux can switch to
+ svadu once the SBI FWFT extension is available).
+
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
--
2.17.1
next parent reply other threads:[~2024-06-05 12:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240605121512.32083-1-yongxuan.wang@sifive.com>
2024-06-05 12:15 ` Yong-Xuan Wang [this message]
2024-06-05 16:54 ` [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Conor Dooley
2024-06-18 10:38 ` Yong-Xuan Wang
2024-06-19 18:11 ` Conor Dooley
2024-06-20 6:25 ` Anup Patel
2024-06-21 8:33 ` Andrew Jones
2024-06-21 10:11 ` Conor Dooley
2024-06-25 10:15 ` Yong-Xuan Wang
2024-06-21 8:37 ` Alexandre Ghiti
2024-06-21 10:17 ` Conor Dooley
2024-06-21 12:42 ` Alexandre Ghiti
2024-06-21 13:15 ` Andrew Jones
2024-06-21 14:04 ` Conor Dooley
2024-06-21 14:52 ` Andrew Jones
2024-06-21 14:58 ` Conor Dooley
2024-06-21 15:08 ` Andrew Jones
2024-06-22 12:01 ` Conor Dooley
2024-06-25 10:17 ` Yong-Xuan Wang
2024-06-25 10:19 ` Andrew Jones
2024-06-21 7:56 ` Alexandre Ghiti
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