* [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-11 10:05 ` Alexander Stein
2024-06-10 20:46 ` [PATCH v2 2/9] arm64: dts: imx8qm: add lvds subsystem Frank Li
` (8 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi | 63 +++++++++++++
arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++++++++
2 files changed, 177 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
new file mode 100644
index 0000000000000..55fd60446ad21
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+lvds0_subsys: bus@56240000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56240000 0x0 0x56240000 0x10000>;
+
+ qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243000 0x4>;
+ #clock-cells = <1>;
+ clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clock-output-names = "mipi1_pwm_lpcg_clk",
+ "mipi1_pwm_lpcg_ipg_clk",
+ "mipi1_pwm_lpcg_32k_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ };
+
+ qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243010 0x4>;
+ #clock-cells = <1>;
+ clock-output-names = "mipi1_i2c0_lpcg_clk",
+ "mipi1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56244000 0x1000>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ status = "disabled";
+ };
+
+ qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56246000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
new file mode 100644
index 0000000000000..12ae4f48e1e1c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+lvds1_subsys: bus@57240000 {
+ compatible = "simple-bus";
+ interrupt-parent = <&irqsteer_lvds1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57240000 0x0 0x57240000 0x10000>;
+
+ irqsteer_lvds1: interrupt-controller@57240000 {
+ compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x57240000 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ lvds1_lis_lpcg: clock-controller@57243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ };
+
+ lvds1_pwm_lpcg: clock-controller@5724300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5724300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_pwm_lpcg_clk",
+ "lvds1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ };
+
+ lvds1_i2c0_lpcg: clock-controller@57243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_i2c0_lpcg_clk",
+ "lvds1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ };
+
+ lvds1_i2c1_lpcg: clock-controller@57243014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_i2c1_lpcg_clk",
+ "lvds1_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ };
+
+ pwm_lvds1: pwm@57244000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x57244000 0x1000>;
+ clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_lvds1: i2c@57246000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57246000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
+ <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c1_lvds1: i2c@57247000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57247000 0x1000>;
+ interrupts = <9>;
+ clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
+ <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ status = "disabled";
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem
2024-06-10 20:46 ` [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem Frank Li
@ 2024-06-11 10:05 ` Alexander Stein
2024-06-12 15:13 ` Frank Li
0 siblings, 1 reply; 15+ messages in thread
From: Alexander Stein @ 2024-06-11 10:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng, linux-arm-kernel
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Frank Li
Hi Frank,
Am Montag, 10. Juni 2024, 22:46:18 CEST schrieb Frank Li:
> Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi | 63 +++++++++++++
> arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++++++++
> 2 files changed, 177 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> new file mode 100644
> index 0000000000000..55fd60446ad21
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +lvds0_subsys: bus@56240000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x56240000 0x0 0x56240000 0x10000>;
> +
> + qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56243000 0x4>;
> + #clock-cells = <1>;
> + clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1>;
> + };
> +
> + qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5624300c 0x4>;
> + #clock-cells = <1>;
> + clock-output-names = "mipi1_pwm_lpcg_clk",
> + "mipi1_pwm_lpcg_ipg_clk",
> + "mipi1_pwm_lpcg_32k_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + };
> +
> + qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56243010 0x4>;
> + #clock-cells = <1>;
> + clock-output-names = "mipi1_i2c0_lpcg_clk",
> + "mipi1_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x56244000 0x1000>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
Is IMX_SC_R_MIPI_1_I2C_0 actually correct? I would have assumed
it's IMX_SC_R_MIPI_1_PWM_0.
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + status = "disabled";
> + };
> +
> + qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
> + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x56246000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <8>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + status = "disabled";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
> new file mode 100644
> index 0000000000000..12ae4f48e1e1c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
This is only for imx8qm, no?
It maybe makes sense to rename this file to imx8qm-ss-lvds1.dtsi
Best regards,
Alexander
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +lvds1_subsys: bus@57240000 {
> + compatible = "simple-bus";
> + interrupt-parent = <&irqsteer_lvds1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x57240000 0x0 0x57240000 0x10000>;
> +
> + irqsteer_lvds1: interrupt-controller@57240000 {
> + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> + reg = <0x57240000 0x1000>;
> + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <1>;
> + clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_LVDS_1>;
> + fsl,channel = <0>;
> + fsl,num-irqs = <32>;
> + };
> +
> + lvds1_lis_lpcg: clock-controller@57243000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57243000 0x4>;
> + #clock-cells = <1>;
> + clocks = <&lvds_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_4>;
> + clock-output-names = "lvds1_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_LVDS_1>;
> + };
> +
> + lvds1_pwm_lpcg: clock-controller@5724300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5724300c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
> + <&lvds_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "lvds1_pwm_lpcg_clk",
> + "lvds1_pwm_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> + };
> +
> + lvds1_i2c0_lpcg: clock-controller@57243010 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57243010 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> + <&lvds_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "lvds1_i2c0_lpcg_clk",
> + "lvds1_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> + };
> +
> + lvds1_i2c1_lpcg: clock-controller@57243014 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57243014 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> + <&lvds_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "lvds1_i2c1_lpcg_clk",
> + "lvds1_i2c1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> + };
> +
> + pwm_lvds1: pwm@57244000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x57244000 0x1000>;
> + clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
> + <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> + status = "disabled";
> + };
> +
> + i2c0_lvds1: i2c@57246000 {
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x57246000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <8>;
> + clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
> + <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> + status = "disabled";
> + };
> +
> + i2c1_lvds1: i2c@57247000 {
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x57247000 0x1000>;
> + interrupts = <9>;
> + clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
> + <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> + status = "disabled";
> + };
> +};
>
>
--
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Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem
2024-06-11 10:05 ` Alexander Stein
@ 2024-06-12 15:13 ` Frank Li
0 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-12 15:13 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng, linux-arm-kernel, devicetree, imx, linux-kernel
On Tue, Jun 11, 2024 at 12:05:35PM +0200, Alexander Stein wrote:
> Hi Frank,
>
> Am Montag, 10. Juni 2024, 22:46:18 CEST schrieb Frank Li:
> > Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi | 63 +++++++++++++
> > arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++++++++
> > 2 files changed, 177 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> > new file mode 100644
> > index 0000000000000..55fd60446ad21
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> > @@ -0,0 +1,63 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +lvds0_subsys: bus@56240000 {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x56240000 0x0 0x56240000 0x10000>;
> > +
> > + qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x56243000 0x4>;
> > + #clock-cells = <1>;
> > + clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1>;
> > + };
> > +
> > + qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5624300c 0x4>;
> > + #clock-cells = <1>;
> > + clock-output-names = "mipi1_pwm_lpcg_clk",
> > + "mipi1_pwm_lpcg_ipg_clk",
> > + "mipi1_pwm_lpcg_32k_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > + };
> > +
> > + qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x56243010 0x4>;
> > + #clock-cells = <1>;
> > + clock-output-names = "mipi1_i2c0_lpcg_clk",
> > + "mipi1_i2c0_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > + };
> > +
> > + qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
> > + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > + reg = <0x56244000 0x1000>;
> > + clock-names = "ipg", "per";
> > + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
>
> Is IMX_SC_R_MIPI_1_I2C_0 actually correct? I would have assumed
> it's IMX_SC_R_MIPI_1_PWM_0.
>
> > + assigned-clock-rates = <24000000>;
> > + #pwm-cells = <3>;
> > + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > + status = "disabled";
> > + };
> > +
> > + qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
> > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > + reg = <0x56246000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <8>;
> > + clock-names = "per", "ipg";
> > + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
> > + assigned-clock-rates = <24000000>;
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > + status = "disabled";
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
> > new file mode 100644
> > index 0000000000000..12ae4f48e1e1c
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
>
> This is only for imx8qm, no?
>
> It maybe makes sense to rename this file to imx8qm-ss-lvds1.dtsi
It plan include in root node, it'd better keep consistency with other
file names.
/* sorted in register address */
#include "imx8-ss-audio.dtsi"
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-security.dtsi"
#include "imx8-ss-cm41.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
#include "imx8-ss-lsio.dtsi"
#include "imx8-ss-hsio.dtsi"
#include "imx8-ss-dc0.dtsi"
#include "imx8-ss-dc1.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-gpu1.dtsi"
#include "imx8-ss-vpu.dtsi"
}
imx8qm-ss-xxx should overwrite common ss part.
Frank
>
> Best regards,
> Alexander
>
> > @@ -0,0 +1,114 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +lvds1_subsys: bus@57240000 {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&irqsteer_lvds1>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x57240000 0x0 0x57240000 0x10000>;
> > +
> > + irqsteer_lvds1: interrupt-controller@57240000 {
> > + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> > + reg = <0x57240000 0x1000>;
> > + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + interrupt-parent = <&gic>;
> > + #interrupt-cells = <1>;
> > + clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
> > + clock-names = "ipg";
> > + power-domains = <&pd IMX_SC_R_LVDS_1>;
> > + fsl,channel = <0>;
> > + fsl,num-irqs = <32>;
> > + };
> > +
> > + lvds1_lis_lpcg: clock-controller@57243000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57243000 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&lvds_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_4>;
> > + clock-output-names = "lvds1_lis_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_LVDS_1>;
> > + };
> > +
> > + lvds1_pwm_lpcg: clock-controller@5724300c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5724300c 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
> > + <&lvds_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "lvds1_pwm_lpcg_clk",
> > + "lvds1_pwm_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> > + };
> > +
> > + lvds1_i2c0_lpcg: clock-controller@57243010 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57243010 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> > + <&lvds_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "lvds1_i2c0_lpcg_clk",
> > + "lvds1_i2c0_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > + };
> > +
> > + lvds1_i2c1_lpcg: clock-controller@57243014 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57243014 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> > + <&lvds_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "lvds1_i2c1_lpcg_clk",
> > + "lvds1_i2c1_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > + };
> > +
> > + pwm_lvds1: pwm@57244000 {
> > + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > + reg = <0x57244000 0x1000>;
> > + clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
> > + <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
> > + clock-names = "ipg", "per";
> > + assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
> > + assigned-clock-rates = <24000000>;
> > + #pwm-cells = <3>;
> > + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c0_lvds1: i2c@57246000 {
> > + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > + reg = <0x57246000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <8>;
> > + clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
> > + <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
> > + clock-names = "per", "ipg";
> > + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> > + assigned-clock-rates = <24000000>;
> > + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c1_lvds1: i2c@57247000 {
> > + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > + reg = <0x57247000 0x1000>;
> > + interrupts = <9>;
> > + clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
> > + <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
> > + clock-names = "per", "ipg";
> > + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> > + assigned-clock-rates = <24000000>;
> > + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > + status = "disabled";
> > + };
> > +};
> >
> >
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/9] arm64: dts: imx8qm: add lvds subsystem
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
2024-06-10 20:46 ` [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-10 20:46 ` [PATCH v2 3/9] arm64: dts: imx8: add basic mipi subsystem Frank Li
` (7 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
Add irqsteer, pwm and i2c in lvds subsystem.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 77 +++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 10 +++
2 files changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
new file mode 100644
index 0000000000000..1da3934847057
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2024 NXP
+ */
+
+&qm_lvds0_lis_lpcg {
+ clocks = <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+};
+
+&qm_lvds0_pwm_lpcg {
+ clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+};
+
+&qm_lvds0_i2c0_lpcg {
+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+};
+
+&qm_pwm_lvds0 {
+ clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>;
+};
+
+&qm_i2c0_lvds0 {
+ clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>,
+ <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>;
+};
+
+&lvds0_subsys {
+ interrupt-parent = <&irqsteer_lvds0>;
+
+ irqsteer_lvds0: interrupt-controller@56240000 {
+ compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x56240000 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&qm_lvds0_lis_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ lvds0_i2c1_lpcg: clock-controller@56243014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds0_i2c1_lpcg_clk",
+ "lvds0_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ };
+
+ i2c1_lvds0: i2c@56247000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56247000 0x1000>;
+ interrupts = <9>;
+ clocks = <&lvds0_i2c1_lpcg IMX_LPCG_CLK_0>,
+ <&lvds0_i2c1_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ status = "disabled";
+ };
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 61986e0639e53..1e8511e8d8577 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -560,11 +560,20 @@ clk_spdif1_rx: clock-spdif1-rx {
clock-output-names = "spdif1_rx";
};
+ lvds_ipg_clk: clock-controller-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "lvds0_ipg_clk";
+ };
+
/* sorted in register address */
#include "imx8-ss-cm41.dtsi"
#include "imx8-ss-audio.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-gpu0.dtsi"
+ #include "imx8-ss-lvds0.dtsi"
+ #include "imx8-ss-lvds1.dtsi"
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"
@@ -576,3 +585,4 @@ clk_spdif1_rx: clock-spdif1-rx {
#include "imx8qm-ss-conn.dtsi"
#include "imx8qm-ss-lsio.dtsi"
#include "imx8qm-ss-audio.dtsi"
+#include "imx8qm-ss-lvds.dtsi"
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 3/9] arm64: dts: imx8: add basic mipi subsystem
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
2024-06-10 20:46 ` [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem Frank Li
2024-06-10 20:46 ` [PATCH v2 2/9] arm64: dts: imx8qm: add lvds subsystem Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-11 11:14 ` Alexander Stein
2024-06-10 20:46 ` [PATCH v2 4/9] arm64: dts: imx8qm: add " Frank Li
` (6 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
Add basic mipi subsystem for imx8qm and imx8qxp.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++++++++++++++
2 files changed, 276 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
new file mode 100644
index 0000000000000..6b56315e8c434
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+mipi0_subsys: bus@56220000 {
+ compatible = "simple-bus";
+ interrupt-parent = <&irqsteer_mipi0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56220000 0x0 0x56220000 0x10000>;
+
+ irqsteer_mipi0: interrupt-controller@56220000 {
+ compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x56220000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ mipi0_lis_lpcg: clock-controller@56223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ mipi0_pwm_lpcg: clock-controller@5622300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi0_pwm_lpcg_clk",
+ "mipi0_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ };
+
+ mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622302c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ pwm_mipi0: pwm@56224000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56224000 0x1000>;
+ clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi0: i2c@56226000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56226000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
+ <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ status = "disabled";
+ };
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
new file mode 100644
index 0000000000000..5b1f08e412b24
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+mipi1_subsys: bus@57220000 {
+ compatible = "simple-bus";
+ interrupt-parent = <&irqsteer_mipi1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57220000 0x0 0x57220000 0x10000>;
+
+ irqsteer_mipi1: interrupt-controller@57220000 {
+ compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x57220000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ mipi1_lis_lpcg: clock-controller@57223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ mipi1_pwm_lpcg: clock-controller@5722300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi1_pwm_lpcg_clk",
+ "mipi1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ };
+
+ mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722302c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ pwm_mipi1: pwm@57224000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x57224000 0x1000>;
+ clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi1: i2c@57226000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57226000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_mipi1>;
+ clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
+ <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ status = "disabled";
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 3/9] arm64: dts: imx8: add basic mipi subsystem
2024-06-10 20:46 ` [PATCH v2 3/9] arm64: dts: imx8: add basic mipi subsystem Frank Li
@ 2024-06-11 11:14 ` Alexander Stein
2024-06-11 15:03 ` Frank Li
0 siblings, 1 reply; 15+ messages in thread
From: Alexander Stein @ 2024-06-11 11:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng, linux-arm-kernel
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Frank Li
Am Montag, 10. Juni 2024, 22:46:20 CEST schrieb Frank Li:
> ********************
> Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter.
> Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it.
> ********************
>
> Add basic mipi subsystem for imx8qm and imx8qxp.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++++++++++++++
> 2 files changed, 276 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> new file mode 100644
> index 0000000000000..6b56315e8c434
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +mipi0_subsys: bus@56220000 {
> + compatible = "simple-bus";
> + interrupt-parent = <&irqsteer_mipi0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x56220000 0x0 0x56220000 0x10000>;
> +
> + irqsteer_mipi0: interrupt-controller@56220000 {
> + compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
> + reg = <0x56220000 0x1000>;
> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <1>;
> + clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> + fsl,channel = <0>;
> + fsl,num-irqs = <32>;
> + };
> +
> + mipi0_lis_lpcg: clock-controller@56223000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223000 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
That's LPCG_DI_LVDS_LPCG_0 for imx8qxp, no? So clock-indices and
clock-output-names should be split similar to patch.
> + clock-output-names = "mipi0_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> + };
> +
> + mipi0_pwm_lpcg: clock-controller@5622300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622300c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
> + <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "mipi0_pwm_lpcg_clk",
> + "mipi0_pwm_lpcg_ipg_clk";
That's LPCG_DI_MIPI_LPCG_12, no? imx8qm RM Rev 0 just lists one clock.
Also it's different on imx8qxp.
> + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> + };
> +
> + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223014 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
Just 0 instead of IMX_LPCG_CLK_0.
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223018 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622301c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223024 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622302c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223028 0x4>;
Order nodes by base address please.
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + pwm_mipi0: pwm@56224000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x56224000 0x1000>;
> + clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
> + <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
I don't think that's correct. IMX_LPCG_CLK_4 evaluates to 16.
'mipi0_pwm_lpcg' only has 2 clocks, so you should use just '1' and '0'.
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> + status = "disabled";
> + };
> +
> + i2c0_mipi0: i2c@56226000 {
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x56226000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <8>;
> + clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> + <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
Just use 0 instead of IMX_LPCG_CLK_0.
> + clock-names = "per", "ipg";
> + assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + status = "disabled";
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
> new file mode 100644
> index 0000000000000..5b1f08e412b24
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
This is only for imx8qm, no?
It maybe makes sense to rename this file to imx8qm-ss-mipi1.dtsi
Best regards,
Alexander
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +mipi1_subsys: bus@57220000 {
> + compatible = "simple-bus";
> + interrupt-parent = <&irqsteer_mipi1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x57220000 0x0 0x57220000 0x10000>;
> +
> + irqsteer_mipi1: interrupt-controller@57220000 {
> + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> + reg = <0x57220000 0x1000>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <1>;
> + clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_MIPI_1>;
> + fsl,channel = <0>;
> + fsl,num-irqs = <32>;
> + };
> +
> + mipi1_lis_lpcg: clock-controller@57223000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223000 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1>;
> + };
> +
> + mipi1_pwm_lpcg: clock-controller@5722300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722300c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
> + <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "mipi1_pwm_lpcg_clk",
> + "mipi1_pwm_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + };
> +
> + mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722301c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223014 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223018 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223024 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223028 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722302c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + pwm_mipi1: pwm@57224000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x57224000 0x1000>;
> + clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
> + <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + status = "disabled";
> + };
> +
> + i2c0_mipi1: i2c@57226000 {
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x57226000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <8>;
> + interrupt-parent = <&irqsteer_mipi1>;
> + clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> + <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + status = "disabled";
> + };
> +};
>
>
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 3/9] arm64: dts: imx8: add basic mipi subsystem
2024-06-11 11:14 ` Alexander Stein
@ 2024-06-11 15:03 ` Frank Li
0 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-11 15:03 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng, linux-arm-kernel, devicetree, imx, linux-kernel
On Tue, Jun 11, 2024 at 01:14:20PM +0200, Alexander Stein wrote:
> Am Montag, 10. Juni 2024, 22:46:20 CEST schrieb Frank Li:
> > ********************
> > Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter.
> > Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it.
> > ********************
> >
> > Add basic mipi subsystem for imx8qm and imx8qxp.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++++++++++++++
> > arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++++++++++++++
> > 2 files changed, 276 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> > new file mode 100644
> > index 0000000000000..6b56315e8c434
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> > @@ -0,0 +1,138 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +mipi0_subsys: bus@56220000 {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&irqsteer_mipi0>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x56220000 0x0 0x56220000 0x10000>;
> > +
> > + irqsteer_mipi0: interrupt-controller@56220000 {
> > + compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
> > + reg = <0x56220000 0x1000>;
> > + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + interrupt-parent = <&gic>;
> > + #interrupt-cells = <1>;
> > + clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
> > + clock-names = "ipg";
> > + power-domains = <&pd IMX_SC_R_MIPI_0>;
> > + fsl,channel = <0>;
> > + fsl,num-irqs = <32>;
> > + };
> > +
> > + mipi0_lis_lpcg: clock-controller@56223000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x56223000 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
>
> That's LPCG_DI_LVDS_LPCG_0 for imx8qxp, no? So clock-indices and
> clock-output-names should be split similar to patch.
I am focus qm firstly. I can remove it.
>
> > + clock-output-names = "mipi0_lis_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_0>;
> > + };
> > +
> > + mipi0_pwm_lpcg: clock-controller@5622300c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5622300c 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
> > + <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "mipi0_pwm_lpcg_clk",
> > + "mipi0_pwm_lpcg_ipg_clk";
>
> That's LPCG_DI_MIPI_LPCG_12, no? imx8qm RM Rev 0 just lists one clock.
> Also it's different on imx8qxp.
>
> > + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> > + };
> > +
> > + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x56223014 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
>
> Just 0 instead of IMX_LPCG_CLK_0.
all lpcg have to use IMX_LPCG_CLK_n, down stream clk driver is difference
with upstream one.
>
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > + };
> > +
> > + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x56223018 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > + };
> > +
> > + mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5622301c 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi0_i2c0_lpcg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > + };
> > +
> > + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x56223024 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> > + };
> > +
> > + mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5622302c 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi0_i2c1_lpcg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> > + };
> > +
> > + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x56223028 0x4>;
>
> Order nodes by base address please.
>
> > + #clock-cells = <1>;
> > + clocks = <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> > + };
> > +
> > + pwm_mipi0: pwm@56224000 {
> > + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > + reg = <0x56224000 0x1000>;
> > + clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
> > + <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
>
> I don't think that's correct. IMX_LPCG_CLK_4 evaluates to 16.
> 'mipi0_pwm_lpcg' only has 2 clocks, so you should use just '1' and '0'.
all lpcg have to use indices, instead of index. Upstream clk driver use
arg0 as clock indices, which is difference downstream version.
>
> > + clock-names = "ipg", "per";
> > + assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
> > + assigned-clock-rates = <24000000>;
> > + #pwm-cells = <3>;
> > + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c0_mipi0: i2c@56226000 {
> > + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > + reg = <0x56226000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <8>;
> > + clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> > + <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
>
> Just use 0 instead of IMX_LPCG_CLK_0.
>
> > + clock-names = "per", "ipg";
> > + assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> > + assigned-clock-rates = <24000000>;
> > + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > + status = "disabled";
> > + };
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
> > new file mode 100644
> > index 0000000000000..5b1f08e412b24
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
>
> This is only for imx8qm, no?
>
> It maybe makes sense to rename this file to imx8qm-ss-mipi1.dtsi
>
> Best regards,
> Alexander
>
> > @@ -0,0 +1,138 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +mipi1_subsys: bus@57220000 {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&irqsteer_mipi1>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x57220000 0x0 0x57220000 0x10000>;
> > +
> > + irqsteer_mipi1: interrupt-controller@57220000 {
> > + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> > + reg = <0x57220000 0x1000>;
> > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + interrupt-parent = <&gic>;
> > + #interrupt-cells = <1>;
> > + clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
> > + clock-names = "ipg";
> > + power-domains = <&pd IMX_SC_R_MIPI_1>;
> > + fsl,channel = <0>;
> > + fsl,num-irqs = <32>;
> > + };
> > +
> > + mipi1_lis_lpcg: clock-controller@57223000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57223000 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1>;
> > + };
> > +
> > + mipi1_pwm_lpcg: clock-controller@5722300c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5722300c 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
> > + <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "mipi1_pwm_lpcg_clk",
> > + "mipi1_pwm_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > + };
> > +
> > + mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5722301c 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi1_i2c0_lpcg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > + };
> > +
> > + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57223014 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > + };
> > +
> > + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57223018 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > + };
> > +
> > + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57223024 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> > + };
> > +
> > + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x57223028 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&dsi_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> > + };
> > +
> > + mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x5722302c 0x4>;
> > + #clock-cells = <1>;
> > + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "mipi1_i2c1_lpcg_clk";
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> > + };
> > +
> > + pwm_mipi1: pwm@57224000 {
> > + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > + reg = <0x57224000 0x1000>;
> > + clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
> > + <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
> > + clock-names = "ipg", "per";
> > + assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
> > + assigned-clock-rates = <24000000>;
> > + #pwm-cells = <3>;
> > + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c0_mipi1: i2c@57226000 {
> > + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > + reg = <0x57226000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <8>;
> > + interrupt-parent = <&irqsteer_mipi1>;
> > + clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> > + <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> > + clock-names = "per", "ipg";
> > + assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> > + assigned-clock-rates = <24000000>;
> > + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > + status = "disabled";
> > + };
> > +};
> >
> >
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 4/9] arm64: dts: imx8qm: add mipi subsystem
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
` (2 preceding siblings ...)
2024-06-10 20:46 ` [PATCH v2 3/9] arm64: dts: imx8: add basic mipi subsystem Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-10 20:46 ` [PATCH v2 5/9] arm64: dts: imx8qm-mek: add cm4 remote-proc and related memory region Frank Li
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
Include common imx8-ss-mipi.dtsi and imx8-ss-mipi2.dtsi.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 1e8511e8d8577..9554e60228dab 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -567,6 +567,20 @@ lvds_ipg_clk: clock-controller-lvds-ipg {
clock-output-names = "lvds0_ipg_clk";
};
+ dsi_ipg_clk: clock-controller-dsi-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dsi_ipg_clk";
+ };
+
+ mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <432000000>;
+ clock-output-names = "mipi_pll_div2_clk";
+ };
+
/* sorted in register address */
#include "imx8-ss-cm41.dtsi"
#include "imx8-ss-audio.dtsi"
@@ -574,6 +588,8 @@ lvds_ipg_clk: clock-controller-lvds-ipg {
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-lvds0.dtsi"
#include "imx8-ss-lvds1.dtsi"
+ #include "imx8-ss-mipi0.dtsi"
+ #include "imx8-ss-mipi1.dtsi"
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"
@@ -586,3 +602,4 @@ lvds_ipg_clk: clock-controller-lvds-ipg {
#include "imx8qm-ss-lsio.dtsi"
#include "imx8qm-ss-audio.dtsi"
#include "imx8qm-ss-lvds.dtsi"
+#include "imx8qm-ss-mipi.dtsi"
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 5/9] arm64: dts: imx8qm-mek: add cm4 remote-proc and related memory region
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
` (3 preceding siblings ...)
2024-06-10 20:46 ` [PATCH v2 4/9] arm64: dts: imx8qm: add " Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-10 20:46 ` [PATCH v2 6/9] arm64: dts: imx8qm-mek: add pwm and i2c in lvds subsystem Frank Li
` (4 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Peng Fan
Add two cm4 remote-proc and related memory regions.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 93 ++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index c024be33fbcce..dbd478af2e474 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -31,6 +31,68 @@ memory@80000000 {
reg = <0x00000000 0x80000000 0 0x40000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ vdev0vring0: memory@90000000 {
+ reg = <0 0x90000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@90008000 {
+ reg = <0 0x90008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@90010000 {
+ reg = <0 0x90010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@90018000 {
+ reg = <0 0x90018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table0: memory@900ff000 {
+ reg = <0 0x900ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: memory {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90400000 0 0x100000>;
+ no-map;
+ };
+
+ vdev2vring0: memory@90100000 {
+ reg = <0 0x90100000 0 0x8000>;
+ no-map;
+ };
+
+ vdev2vring1: memory@90108000 {
+ reg = <0 0x90108000 0 0x8000>;
+ no-map;
+ };
+
+ vdev3vring0: memory@90110000 {
+ reg = <0 0x90110000 0 0x8000>;
+ no-map;
+ };
+
+ vdev3vring1: memory@90118000 {
+ reg = <0 0x90118000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table1: memory@901ff000 {
+ reg = <0 0x901ff000 0 0x1000>;
+ no-map;
+ };
+ };
+
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@@ -133,6 +195,37 @@ sound-wm8960 {
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
};
+
+ imx8qm-cm4-0 {
+ compatible = "fsl,imx8qm-cm4";
+ clocks = <&clk_dummy>;
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&lsio_mu5 0 1
+ &lsio_mu5 1 1
+ &lsio_mu5 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>;
+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
+
+ fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
+ fsl,entry-address = <0x34fe0000>;
+ };
+
+ imx8qm-cm4-1 {
+ compatible = "fsl,imx8qm-cm4";
+ clocks = <&clk_dummy>;
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&lsio_mu6 0 1
+ &lsio_mu6 1 1
+ &lsio_mu6 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>,
+ <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>;
+ power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>;
+
+ fsl,resource-id = <IMX_SC_R_M4_1_PID0>;
+ fsl,entry-address = <0x38fe0000>;
+ };
+
};
&adc0 {
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 6/9] arm64: dts: imx8qm-mek: add pwm and i2c in lvds subsystem
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
` (4 preceding siblings ...)
2024-06-10 20:46 ` [PATCH v2 5/9] arm64: dts: imx8qm-mek: add cm4 remote-proc and related memory region Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-10 20:46 ` [PATCH v2 7/9] arm64: dts: imx8qm-mek: add i2c in mipi[0,1] subsystem Frank Li
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Peng Fan
Add pwm[0,1] and i2c[0,1] in lvds subsystem.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 68 ++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index dbd478af2e474..3cf39c868e752 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -93,6 +93,22 @@ rsc_table1: memory@901ff000 {
};
};
+ lvds_backlight0: backlight-lvds0 {
+ compatible = "pwm-backlight";
+ pwms = <&qm_pwm_lvds0 0 100000 0>;
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <80>;
+ };
+
+ lvds_backlight1: backlight-lvds1 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm_lvds1 0 100000 0>;
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <80>;
+ };
+
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@@ -334,6 +350,20 @@ wm8960: audio-codec@1a {
};
};
+&i2c1_lvds0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1_lvds1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
@@ -449,6 +479,18 @@ &fec2 {
status = "okay";
};
+&qm_pwm_lvds0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_lvds0>;
+ status = "okay";
+};
+
+&pwm_lvds1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_lvds1>;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -675,6 +717,32 @@ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
>;
};
+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+ fsl,pins = <
+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+ fsl,pins = <
+ IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
+ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_pwm_lvds0: pwmlvds0grp {
+ fsl,pins = <
+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020
+ >;
+ };
+
+ pinctrl_pwm_lvds1: pwmlvds1grp {
+ fsl,pins = <
+ IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020
+ >;
+ };
+
pinctrl_sai0: sai0grp {
fsl,pins = <
IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 7/9] arm64: dts: imx8qm-mek: add i2c in mipi[0,1] subsystem
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
` (5 preceding siblings ...)
2024-06-10 20:46 ` [PATCH v2 6/9] arm64: dts: imx8qm-mek: add pwm and i2c in lvds subsystem Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-10 20:46 ` [PATCH v2 8/9] arm64: dts: imx8qm-mek: fix gpio number for reg_usdhc2_vmmc Frank Li
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Peng Fan
Add i2c node in mipi[0,1] subystem for imx8qm-mek.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 30 ++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 3cf39c868e752..e3a653be7dacc 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -364,6 +364,20 @@ &i2c1_lvds1 {
status = "okay";
};
+&i2c0_mipi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi0_lpi2c0>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c0_mipi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi1_lpi2c0>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
@@ -636,6 +650,22 @@ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
>;
};
+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
+ fsl,pins = <
+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
+ IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020
+ >;
+ };
+
+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
+ fsl,pins = <
+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
+ IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020
+ >;
+ };
+
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 8/9] arm64: dts: imx8qm-mek: fix gpio number for reg_usdhc2_vmmc
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
` (6 preceding siblings ...)
2024-06-10 20:46 ` [PATCH v2 7/9] arm64: dts: imx8qm-mek: add i2c in mipi[0,1] subsystem Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-10 20:46 ` [PATCH v2 9/9] arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodes Frank Li
2024-06-10 21:08 ` [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li, stable,
Peng Fan
The gpio in "reg_usdhc2_vmmc" should be 7 instead of 19.
Cc: stable@vger.kernel.org
Fixes: 307fd14d4b14 ("arm64: dts: imx: add imx8qm mek support")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index e3a653be7dacc..8ab75cc5b9aff 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -114,7 +114,7 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 9/9] arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodes
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
` (7 preceding siblings ...)
2024-06-10 20:46 ` [PATCH v2 8/9] arm64: dts: imx8qm-mek: fix gpio number for reg_usdhc2_vmmc Frank Li
@ 2024-06-10 20:46 ` Frank Li
2024-06-10 21:08 ` [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 20:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
Enable usb3.0 and related usb type C nodes.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 87 ++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 8ab75cc5b9aff..0f4132f342d89 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -6,6 +6,7 @@
/dts-v1/;
+#include <dt-bindings/usb/pd.h>
#include "imx8qm.dtsi"
/ {
@@ -109,6 +110,21 @@ lvds_backlight1: backlight-lvds1 {
default-brightness-level = <80>;
};
+ mux-controller {
+ compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec_mux>;
+ select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+ orientation-switch;
+
+ port {
+ usb3_data_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+ };
+
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@@ -321,6 +337,44 @@ gyrometer@69 {
compatible = "st,l3g4200d-gyro";
reg = <0x69>;
};
+
+ ptn5110: tcpc@51 {
+ compatible = "nxp,ptn5110", "tcpci";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x51>;
+ interrupt-parent = <&lsio_gpio4>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+
+ usb_con1: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "source";
+ data-role = "dual";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec_dr_sw: endpoint {
+ remote-endpoint = <&usb3_drd_sw>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb3_data_ss>;
+ };
+ };
+ };
+ };
+ };
};
&i2c1 {
@@ -525,6 +579,26 @@ &usdhc2 {
status = "okay";
};
+&usb3_phy {
+ status = "okay";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usbotg3_cdns3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb3_drd_sw: endpoint {
+ remote-endpoint = <&typec_dr_sw>;
+ };
+ };
+};
+
&sai0 {
#sound-dai-cells = <0>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
@@ -791,6 +865,19 @@ IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040
>;
};
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
+ >;
+ };
+
+ pinctrl_typec_mux: typecmuxgrp {
+ fsl,pins = <
+ IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60
+ IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi
2024-06-10 20:46 [PATCH v2 0/9] arm64: dts: imx8qm: add subsystem lvds and mipi Frank Li
` (8 preceding siblings ...)
2024-06-10 20:46 ` [PATCH v2 9/9] arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodes Frank Li
@ 2024-06-10 21:08 ` Frank Li
9 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2024-06-10 21:08 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dong Aisheng
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan, stable
On Mon, Jun 10, 2024 at 04:46:17PM -0400, Frank Li wrote:
> Add subsystem lvds and mipi. Add pwm and i2c in lvds and mipi.
> imx8qm-mek:
> - add remove-proc
> - fixed gpio number error for vmmc
> - add usb3 and typec
> - add pwm and i2c in lvds and mipi
Sorry, please forget these, a file missed to add.
Frank
>
> DTB_CHECK warning fixed by seperate patches.
> arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: usb@5b110000: usb@5b120000: 'port', 'usb-role-switch' do not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
> arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: usb@5b120000: 'port', 'usb-role-switch' do not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
>
> ** binding fix patch: https://lore.kernel.org/imx/20240606161509.3201080-1-Frank.Li@nxp.com/T/#u
>
> arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: interrupt-controller@56240000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
>
> ** binding fix patch: https://lore.kernel.org/imx/20240528071141.92003-1-alexander.stein@ew.tq-group.com/T/#me3425d580ba9a086866c3053ef854810ac7a0ef6
>
> arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: pwm@56244000: 'oneOf' conditional failed, one must be fixed:
> 'interrupts' is a required property
> 'interrupts-extended' is a required property
> from schema $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
>
> ** binding fix patch: https://lore.kernel.org/imx/dc9accba-78af-45ec-a516-b89f2d4f4b03@kernel.org/T/#t
>
> from schema $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
> arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: imx8qm-cm4-0: power-domains: [[15, 278], [15, 297]] is too short
> from schema $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
> arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: imx8qm-cm4-1: power-domains: [[15, 298], [15, 317]] is too short
>
> ** binding fix patch: https://lore.kernel.org/imx/20240606150030.3067015-1-Frank.Li@nxp.com/T/#u
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Changes in v2:
> Changes in v2:
> - split common lvds and mipi part to seperate dtsi file.
> - num-interpolated-steps = <100>
> - irq-steer add "fsl,imx8qm-irqsteer"
> - using mux-controller
> - move address-cells common dtsi
> - Link to v1: https://lore.kernel.org/r/20240606-imx8qm-dts-usb-v1-0-565721b64f25@nxp.com
>
> ---
> Frank Li (9):
> arm64: dts: imx8: add basic lvds and lvds2 subsystem
> arm64: dts: imx8qm: add lvds subsystem
> arm64: dts: imx8: add basic mipi subsystem
> arm64: dts: imx8qm: add mipi subsystem
> arm64: dts: imx8qm-mek: add cm4 remote-proc and related memory region
> arm64: dts: imx8qm-mek: add pwm and i2c in lvds subsystem
> arm64: dts: imx8qm-mek: add i2c in mipi[0,1] subsystem
> arm64: dts: imx8qm-mek: fix gpio number for reg_usdhc2_vmmc
> arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodes
>
> arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi | 63 +++++
> arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++
> arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++
> arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++
> arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 280 +++++++++++++++++++++-
> arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 77 ++++++
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 27 +++
> 7 files changed, 836 insertions(+), 1 deletion(-)
> ---
> base-commit: ee78a17615ad0cfdbbc27182b1047cd36c9d4d5f
> change-id: 20240606-imx8qm-dts-usb-9c55d2bfe526
>
> Best regards,
> ---
> Frank Li <Frank.Li@nxp.com>
>
^ permalink raw reply [flat|nested] 15+ messages in thread