From: Martin Schiller <ms@dev.tdt.de>
To: martin.blumenstingl@googlemail.com, hauke@hauke-m.de,
andrew@lunn.ch, f.fainelli@gmail.com, olteanv@gmail.com,
davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, ms@dev.tdt.de
Subject: [PATCH net-next v4 01/13] dt-bindings: net: dsa: lantiq,gswip: convert to YAML schema
Date: Tue, 11 Jun 2024 13:40:15 +0200 [thread overview]
Message-ID: <20240611114027.3136405-2-ms@dev.tdt.de> (raw)
In-Reply-To: <20240611114027.3136405-1-ms@dev.tdt.de>
Convert the lantiq,gswip bindings to YAML format.
Also add this new file to the MAINTAINERS file.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
---
.../bindings/net/dsa/lantiq,gswip.yaml | 195 ++++++++++++++++++
.../bindings/net/dsa/lantiq-gswip.txt | 146 -------------
MAINTAINERS | 1 +
3 files changed, 196 insertions(+), 146 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
delete mode 100644 Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
new file mode 100644
index 000000000000..14ef48d6a0ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
@@ -0,0 +1,195 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq GSWIP Ethernet switches
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+maintainers:
+ - Hauke Mehrtens <hauke@hauke-m.de>
+
+properties:
+ compatible:
+ enum:
+ - lantiq,xrx200-gswip
+ - lantiq,xrx300-gswip
+ - lantiq,xrx330-gswip
+
+ reg:
+ minItems: 3
+ maxItems: 3
+ reg-names:
+ items:
+ - const: switch
+ - const: mdio
+ - const: mii
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ compatible:
+ const: lantiq,xrx200-mdio
+
+ required:
+ - compatible
+
+ gphy-fw:
+ type: object
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+
+ compatible:
+ allOf:
+ - items:
+ - enum:
+ - lantiq,xrx200-gphy-fw
+ - lantiq,xrx300-gphy-fw
+ - lantiq,xrx330-gphy-fw
+ - const: lantiq,gphy-fw
+
+ lantiq,rcu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the RCU syscon
+
+ patternProperties:
+ "^gphy@[0-9a-f]+$":
+ type: object
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 255
+ description:
+ Offset of the GPHY firmware register in the RCU register range
+
+ resets:
+ items:
+ - description: GPHY reset line
+
+ reset-names:
+ items:
+ - const: gphy
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+ required:
+ - compatible
+ - lantiq,rcu
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ switch@e108000 {
+ compatible = "lantiq,xrx200-gswip";
+ reg = <0xe108000 0x3100>, /* switch */
+ <0xe10b100 0xd8>, /* mdio */
+ <0xe10b1d8 0x130>; /* mii */
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan3";
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&phy11>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&phy13>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "wan";
+ phy-mode = "rgmii";
+ phy-handle = <&phy5>;
+ };
+
+ port@6 {
+ reg = <0x6>;
+ ethernet = <ð0>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "lantiq,xrx200-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <0x11>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <0x13>;
+ };
+ };
+
+ gphy-fw {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
+ lantiq,rcu = <&rcu0>;
+
+ gphy@20 {
+ reg = <0x20>;
+
+ resets = <&reset0 31 30>;
+ reset-names = "gphy";
+ };
+
+ gphy@68 {
+ reg = <0x68>;
+
+ resets = <&reset0 29 28>;
+ reset-names = "gphy";
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
deleted file mode 100644
index 8bb1eff21cb1..000000000000
--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
+++ /dev/null
@@ -1,146 +0,0 @@
-Lantiq GSWIP Ethernet switches
-==================================
-
-Required properties for GSWIP core:
-
-- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
- xRX200 SoC
- "lantiq,xrx300-gswip" for the embedded GSWIP in the
- xRX300 SoC
- "lantiq,xrx330-gswip" for the embedded GSWIP in the
- xRX330 SoC
-- reg : memory range of the GSWIP core registers
- : memory range of the GSWIP MDIO registers
- : memory range of the GSWIP MII registers
-
-See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
-additional required and optional properties.
-
-
-Required properties for MDIO bus:
-- compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
- core of the xRX200 SoC and the PHYs connected to it.
-
-See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
-required and optional properties.
-
-
-Required properties for GPHY firmware loading:
-- compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
- "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
- "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
- for the loading of the firmware into the embedded
- GPHY core of the SoC.
-- lantiq,rcu : reference to the rcu syscon
-
-The GPHY firmware loader has a list of GPHY entries, one for each
-embedded GPHY
-
-- reg : Offset of the GPHY firmware register in the RCU
- register range
-- resets : list of resets of the embedded GPHY
-- reset-names : list of names of the resets
-
-Example:
-
-Ethernet switch on the VRX200 SoC:
-
-switch@e108000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "lantiq,xrx200-gswip";
- reg = < 0xe108000 0x3100 /* switch */
- 0xe10b100 0xd8 /* mdio */
- 0xe10b1d8 0x130 /* mii */
- >;
- dsa,member = <0 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan3";
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "rgmii";
- phy-handle = <&phy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy11>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy13>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "rgmii";
- phy-handle = <&phy5>;
- };
-
- port@6 {
- reg = <0x6>;
- ethernet = <ð0>;
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "lantiq,xrx200-mdio";
- reg = <0>;
-
- phy0: ethernet-phy@0 {
- reg = <0x0>;
- };
- phy1: ethernet-phy@1 {
- reg = <0x1>;
- };
- phy5: ethernet-phy@5 {
- reg = <0x5>;
- };
- phy11: ethernet-phy@11 {
- reg = <0x11>;
- };
- phy13: ethernet-phy@13 {
- reg = <0x13>;
- };
- };
-
- gphy-fw {
- compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
- lantiq,rcu = <&rcu0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gphy@20 {
- reg = <0x20>;
-
- resets = <&reset0 31 30>;
- reset-names = "gphy";
- };
-
- gphy@68 {
- reg = <0x68>;
-
- resets = <&reset0 29 28>;
- reset-names = "gphy";
- };
- };
-};
diff --git a/MAINTAINERS b/MAINTAINERS
index cd3277a98cfe..ca1050f6691b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12449,6 +12449,7 @@ LANTIQ / INTEL Ethernet drivers
M: Hauke Mehrtens <hauke@hauke-m.de>
L: netdev@vger.kernel.org
S: Maintained
+F: Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
F: drivers/net/dsa/lantiq_gswip.c
F: drivers/net/dsa/lantiq_pce.h
F: drivers/net/ethernet/lantiq_xrx200.c
--
2.39.2
next prev parent reply other threads:[~2024-06-11 11:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-11 11:40 [PATCH net-next v4 00/13] net: dsa: lantiq_gswip: code improvements Martin Schiller
2024-06-11 11:40 ` Martin Schiller [this message]
2024-06-11 12:51 ` [PATCH net-next v4 01/13] dt-bindings: net: dsa: lantiq,gswip: convert to YAML schema Rob Herring (Arm)
2024-06-11 13:17 ` Martin Schiller
2024-06-11 13:27 ` Rob Herring
2024-06-11 13:48 ` Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 02/13] dt-bindings: net: dsa: lantiq,gswip: Add missing CPU port phy-mode and fixed-link to example Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 03/13] net: dsa: lantiq_gswip: Only allow phy-mode = "internal" on the CPU port Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 04/13] net: dsa: lantiq_gswip: add terminating \n where missing Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 05/13] net: dsa: lantiq_gswip: Use dev_err_probe where appropriate Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 06/13] net: dsa: lantiq_gswip: Don't manually call gswip_port_enable() Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 07/13] net: dsa: lantiq_gswip: do also enable or disable cpu port Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 08/13] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in gswip_port_change_mtu() Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 09/13] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 10/13] net: dsa: lantiq_gswip: Consistently use macros for the mac bridge table Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 11/13] net: dsa: lantiq_gswip: Remove dead code from gswip_add_single_port_br() Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 12/13] net: dsa: lantiq_gswip: Update comments in gswip_port_vlan_filtering() Martin Schiller
2024-06-11 11:40 ` [PATCH net-next v4 13/13] net: dsa: lantiq_gswip: Improve error message in gswip_port_fdb() Martin Schiller
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