From: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@outlook.com>,
Chao Wei <chao.wei@sophgo.com>
Cc: "Albert Ou" <aou@eecs.berkeley.edu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Miquèl Raynal" <miquel.raynal@bootlin.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org,
"Thomas Bonnefille" <thomas.bonnefille@bootlin.com>
Subject: [PATCH v2 1/6] riscv: dts: sophgo: Put sdhci compatible in dt of specific SoC
Date: Wed, 12 Jun 2024 10:02:31 +0200 [thread overview]
Message-ID: <20240612-sg2002-v2-1-19a585af6846@bootlin.com> (raw)
In-Reply-To: <20240612-sg2002-v2-0-19a585af6846@bootlin.com>
Remove SDHCI compatible for CV1800b from common dtsi file to put it in
the specific dtsi file of the CV1800b.
This commits aims at following the same guidelines as in the other nodes
of the CV18XX family.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 1 -
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index ec9530972ae2..b9cd51457b4c 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -25,3 +25,7 @@ &clint {
&clk {
compatible = "sophgo,cv1800-clk";
};
+
+&sdhci0 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..7247c7c3013c 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -288,7 +288,6 @@ uart4: serial@41c0000 {
};
sdhci0: mmc@4310000 {
- compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4310000 0x1000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD0>,
--
2.45.2
next prev parent reply other threads:[~2024-06-12 8:05 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 8:02 [PATCH v2 0/6] Add board support for Sipeed LicheeRV Nano Thomas Bonnefille
2024-06-12 8:02 ` Thomas Bonnefille [this message]
2024-06-12 10:47 ` [PATCH v2 1/6] riscv: dts: sophgo: Put sdhci compatible in dt of specific SoC Inochi Amaoto
2024-06-16 23:58 ` Yixun Lan
2024-06-17 3:36 ` Inochi Amaoto
2024-06-17 9:16 ` Thomas Bonnefille
2024-06-17 13:16 ` Jisheng Zhang
2024-06-17 15:40 ` Conor Dooley
2024-06-17 15:57 ` Samuel Holland
2024-06-18 4:20 ` Jisheng Zhang
2024-06-18 6:36 ` Inochi Amaoto
2024-06-12 8:02 ` [PATCH v2 2/6] dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic Thomas Bonnefille
2024-06-12 15:30 ` Rob Herring
2024-06-12 16:45 ` Conor Dooley
2024-06-12 8:02 ` [PATCH v2 3/6] dt-bindings: timer: Add SOPHGO SG2002 clint Thomas Bonnefille
2024-06-12 16:46 ` Conor Dooley
2024-06-12 8:02 ` [PATCH v2 4/6] dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles Thomas Bonnefille
2024-06-12 16:46 ` Conor Dooley
2024-06-12 8:02 ` [PATCH v2 5/6] riscv: dts: sophgo: Add initial SG2002 SoC device tree Thomas Bonnefille
2024-06-17 16:01 ` Samuel Holland
2024-06-12 8:02 ` [PATCH v2 6/6] riscv: dts: sophgo: Add LicheeRV Nano board " Thomas Bonnefille
2024-06-20 1:00 ` Inochi Amaoto
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