From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D774815253B for ; Thu, 13 Jun 2024 19:17:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718306241; cv=none; b=hSiEy8S9n4visw52Rwex13UoVk2aPfOxBzC2F8kBBfLMkxZwoc9y6NB88AJAMMwb5X55+K7nEytLzMOFcv7i2oRLPi6qB2WTf3rNqd0IjC6x2zJ2OWobZRi2NOGeyLA9Pw2utd0znUeMZAkHVNFv4C2F1ZDOUS+dqy3CrSH74bw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718306241; c=relaxed/simple; bh=+jnJtiUScAEX7YebGNkKf8lf6RqHQioTg5h1y/TviSY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LeEFcyUDoY0WbrwTBiL38NqCbUJVeCKCMWwf2zG57BmQ/KceZwyFoe1byHfys0x9/jnFEd/mkE8UZRucN61icguBKPUBceBZQZDKB7/vbjbDnu9vRR3rAAjGYmBOTiYVQKG0riRHGjT0MzxfgvmArrVEivM6sJJzq+gG8HrEkYw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=PghC1xDV; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="PghC1xDV" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-1f64ecb1766so11615115ad.1 for ; Thu, 13 Jun 2024 12:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1718306239; x=1718911039; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d2si2x/qxMiiRgx/ptA73I3ih5KSBTyIVIweBGPWOt8=; b=PghC1xDVcvoeRzTkSxuMFXK0jJO/4JFGVDpQCQYwx1JDHGatOuKUhsvMC/T9XTVxZq ts7INWTFFDqwPdVnfDq2EgnnvjRCR6KBm4dKNdeAoWJYGtgmWcWPw9VEQYqxI5slI36m GZfHy72ZjoOaV1e7sU5iZLj2n5pHPe3n5Z/DEhAmykCmkAaK+2qcuPwCAVK9Cw8H5QUL y8Mlvvce2YZVSkw9XsNl9DHOUX+CsSOp4l4rl0Uuo4jvAbHOjVkREnwzTyNgoCD5RCrW yIkGBuD4W1jKiodGmintUg1KaOm9/WwfI7awiv9dje6cXPrTg1vnI8264qAUUK122VnM n+pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718306239; x=1718911039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d2si2x/qxMiiRgx/ptA73I3ih5KSBTyIVIweBGPWOt8=; b=ij40+kS4+Z6vSn9Y8J6ykt9pfyAFyvv6W/GPr9sv6Y5FMf1mPT+O2BKfy0qcM0hvX1 adUvirXghLQHpzKpLkn/hd5xEn1iTjq9S6qoaQa0cmgX5pXKSB3iPGSby8ObiOmr7WRB 7KtzbWAIGJuxMyl67QYnxPH2AIUaQAjhMb0YLlDeSFdTJtfk2ZQ8RLBt7VuprUomI5CP NnhGaQGNG+hpi6gmyChORif8qy5Q8GycpBd3EG4Tk/kXe3lUxrPJjLJTEt/WjZcDE+qb 5bZsbgVoytxJ4puVecJCbUWR8qNZ+R+EhDQL+iWqGlXW3e7reTcYYzGSacfDmvz8sYcB rRnQ== X-Forwarded-Encrypted: i=1; AJvYcCWuKQozq9cd1fNORMyucqS5NlOfaIOKOG+IZgZPrbjXxhqGbExl6C+msTB93g7Lfpm8cD8JksPhwNpns1nDKDqQivNGsH9Y7kENGQ== X-Gm-Message-State: AOJu0YwxllTtfBgeCcsUXxRdgVLij80lsEa6rDXUo1bN4g+4UYrlKmKv pHcUYAwGF4xKkz+kopUvpHOamVeDPV5ehxw/wAD8EsC1t3xThN+VPvnR83ETYWM= X-Google-Smtp-Source: AGHT+IEe/pgm4wbdzYk9w01vIQjdm01pqBBmuWzC0VnQ7Vhdd+iuX8Zf6okO8XfjDwZx3EhOCo7asg== X-Received: by 2002:a17:903:2341:b0:1f6:7ee8:8935 with SMTP id d9443c01a7336-1f8629fef3bmr7650085ad.59.1718306239110; Thu, 13 Jun 2024 12:17:19 -0700 (PDT) Received: from jesse-desktop.. (pool-108-26-179-17.bstnma.fios.verizon.net. [108.26.179.17]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm17471015ad.106.2024.06.13.12.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 12:17:18 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Andrew Jones , Jesse Taube , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/6] RISC-V: Check scalar unaligned access on all CPUs Date: Thu, 13 Jun 2024 15:16:12 -0400 Message-ID: <20240613191616.2101821-4-jesse@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240613191616.2101821-1-jesse@rivosinc.com> References: <20240613191616.2101821-1-jesse@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Originally, the check_unaligned_access_emulated_all_cpus function only checked the boot hart. This fixes the function to check all harts. Check for Zicclsm before checking for unaligned access. This will greatly reduce the boot up time as finding the access speed is no longer necessary. Signed-off-by: Jesse Taube --- V1 -> V2: - New patch --- arch/riscv/kernel/traps_misaligned.c | 23 ++++++---------------- arch/riscv/kernel/unaligned_access_speed.c | 23 +++++++++++++--------- 2 files changed, 20 insertions(+), 26 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index b62d5a2f4541..8fadbe00dd62 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -526,31 +526,17 @@ int handle_misaligned_store(struct pt_regs *regs) return 0; } -static bool check_unaligned_access_emulated(int cpu) +static void check_unaligned_access_emulated(struct work_struct *unused) { + int cpu = smp_processor_id(); long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); unsigned long tmp_var, tmp_val; - bool misaligned_emu_detected; *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN; __asm__ __volatile__ ( " "REG_L" %[tmp], 1(%[ptr])\n" : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); - - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED); - /* - * If unaligned_ctl is already set, this means that we detected that all - * CPUS uses emulated misaligned access at boot time. If that changed - * when hotplugging the new cpu, this is something we don't handle. - */ - if (unlikely(unaligned_ctl && !misaligned_emu_detected)) { - pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n"); - while (true) - cpu_relax(); - } - - return misaligned_emu_detected; } bool check_unaligned_access_emulated_all_cpus(void) @@ -562,8 +548,11 @@ bool check_unaligned_access_emulated_all_cpus(void) * accesses emulated since tasks requesting such control can run on any * CPU. */ + schedule_on_each_cpu(check_unaligned_access_emulated); + for_each_online_cpu(cpu) - if (!check_unaligned_access_emulated(cpu)) + if (per_cpu(misaligned_access_speed, cpu) + != RISCV_HWPROBE_MISALIGNED_EMULATED) return false; unaligned_ctl = true; diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index a9a6bcb02acf..70c1588fc353 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -259,23 +259,28 @@ static int check_unaligned_access_speed_all_cpus(void) kfree(bufs); return 0; } +#endif /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ static int check_unaligned_access_all_cpus(void) { - bool all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); + bool all_cpus_emulated; + int cpu; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) { + for_each_online_cpu(cpu) { + per_cpu(misaligned_access_speed, cpu) = RISCV_HWPROBE_MISALIGNED_FAST; + } + return 0; + } + + all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); + +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS if (!all_cpus_emulated) return check_unaligned_access_speed_all_cpus(); +#endif return 0; } -#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static int check_unaligned_access_all_cpus(void) -{ - check_unaligned_access_emulated_all_cpus(); - - return 0; -} -#endif arch_initcall(check_unaligned_access_all_cpus); -- 2.43.0