* [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95
@ 2024-06-17 20:16 Frank Li
2024-06-17 20:16 ` [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li
` (10 more replies)
0 siblings, 11 replies; 24+ messages in thread
From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li, Jason Liu, Conor Dooley
Fixed 8mp EP mode problem.
imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid
confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to
pci-imx.c to avoid confuse.
Using callback to reduce switch case for core reset and refclk.
Add iMX8QXP and iMX8QM support. PHY driver ref:
https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git/commit/?h=next&id=82c56b6dd24fcdf811f2b47b72e5585c8a79b685
Base on linux 6.10-rc1
To: Richard Zhu <hongxing.zhu@nxp.com>
To: Lucas Stach <l.stach@pengutronix.de>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kw@linux.com>
To: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
To: Shawn Guo <shawnguo@kernel.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
To: Pengutronix Kernel Team <kernel@pengutronix.de>
To: Fabio Estevam <festevam@gmail.com>
To: NXP Linux Team <linux-imx@nxp.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Liam Girdwood <lgirdwood@gmail.com>
To: Mark Brown <broonie@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-pci@vger.kernel.org
Cc: imx@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: bpf@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Changes in v6:
- Base on Linux 6.10-rc1 by Bjorn's required.
- Remove imx95 LUT patch because it need more time to work out the
solution. This patch add 8qxp and 8qm and support and some bug fixes.
- Link to v5: https://lore.kernel.org/r/20240528-pci2_upstream-v5-0-750aa7edb8e2@nxp.com
Changes in v5:
- Rebase to linux-pci next. fix conflict with gpiod change
- Add rob and cornor's review tag
- Link to v4: https://lore.kernel.org/r/20240507-pci2_upstream-v4-0-e8c80d874057@nxp.com
Changes in v4:
- Improve comment message for patch 1 and 2.
- Rework commit message for patch 3 and add mani's review tag
- Remove file rename patch and update maintainer patch
- [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
remove extra space.
keep original comments format (wrap at 80 column width)
update error message "'Failed to enable PCIe REFCLK'"
- PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback
keep exact the logic as original code
- Add patch to update comment about workaround ERR010728
- Add patch about help function imx_pcie_match_device()
- Using bus device notify to update LUT information for imx95 to avoid
parse iommu-map and msi-map in driver code. Bus notify will better and
only update lut when device added.
- split patch call PHY interface function.
- Improve commit message for imx8q. remove local-address dts proptery. and
use standard "range" to convert cpu address to bus address.
- Check entry in cpu_fix function is too late. Check it at probe
- Link to v3: https://lore.kernel.org/r/20240402-pci2_upstream-v3-0-803414bdb430@nxp.com
Changes in v3:
- Add an EP fixed patch
PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
- Add 8qxp rc support
dt-bing yaml pass binding check
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml
LINT Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb
- Link to v2: https://lore.kernel.org/r/20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com
Changes in v2:
- remove file to 'pcie-imx.c'
- keep CONFIG unchange.
- Link to v1: https://lore.kernel.org/r/20240227-pci2_upstream-v1-0-b952f8333606@nxp.com
---
Frank Li (6):
PCI: imx6: Rename imx6_* with imx_*
PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
PCI: imx6: Simplify switch-case logic by involve core_reset callback
PCI: imx6: Improve comment for workaround ERR010728
PCI: imx6: Consolidate redundant if-checks
PCI: imx6: Call: Common PHY API to set mode, speed, and submode
Richard Zhu (4):
PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP
PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string
PCI: imx6: Add i.MX8Q PCIe root complex (RC) support
.../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 +
drivers/pci/controller/dwc/pci-imx6.c | 1004 +++++++++++---------
2 files changed, 551 insertions(+), 469 deletions(-)
---
base-commit: d9b6deec8e0a49b3ade6559b68c6a77ded0f4a8d
change-id: 20240227-pci2_upstream-0cdd19a15163
Best regards,
---
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-29 12:23 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Frank Li ` (9 subsequent siblings) 10 siblings, 1 reply; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li From: Richard Zhu <hongxing.zhu@nxp.com> Add IMX6_PCIE_FLAG_HAS_APP_RESET flag to IMX8MM_EP and IMX8MP_EP drvdata. This flag was overlooked during code restructuring. It is crucial to release the app-reset from the System Reset Controller before initiating LTSSM to rectify the issue Fixes: 0c9651c21f2a ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 917c69edee1d5..9a71b8aa09b3c 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1578,7 +1578,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1589,7 +1590,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP_EP] = { .variant = IMX8MP_EP, - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP 2024-06-17 20:16 ` [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li @ 2024-06-29 12:23 ` Manivannan Sadhasivam 0 siblings, 0 replies; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-06-29 12:23 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Mon, Jun 17, 2024 at 04:16:37PM -0400, Frank Li wrote: > From: Richard Zhu <hongxing.zhu@nxp.com> > > Add IMX6_PCIE_FLAG_HAS_APP_RESET flag to IMX8MM_EP and IMX8MP_EP drvdata. > This flag was overlooked during code restructuring. It is crucial to > release the app-reset from the System Reset Controller before initiating > LTSSM to rectify the issue > > Fixes: 0c9651c21f2a ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET") > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > drivers/pci/controller/dwc/pci-imx6.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 917c69edee1d5..9a71b8aa09b3c 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1578,7 +1578,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > }, > [IMX8MM_EP] = { > .variant = IMX8MM_EP, > - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, > + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | > + IMX6_PCIE_FLAG_HAS_PHYDRV, > .mode = DW_PCIE_EP_TYPE, > .gpr = "fsl,imx8mm-iomuxc-gpr", > .clk_names = imx8mm_clks, > @@ -1589,7 +1590,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > }, > [IMX8MP_EP] = { > .variant = IMX8MP_EP, > - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, > + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | > + IMX6_PCIE_FLAG_HAS_PHYDRV, > .mode = DW_PCIE_EP_TYPE, > .gpr = "fsl,imx8mp-iomuxc-gpr", > .clk_names = imx8mm_clks, > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li 2024-06-17 20:16 ` [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-29 13:05 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 03/10] PCI: imx6: Rename imx6_* with imx_* Frank Li ` (8 subsequent siblings) 10 siblings, 1 reply; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li, Jason Liu From: Richard Zhu <hongxing.zhu@nxp.com> Correct occasional MSI triggering failures in i.MX8MP PCIe EP by apply 64KB hardware alignment requirement. MSI triggering fail if the outbound MSI memory region (ep->msi_mem) is not aligned to 64KB. In dw_pcie_ep_init(): ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, epc->mem->window.page_size); Set ep->page_size to match drvdata::epc_features::align since different SOCs have different alignment requirements. Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Jason Liu <jason.hui.liu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 9a71b8aa09b3c..ca9a000c9a96d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + ep->page_size = imx6_pcie->drvdata->epc_features->align; + ret = dw_pcie_ep_init(ep); if (ret) { dev_err(dev, "failed to initialize endpoint\n"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI 2024-06-17 20:16 ` [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Frank Li @ 2024-06-29 13:05 ` Manivannan Sadhasivam 2024-07-01 18:32 ` Frank Li 0 siblings, 1 reply; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-06-29 13:05 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Jason Liu On Mon, Jun 17, 2024 at 04:16:38PM -0400, Frank Li wrote: > From: Richard Zhu <hongxing.zhu@nxp.com> > > Correct occasional MSI triggering failures in i.MX8MP PCIe EP by apply 64KB > hardware alignment requirement. > > MSI triggering fail if the outbound MSI memory region (ep->msi_mem) is not > aligned to 64KB. > > In dw_pcie_ep_init(): > > ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > epc->mem->window.page_size); > So this is an alignment restriction w.r.t iATU. In that case, we should be passing 'pci_epc_features::align' instead? - Mani > Set ep->page_size to match drvdata::epc_features::align since different > SOCs have different alignment requirements. > > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Acked-by: Jason Liu <jason.hui.liu@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 9a71b8aa09b3c..ca9a000c9a96d 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > + ep->page_size = imx6_pcie->drvdata->epc_features->align; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI 2024-06-29 13:05 ` Manivannan Sadhasivam @ 2024-07-01 18:32 ` Frank Li 2024-07-06 17:39 ` Manivannan Sadhasivam 0 siblings, 1 reply; 24+ messages in thread From: Frank Li @ 2024-07-01 18:32 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Jason Liu On Sat, Jun 29, 2024 at 06:35:25PM +0530, Manivannan Sadhasivam wrote: > On Mon, Jun 17, 2024 at 04:16:38PM -0400, Frank Li wrote: > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > Correct occasional MSI triggering failures in i.MX8MP PCIe EP by apply 64KB > > hardware alignment requirement. > > > > MSI triggering fail if the outbound MSI memory region (ep->msi_mem) is not > > aligned to 64KB. > > > > In dw_pcie_ep_init(): > > > > ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > > epc->mem->window.page_size); > > > > So this is an alignment restriction w.r.t iATU. In that case, we should be > passing 'pci_epc_features::align' instead? pci_epc_features::align already set. pci_epc_mem_alloc_addr( ... align_size = ALIGN(size, mem->window.page_size); order = pci_epc_mem_get_order(mem, align_size); ... } but pci_epc_mem_alloc_addr() align to page_size, instead of pci_epc_features::align. Frank > > - Mani > > > Set ep->page_size to match drvdata::epc_features::align since different > > SOCs have different alignment requirements. > > > > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Acked-by: Jason Liu <jason.hui.liu@nxp.com> > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > drivers/pci/controller/dwc/pci-imx6.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index 9a71b8aa09b3c..ca9a000c9a96d 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > > > + ep->page_size = imx6_pcie->drvdata->epc_features->align; > > + > > ret = dw_pcie_ep_init(ep); > > if (ret) { > > dev_err(dev, "failed to initialize endpoint\n"); > > > > -- > > 2.34.1 > > > > -- > மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI 2024-07-01 18:32 ` Frank Li @ 2024-07-06 17:39 ` Manivannan Sadhasivam 0 siblings, 0 replies; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-07-06 17:39 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Jason Liu On Mon, Jul 01, 2024 at 02:32:59PM -0400, Frank Li wrote: > On Sat, Jun 29, 2024 at 06:35:25PM +0530, Manivannan Sadhasivam wrote: > > On Mon, Jun 17, 2024 at 04:16:38PM -0400, Frank Li wrote: > > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > > > Correct occasional MSI triggering failures in i.MX8MP PCIe EP by apply 64KB > > > hardware alignment requirement. > > > > > > MSI triggering fail if the outbound MSI memory region (ep->msi_mem) is not > > > aligned to 64KB. > > > > > > In dw_pcie_ep_init(): > > > > > > ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > > > epc->mem->window.page_size); > > > > > > > So this is an alignment restriction w.r.t iATU. In that case, we should be > > passing 'pci_epc_features::align' instead? > > pci_epc_features::align already set. > > pci_epc_mem_alloc_addr( > ... > align_size = ALIGN(size, mem->window.page_size); > order = pci_epc_mem_get_order(mem, align_size); > ... > } > > but pci_epc_mem_alloc_addr() align to page_size, instead of > pci_epc_features::align. > 'window.page_size' is set to what is passed as 'page_size' argument to pci_epc_mem_init(). In this case, 'ep->page_size' is passed which corresponds to size of pages that can be allocated within the memory window. Default value of 'ep->page_size' is PAGE_SIZE which is most likely 4K. So if your hardware cannot allocate 4K pages within the memory window, then it doesn't support splitting this OB region into 4K pages. But this has nothing to do with alignment AFAIU since epc_features::align is used for IB memory. This 'page_size' argument was introduced for some TI SoC that doesn't handle PAGE_SIZE splitting of OB memory window. Reference: 52c9285d4745 ("PCI: endpoint: Add support for configurable page size") Can you check if your SoC also suffers from the same limitation? If so, then you should modify the commit message to make it clear. - Mani -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 03/10] PCI: imx6: Rename imx6_* with imx_* 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li 2024-06-17 20:16 ` [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li 2024-06-17 20:16 ` [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-17 20:16 ` [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li ` (7 subsequent siblings) 10 siblings, 0 replies; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li Since this driver has evolved to support other i.MX SoCs such as i.MX7/8/9, let's rename the 'imx6' prefix to 'imx' to avoid confusion. But the driver name is left unchanged to avoid breaking userspace scripts Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 760 +++++++++++++++++----------------- 1 file changed, 380 insertions(+), 380 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index ca9a000c9a96d..47134e2dfecf2 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,9 +55,9 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) -#define to_imx6_pcie(x) dev_get_drvdata((x)->dev) +#define to_imx_pcie(x) dev_get_drvdata((x)->dev) -enum imx6_pcie_variants { +enum imx_pcie_variants { IMX6Q, IMX6SX, IMX6QP, @@ -72,25 +72,25 @@ enum imx6_pcie_variants { IMX95_EP, }; -#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) -#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) -#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) -#define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) -#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) -#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) -#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) -#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_IMX_PHY BIT(0) +#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1) +#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3) +#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) +#define IMX_PCIE_FLAG_HAS_SERDES BIT(6) +#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) -#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) +#define imx_check_flag(pci, val) (pci->drvdata->flags & val) -#define IMX6_PCIE_MAX_CLKS 6 +#define IMX_PCIE_MAX_CLKS 6 -#define IMX6_PCIE_MAX_INSTANCES 2 +#define IMX_PCIE_MAX_INSTANCES 2 -struct imx6_pcie; +struct imx_pcie; -struct imx6_pcie_drvdata { - enum imx6_pcie_variants variant; +struct imx_pcie_drvdata { + enum imx_pcie_variants variant; enum dw_pcie_device_mode mode; u32 flags; int dbi_length; @@ -99,18 +99,18 @@ struct imx6_pcie_drvdata { const u32 clks_cnt; const u32 ltssm_off; const u32 ltssm_mask; - const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; - const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; - int (*init_phy)(struct imx6_pcie *pcie); + int (*init_phy)(struct imx_pcie *pcie); }; -struct imx6_pcie { +struct imx_pcie { struct dw_pcie *pci; int reset_gpio; bool gpio_active_high; bool link_is_up; - struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; + struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; @@ -131,7 +131,7 @@ struct imx6_pcie { /* power domain for pcie phy */ struct device *pd_pcie_phy; struct phy *phy; - const struct imx6_pcie_drvdata *drvdata; + const struct imx_pcie_drvdata *drvdata; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -186,28 +186,28 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) -static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) +static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie) { - WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && - imx6_pcie->drvdata->variant != IMX8MQ_EP && - imx6_pcie->drvdata->variant != IMX8MM && - imx6_pcie->drvdata->variant != IMX8MM_EP && - imx6_pcie->drvdata->variant != IMX8MP && - imx6_pcie->drvdata->variant != IMX8MP_EP); - return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; + WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && + imx_pcie->drvdata->variant != IMX8MQ_EP && + imx_pcie->drvdata->variant != IMX8MM && + imx_pcie->drvdata->variant != IMX8MM_EP && + imx_pcie->drvdata->variant != IMX8MP && + imx_pcie->drvdata->variant != IMX8MP_EP); + return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } -static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, IMX95_PCIE_PHY_CR_PARA_SEL, IMX95_PCIE_PHY_CR_PARA_SEL); - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL, IMX95_PCIE_REF_USE_PAD, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, IMX95_PCIE_REF_CLKEN, IMX95_PCIE_REF_CLKEN); @@ -215,9 +215,9 @@ static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) return 0; } -static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) +static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) { - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; unsigned int mask, val, mode, id; if (drvdata->mode == DW_PCIE_EP_TYPE) @@ -225,7 +225,7 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) else mode = PCI_EXP_TYPE_ROOT_PORT; - id = imx6_pcie->controller_id; + id = imx_pcie->controller_id; /* If mode_mask[id] is zero, means each controller have its individual gpr */ if (!drvdata->mode_mask[id]) @@ -234,12 +234,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) mask = drvdata->mode_mask[id]; val = mode << (ffs(mask) - 1); - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); } -static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) +static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; bool val; u32 max_iterations = 10; u32 wait_counter = 0; @@ -258,9 +258,9 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) return -ETIMEDOUT; } -static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) +static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 val; int ret; @@ -270,24 +270,24 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) val |= PCIE_PHY_CTRL_CAP_ADR; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; val = PCIE_PHY_CTRL_DATA(addr); dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); - return pcie_phy_poll_ack(imx6_pcie, false); + return pcie_phy_poll_ack(imx_pcie, false); } /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ -static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) +static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 phy_ctl; int ret; - ret = pcie_phy_wait_ack(imx6_pcie, addr); + ret = pcie_phy_wait_ack(imx_pcie, addr); if (ret) return ret; @@ -295,7 +295,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) phy_ctl = PCIE_PHY_CTRL_RD; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -304,18 +304,18 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) /* deassert Read signal */ dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); - return pcie_phy_poll_ack(imx6_pcie, false); + return pcie_phy_poll_ack(imx_pcie, false); } -static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) +static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 var; int ret; /* write addr */ /* cap addr */ - ret = pcie_phy_wait_ack(imx6_pcie, addr); + ret = pcie_phy_wait_ack(imx_pcie, addr); if (ret) return ret; @@ -326,7 +326,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) var |= PCIE_PHY_CTRL_CAP_DAT; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -335,7 +335,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ - ret = pcie_phy_poll_ack(imx6_pcie, false); + ret = pcie_phy_poll_ack(imx_pcie, false); if (ret) return ret; @@ -344,7 +344,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack */ - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -353,7 +353,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ - ret = pcie_phy_poll_ack(imx6_pcie, false); + ret = pcie_phy_poll_ack(imx_pcie, false); if (ret) return ret; @@ -362,74 +362,74 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) return 0; } -static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) { /* TODO: Currently this code assumes external oscillator is being used */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), + regmap_update_bits(imx_pcie->iomuxc_gpr, + imx_pcie_grp_offset(imx_pcie), IMX8MQ_GPR_PCIE_REF_USE_PAD, IMX8MQ_GPR_PCIE_REF_USE_PAD); /* * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. */ - if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), + if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) + regmap_update_bits(imx_pcie->iomuxc_gpr, + imx_pcie_grp_offset(imx_pcie), IMX8MQ_GPR_PCIE_VREG_BYPASS, 0); return 0; } -static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); return 0; } -static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); /* configure constant input signal to the pcie ctrl and phy */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_LOS_LEVEL, 9 << 4); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN1, - imx6_pcie->tx_deemph_gen1 << 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, - imx6_pcie->tx_deemph_gen2_3p5db << 6); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, - imx6_pcie->tx_deemph_gen2_6db << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_FULL, - imx6_pcie->tx_swing_full << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_swing_full << 18); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_LOW, - imx6_pcie->tx_swing_low << 25); + imx_pcie->tx_swing_low << 25); return 0; } -static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); - return imx6_pcie_init_phy(imx6_pcie); + return imx_pcie_init_phy(imx_pcie); } -static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) +static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie) { u32 val; - struct device *dev = imx6_pcie->pci->dev; + struct device *dev = imx_pcie->pci->dev; - if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, + if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, IOMUXC_GPR22, val, val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, PHY_PLL_LOCK_WAIT_USLEEP_MAX, @@ -437,19 +437,19 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) dev_err(dev, "PCIe PLL lock timeout\n"); } -static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) +static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie) { unsigned long phy_rate = 0; int mult, div; u16 val; int i; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) return 0; - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) - if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) - phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) + if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0) + phy_rate = clk_get_rate(imx_pcie->clks[i].clk); switch (phy_rate) { case 125000000: @@ -467,46 +467,46 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) div = 1; break; default: - dev_err(imx6_pcie->pci->dev, + dev_err(imx_pcie->pci->dev, "Unsupported PHY reference clock rate %lu\n", phy_rate); return -EINVAL; } - pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); + pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << PCIE_PHY_MPLL_MULTIPLIER_SHIFT); val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; - pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); + pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); - pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); + pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val); val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; val |= PCIE_PHY_ATEOVRD_EN; - pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); + pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val); return 0; } -static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) +static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie) { u16 tmp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) return; - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); usleep_range(2000, 3000); - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); } #ifdef CONFIG_ARM @@ -545,22 +545,22 @@ static int imx6q_pcie_abort_handler(unsigned long addr, } #endif -static int imx6_pcie_attach_pd(struct device *dev) +static int imx_pcie_attach_pd(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); struct device_link *link; /* Do nothing when in a single power domain */ if (dev->pm_domain) return 0; - imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); - if (IS_ERR(imx6_pcie->pd_pcie)) - return PTR_ERR(imx6_pcie->pd_pcie); + imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); + if (IS_ERR(imx_pcie->pd_pcie)) + return PTR_ERR(imx_pcie->pd_pcie); /* Do nothing when power domain missing */ - if (!imx6_pcie->pd_pcie) + if (!imx_pcie->pd_pcie) return 0; - link = device_link_add(dev, imx6_pcie->pd_pcie, + link = device_link_add(dev, imx_pcie->pd_pcie, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); @@ -569,11 +569,11 @@ static int imx6_pcie_attach_pd(struct device *dev) return -EINVAL; } - imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); - if (IS_ERR(imx6_pcie->pd_pcie_phy)) - return PTR_ERR(imx6_pcie->pd_pcie_phy); + imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); + if (IS_ERR(imx_pcie->pd_pcie_phy)) + return PTR_ERR(imx_pcie->pd_pcie_phy); - link = device_link_add(dev, imx6_pcie->pd_pcie_phy, + link = device_link_add(dev, imx_pcie->pd_pcie_phy, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); @@ -585,20 +585,20 @@ static int imx6_pcie_attach_pd(struct device *dev) return 0; } -static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) +static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) { unsigned int offset; int ret = 0; - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); break; case IMX6QP: case IMX6Q: /* power up core phy and enable ref clock */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); /* * the async reset input need ref clock to sync internally, @@ -607,7 +607,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) * add one ~10us delay here. */ usleep_range(10, 100); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); break; case IMX7D: @@ -620,15 +620,15 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX8MQ_EP: case IMX8MP: case IMX8MP_EP: - offset = imx6_pcie_grp_offset(imx6_pcie); + offset = imx_pcie_grp_offset(imx_pcie); /* * Set the over ride low and enabled * make sure that REF_CLK is turned on. */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); break; @@ -637,19 +637,19 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) return ret; } -static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) +static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) { - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6QP: case IMX6Q: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); break; case IMX7D: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; @@ -658,17 +658,17 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) } } -static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) +static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; int ret; - ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); if (ret) return ret; - ret = imx6_pcie_enable_ref_clk(imx6_pcie); + ret = imx_pcie_enable_ref_clk(imx_pcie); if (ret) { dev_err(dev, "unable to enable pcie ref clock\n"); goto err_ref_clk; @@ -679,41 +679,41 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) return 0; err_ref_clk: - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); return ret; } -static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) +static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx6_pcie_disable_ref_clk(imx6_pcie); - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + imx_pcie_disable_ref_clk(imx_pcie); + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } -static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) +static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { - reset_control_assert(imx6_pcie->pciephy_reset); - reset_control_assert(imx6_pcie->apps_reset); + reset_control_assert(imx_pcie->pciephy_reset); + reset_control_assert(imx_pcie->apps_reset); - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, IMX6SX_GPR12_PCIE_TEST_POWERDOWN); /* Force PCIe PHY reset */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, IMX6SX_GPR5_PCIE_BTNRST_RESET); break; case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, IMX6Q_GPR1_PCIE_SW_RST); break; case IMX6Q: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; default: @@ -721,47 +721,47 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) } /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx6_pcie->reset_gpio)) - gpio_set_value_cansleep(imx6_pcie->reset_gpio, - imx6_pcie->gpio_active_high); + if (gpio_is_valid(imx_pcie->reset_gpio)) + gpio_set_value_cansleep(imx_pcie->reset_gpio, + imx_pcie->gpio_active_high); } -static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) +static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; - reset_control_deassert(imx6_pcie->pciephy_reset); + reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX7D: /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. */ - if (likely(imx6_pcie->phy_base)) { + if (likely(imx_pcie->phy_base)) { /* De-assert DCC_FB_EN */ writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); + imx_pcie->phy_base + PCIE_PHY_CMN_REG4); /* Assert RX_EQS and RX_EQS_SEL */ writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); /* Assert ATT_MODE */ writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); + imx_pcie->phy_base + PCIE_PHY_CMN_REG26); } else { dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); } - imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); break; case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); break; case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, 0); usleep_range(200, 500); @@ -771,10 +771,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx6_pcie->reset_gpio)) { + if (gpio_is_valid(imx_pcie->reset_gpio)) { msleep(100); - gpio_set_value_cansleep(imx6_pcie->reset_gpio, - !imx6_pcie->gpio_active_high); + gpio_set_value_cansleep(imx_pcie->reset_gpio, + !imx_pcie->gpio_active_high); /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ msleep(100); } @@ -782,9 +782,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) return 0; } -static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) +static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; u32 tmp; unsigned int retries; @@ -801,33 +801,33 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) return -ETIMEDOUT; } -static void imx6_pcie_ltssm_enable(struct device *dev) +static void imx_pcie_ltssm_enable(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; if (drvdata->ltssm_mask) - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, drvdata->ltssm_mask); - reset_control_deassert(imx6_pcie->apps_reset); + reset_control_deassert(imx_pcie->apps_reset); } -static void imx6_pcie_ltssm_disable(struct device *dev) +static void imx_pcie_ltssm_disable(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; if (drvdata->ltssm_mask) - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 0); - reset_control_assert(imx6_pcie->apps_reset); + reset_control_assert(imx_pcie->apps_reset); } -static int imx6_pcie_start_link(struct dw_pcie *pci) +static int imx_pcie_start_link(struct dw_pcie *pci) { - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); struct device *dev = pci->dev; u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 tmp; @@ -846,7 +846,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dw_pcie_dbi_ro_wr_dis(pci); /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); + imx_pcie_ltssm_enable(dev); ret = dw_pcie_wait_for_link(pci); if (ret) @@ -869,8 +869,8 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); dw_pcie_dbi_ro_wr_dis(pci); - if (imx6_pcie->drvdata->flags & - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { + if (imx_pcie->drvdata->flags & + IMX_PCIE_FLAG_IMX_SPEED_CHANGE) { /* * On i.MX7, DIRECT_SPEED_CHANGE behaves differently * from i.MX6 family when no link speed transition @@ -880,7 +880,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * failure. */ - ret = imx6_pcie_wait_for_speed_change(imx6_pcie); + ret = imx_pcie_wait_for_speed_change(imx_pcie); if (ret) { dev_err(dev, "Failed to bring link up!\n"); goto err_reset_phy; @@ -895,37 +895,37 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dev_info(dev, "Link: Only Gen1 is enabled\n"); } - imx6_pcie->link_is_up = true; + imx_pcie->link_is_up = true; tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); return 0; err_reset_phy: - imx6_pcie->link_is_up = false; + imx_pcie->link_is_up = false; dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); - imx6_pcie_reset_phy(imx6_pcie); + imx_pcie_reset_phy(imx_pcie); return 0; } -static void imx6_pcie_stop_link(struct dw_pcie *pci) +static void imx_pcie_stop_link(struct dw_pcie *pci) { struct device *dev = pci->dev; /* Turn off PCIe LTSSM */ - imx6_pcie_ltssm_disable(dev); + imx_pcie_ltssm_disable(dev); } -static int imx6_pcie_host_init(struct dw_pcie_rp *pp) +static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct device *dev = pci->dev; - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); int ret; - if (imx6_pcie->vpcie) { - ret = regulator_enable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) { + ret = regulator_enable(imx_pcie->vpcie); if (ret) { dev_err(dev, "failed to enable vpcie regulator: %d\n", ret); @@ -933,83 +933,83 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) } } - imx6_pcie_assert_core_reset(imx6_pcie); + imx_pcie_assert_core_reset(imx_pcie); - if (imx6_pcie->drvdata->init_phy) - imx6_pcie->drvdata->init_phy(imx6_pcie); + if (imx_pcie->drvdata->init_phy) + imx_pcie->drvdata->init_phy(imx_pcie); - imx6_pcie_configure_type(imx6_pcie); + imx_pcie_configure_type(imx_pcie); - ret = imx6_pcie_clk_enable(imx6_pcie); + ret = imx_pcie_clk_enable(imx_pcie); if (ret) { dev_err(dev, "unable to enable pcie clocks: %d\n", ret); goto err_reg_disable; } - if (imx6_pcie->phy) { - ret = phy_init(imx6_pcie->phy); + if (imx_pcie->phy) { + ret = phy_init(imx_pcie->phy); if (ret) { dev_err(dev, "pcie PHY power up failed\n"); goto err_clk_disable; } } - if (imx6_pcie->phy) { - ret = phy_power_on(imx6_pcie->phy); + if (imx_pcie->phy) { + ret = phy_power_on(imx_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); goto err_phy_off; } } - ret = imx6_pcie_deassert_core_reset(imx6_pcie); + ret = imx_pcie_deassert_core_reset(imx_pcie); if (ret < 0) { dev_err(dev, "pcie deassert core reset failed: %d\n", ret); goto err_phy_off; } - imx6_setup_phy_mpll(imx6_pcie); + imx_setup_phy_mpll(imx_pcie); return 0; err_phy_off: - if (imx6_pcie->phy) - phy_exit(imx6_pcie->phy); + if (imx_pcie->phy) + phy_exit(imx_pcie->phy); err_clk_disable: - imx6_pcie_clk_disable(imx6_pcie); + imx_pcie_clk_disable(imx_pcie); err_reg_disable: - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) + regulator_disable(imx_pcie->vpcie); return ret; } -static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) +static void imx_pcie_host_exit(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); - if (imx6_pcie->phy) { - if (phy_power_off(imx6_pcie->phy)) + if (imx_pcie->phy) { + if (phy_power_off(imx_pcie->phy)) dev_err(pci->dev, "unable to power off PHY\n"); - phy_exit(imx6_pcie->phy); + phy_exit(imx_pcie->phy); } - imx6_pcie_clk_disable(imx6_pcie); + imx_pcie_clk_disable(imx_pcie); - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) + regulator_disable(imx_pcie->vpcie); } -static const struct dw_pcie_host_ops imx6_pcie_host_ops = { - .init = imx6_pcie_host_init, - .deinit = imx6_pcie_host_exit, +static const struct dw_pcie_host_ops imx_pcie_host_ops = { + .init = imx_pcie_host_init, + .deinit = imx_pcie_host_exit, }; static const struct dw_pcie_ops dw_pcie_ops = { - .start_link = imx6_pcie_start_link, - .stop_link = imx6_pcie_stop_link, + .start_link = imx_pcie_start_link, + .stop_link = imx_pcie_stop_link, }; -static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) +static void imx_pcie_ep_init(struct dw_pcie_ep *ep) { enum pci_barno bar; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -1018,7 +1018,7 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } -static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, +static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -1065,35 +1065,35 @@ static const struct pci_epc_features imx95_pcie_epc_features = { }; static const struct pci_epc_features* -imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) +imx_pcie_ep_get_features(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); - return imx6_pcie->drvdata->epc_features; + return imx_pcie->drvdata->epc_features; } static const struct dw_pcie_ep_ops pcie_ep_ops = { - .init = imx6_pcie_ep_init, - .raise_irq = imx6_pcie_ep_raise_irq, - .get_features = imx6_pcie_ep_get_features, + .init = imx_pcie_ep_init, + .raise_irq = imx_pcie_ep_raise_irq, + .get_features = imx_pcie_ep_get_features, }; -static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, +static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, struct platform_device *pdev) { int ret; unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct dw_pcie_rp *pp = &pci->pp; struct device *dev = pci->dev; - imx6_pcie_host_init(pp); + imx_pcie_host_init(pp); ep = &pci->ep; ep->ops = &pcie_ep_ops; - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX8MQ_EP: case IMX8MM_EP: case IMX8MP_EP: @@ -1115,10 +1115,10 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, if (device_property_match_string(dev, "reg-names", "dbi2") >= 0) pci->dbi_base2 = NULL; - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT)) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); - ep->page_size = imx6_pcie->drvdata->epc_features->align; + ep->page_size = imx_pcie->drvdata->epc_features->align; ret = dw_pcie_ep_init(ep); if (ret) { @@ -1136,30 +1136,30 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, dw_pcie_ep_init_notify(ep); /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); + imx_pcie_ltssm_enable(dev); return 0; } -static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) +static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) { - struct device *dev = imx6_pcie->pci->dev; + struct device *dev = imx_pcie->pci->dev; /* Some variants have a turnoff reset in DT */ - if (imx6_pcie->turnoff_reset) { - reset_control_assert(imx6_pcie->turnoff_reset); - reset_control_deassert(imx6_pcie->turnoff_reset); + if (imx_pcie->turnoff_reset) { + reset_control_assert(imx_pcie->turnoff_reset); + reset_control_deassert(imx_pcie->turnoff_reset); goto pm_turnoff_sleep; } /* Others poke directly at IOMUXC registers */ - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, IMX6SX_GPR12_PCIE_PM_TURN_OFF); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); break; default: @@ -1178,73 +1178,73 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) usleep_range(1000, 10000); } -static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) +static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) { u8 offset; u16 val; - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; if (pci_msi_enabled()) { offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); if (save) { val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); - imx6_pcie->msi_ctrl = val; + imx_pcie->msi_ctrl = val; } else { dw_pcie_dbi_ro_wr_en(pci); - val = imx6_pcie->msi_ctrl; + val = imx_pcie->msi_ctrl; dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); dw_pcie_dbi_ro_wr_dis(pci); } } } -static int imx6_pcie_suspend_noirq(struct device *dev) +static int imx_pcie_suspend_noirq(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; - imx6_pcie_msi_save_restore(imx6_pcie, true); - imx6_pcie_pm_turnoff(imx6_pcie); - imx6_pcie_stop_link(imx6_pcie->pci); - imx6_pcie_host_exit(pp); + imx_pcie_msi_save_restore(imx_pcie, true); + imx_pcie_pm_turnoff(imx_pcie); + imx_pcie_stop_link(imx_pcie->pci); + imx_pcie_host_exit(pp); return 0; } -static int imx6_pcie_resume_noirq(struct device *dev) +static int imx_pcie_resume_noirq(struct device *dev) { int ret; - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; - ret = imx6_pcie_host_init(pp); + ret = imx_pcie_host_init(pp); if (ret) return ret; - imx6_pcie_msi_save_restore(imx6_pcie, false); + imx_pcie_msi_save_restore(imx_pcie, false); dw_pcie_setup_rc(pp); - if (imx6_pcie->link_is_up) - imx6_pcie_start_link(imx6_pcie->pci); + if (imx_pcie->link_is_up) + imx_pcie_start_link(imx_pcie->pci); return 0; } -static const struct dev_pm_ops imx6_pcie_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, - imx6_pcie_resume_noirq) +static const struct dev_pm_ops imx_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq, + imx_pcie_resume_noirq) }; -static int imx6_pcie_probe(struct platform_device *pdev) +static int imx_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct dw_pcie *pci; - struct imx6_pcie *imx6_pcie; + struct imx_pcie *imx_pcie; struct device_node *np; struct resource *dbi_base; struct device_node *node = dev->of_node; @@ -1252,8 +1252,8 @@ static int imx6_pcie_probe(struct platform_device *pdev) u16 val; int i; - imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); - if (!imx6_pcie) + imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); + if (!imx_pcie) return -ENOMEM; pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); @@ -1262,10 +1262,10 @@ static int imx6_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; - pci->pp.ops = &imx6_pcie_host_ops; + pci->pp.ops = &imx_pcie_host_ops; - imx6_pcie->pci = pci; - imx6_pcie->drvdata = of_device_get_match_data(dev); + imx_pcie->pci = pci; + imx_pcie->drvdata = of_device_get_match_data(dev); /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); @@ -1277,9 +1277,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) dev_err(dev, "Unable to map PCIe PHY\n"); return ret; } - imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); - if (IS_ERR(imx6_pcie->phy_base)) - return PTR_ERR(imx6_pcie->phy_base); + imx_pcie->phy_base = devm_ioremap_resource(dev, &res); + if (IS_ERR(imx_pcie->phy_base)) + return PTR_ERR(imx_pcie->phy_base); } pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); @@ -1287,12 +1287,12 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(pci->dbi_base); /* Fetch GPIOs */ - imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); - imx6_pcie->gpio_active_high = of_property_read_bool(node, + imx_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); + imx_pcie->gpio_active_high = of_property_read_bool(node, "reset-gpio-active-high"); - if (gpio_is_valid(imx6_pcie->reset_gpio)) { - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, - imx6_pcie->gpio_active_high ? + if (gpio_is_valid(imx_pcie->reset_gpio)) { + ret = devm_gpio_request_one(dev, imx_pcie->reset_gpio, + imx_pcie->gpio_active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, "PCIe reset"); @@ -1300,70 +1300,70 @@ static int imx6_pcie_probe(struct platform_device *pdev) dev_err(dev, "unable to get reset gpio\n"); return ret; } - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { - return imx6_pcie->reset_gpio; + } else if (imx_pcie->reset_gpio == -EPROBE_DEFER) { + return imx_pcie->reset_gpio; } - if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) + if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS) return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) - imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) + imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i]; /* Fetch clocks */ - ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks); if (ret) return ret; - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) { - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(imx6_pcie->phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { + imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(imx_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->phy), "failed to get pcie phy\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) { + imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); + if (IS_ERR(imx_pcie->apps_reset)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset), "failed to get pcie apps reset control\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) { + imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset), "Failed to get PCIEPHY reset control\n"); } - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX8MQ: case IMX8MQ_EP: case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; + imx_pcie->controller_id = 1; break; default: break; } /* Grab turnoff reset */ - imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); - if (IS_ERR(imx6_pcie->turnoff_reset)) { + imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); + if (IS_ERR(imx_pcie->turnoff_reset)) { dev_err(dev, "Failed to get TURNOFF reset control\n"); - return PTR_ERR(imx6_pcie->turnoff_reset); + return PTR_ERR(imx_pcie->turnoff_reset); } - if (imx6_pcie->drvdata->gpr) { + if (imx_pcie->drvdata->gpr) { /* Grab GPR config register range */ - imx6_pcie->iomuxc_gpr = - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + imx_pcie->iomuxc_gpr = + syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr); + if (IS_ERR(imx_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), "unable to find iomuxc registers\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) { void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); if (IS_ERR(off)) @@ -1376,59 +1376,59 @@ static int imx6_pcie_probe(struct platform_device *pdev) .reg_stride = 4, }; - imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(imx_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), "unable to find iomuxc registers\n"); } /* Grab PCIe PHY Tx Settings */ if (of_property_read_u32(node, "fsl,tx-deemph-gen1", - &imx6_pcie->tx_deemph_gen1)) - imx6_pcie->tx_deemph_gen1 = 0; + &imx_pcie->tx_deemph_gen1)) + imx_pcie->tx_deemph_gen1 = 0; if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", - &imx6_pcie->tx_deemph_gen2_3p5db)) - imx6_pcie->tx_deemph_gen2_3p5db = 0; + &imx_pcie->tx_deemph_gen2_3p5db)) + imx_pcie->tx_deemph_gen2_3p5db = 0; if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", - &imx6_pcie->tx_deemph_gen2_6db)) - imx6_pcie->tx_deemph_gen2_6db = 20; + &imx_pcie->tx_deemph_gen2_6db)) + imx_pcie->tx_deemph_gen2_6db = 20; if (of_property_read_u32(node, "fsl,tx-swing-full", - &imx6_pcie->tx_swing_full)) - imx6_pcie->tx_swing_full = 127; + &imx_pcie->tx_swing_full)) + imx_pcie->tx_swing_full = 127; if (of_property_read_u32(node, "fsl,tx-swing-low", - &imx6_pcie->tx_swing_low)) - imx6_pcie->tx_swing_low = 127; + &imx_pcie->tx_swing_low)) + imx_pcie->tx_swing_low = 127; /* Limit link speed */ pci->link_gen = 1; of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); - imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); - if (IS_ERR(imx6_pcie->vpcie)) { - if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) - return PTR_ERR(imx6_pcie->vpcie); - imx6_pcie->vpcie = NULL; + imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); + if (IS_ERR(imx_pcie->vpcie)) { + if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) + return PTR_ERR(imx_pcie->vpcie); + imx_pcie->vpcie = NULL; } - imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); - if (IS_ERR(imx6_pcie->vph)) { - if (PTR_ERR(imx6_pcie->vph) != -ENODEV) - return PTR_ERR(imx6_pcie->vph); - imx6_pcie->vph = NULL; + imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); + if (IS_ERR(imx_pcie->vph)) { + if (PTR_ERR(imx_pcie->vph) != -ENODEV) + return PTR_ERR(imx_pcie->vph); + imx_pcie->vph = NULL; } - platform_set_drvdata(pdev, imx6_pcie); + platform_set_drvdata(pdev, imx_pcie); - ret = imx6_pcie_attach_pd(dev); + ret = imx_pcie_attach_pd(dev); if (ret) return ret; - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { - ret = imx6_add_pcie_ep(imx6_pcie, pdev); + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { + ret = imx_add_pcie_ep(imx_pcie, pdev); if (ret < 0) return ret; } else { @@ -1448,12 +1448,12 @@ static int imx6_pcie_probe(struct platform_device *pdev) return 0; } -static void imx6_pcie_shutdown(struct platform_device *pdev) +static void imx_pcie_shutdown(struct platform_device *pdev) { - struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); + struct imx_pcie *imx_pcie = platform_get_drvdata(pdev); /* bring down link, so bootloader gets clean state in case of reboot */ - imx6_pcie_assert_core_reset(imx6_pcie); + imx_pcie_assert_core_reset(imx_pcie); } static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; @@ -1461,11 +1461,11 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; -static const struct imx6_pcie_drvdata drvdata[] = { +static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { .variant = IMX6Q, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6q_clks, @@ -1474,13 +1474,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, - .init_phy = imx6_pcie_init_phy, + .init_phy = imx_pcie_init_phy, }, [IMX6SX] = { .variant = IMX6SX, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6sx_clks, .clks_cnt = ARRAY_SIZE(imx6sx_clks), @@ -1492,9 +1492,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX6QP] = { .variant = IMX6QP, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6q_clks, @@ -1503,13 +1503,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, - .init_phy = imx6_pcie_init_phy, + .init_phy = imx_pcie_init_phy, }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = imx6q_clks, .clks_cnt = ARRAY_SIZE(imx6q_clks), @@ -1519,8 +1519,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MQ] = { .variant = IMX8MQ, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), @@ -1532,9 +1532,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM] = { .variant = IMX8MM, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHYDRV | - IMX6_PCIE_FLAG_HAS_APP_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), @@ -1543,9 +1543,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP] = { .variant = IMX8MP, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHYDRV | - IMX6_PCIE_FLAG_HAS_APP_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), @@ -1554,7 +1554,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX95] = { .variant = IMX95, - .flags = IMX6_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3, @@ -1565,8 +1565,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, @@ -1580,8 +1580,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1592,8 +1592,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP_EP] = { .variant = IMX8MP_EP, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1604,8 +1604,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX95_EP] = { .variant = IMX95_EP, - .flags = IMX6_PCIE_FLAG_HAS_SERDES | - IMX6_PCIE_FLAG_SUPPORT_64BIT, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_SUPPORT_64BIT, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3, @@ -1618,7 +1618,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, }; -static const struct of_device_id imx6_pcie_of_match[] = { +static const struct of_device_id imx_pcie_of_match[] = { { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, @@ -1634,19 +1634,19 @@ static const struct of_device_id imx6_pcie_of_match[] = { {}, }; -static struct platform_driver imx6_pcie_driver = { +static struct platform_driver imx_pcie_driver = { .driver = { .name = "imx6q-pcie", - .of_match_table = imx6_pcie_of_match, + .of_match_table = imx_pcie_of_match, .suppress_bind_attrs = true, - .pm = &imx6_pcie_pm_ops, + .pm = &imx_pcie_pm_ops, .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, - .probe = imx6_pcie_probe, - .shutdown = imx6_pcie_shutdown, + .probe = imx_pcie_probe, + .shutdown = imx_pcie_shutdown, }; -static void imx6_pcie_quirk(struct pci_dev *dev) +static void imx_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; struct dw_pcie_rp *pp = bus->sysdata; @@ -1656,33 +1656,33 @@ static void imx6_pcie_quirk(struct pci_dev *dev) return; /* Make sure we only quirk devices associated with this driver */ - if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) + if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver) return; if (pci_is_root_bus(bus)) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); /* * Limit config length to avoid the kernel reading beyond * the register set and causing an abort on i.MX 6Quad */ - if (imx6_pcie->drvdata->dbi_length) { - dev->cfg_size = imx6_pcie->drvdata->dbi_length; + if (imx_pcie->drvdata->dbi_length) { + dev->cfg_size = imx_pcie->drvdata->dbi_length; dev_info(&dev->dev, "Limiting cfg_size to %d\n", dev->cfg_size); } } } DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, - PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); + PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk); -static int __init imx6_pcie_init(void) +static int __init imx_pcie_init(void) { #ifdef CONFIG_ARM struct device_node *np; - np = of_find_matching_node(NULL, imx6_pcie_of_match); + np = of_find_matching_node(NULL, imx_pcie_of_match); if (!np) return -ENODEV; of_node_put(np); @@ -1698,6 +1698,6 @@ static int __init imx6_pcie_init(void) "external abort on non-linefetch"); #endif - return platform_driver_register(&imx6_pcie_driver); + return platform_driver_register(&imx_pcie_driver); } -device_initcall(imx6_pcie_init); +device_initcall(imx_pcie_init); -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (2 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 03/10] PCI: imx6: Rename imx6_* with imx_* Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-30 16:04 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li ` (6 subsequent siblings) 10 siblings, 1 reply; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li Instead of using the switch case statement to enable/disable the reference clock handled by this driver itself, let's introduce a new callback set_ref_clk() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 112 ++++++++++++++++------------------ 1 file changed, 52 insertions(+), 60 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 47134e2dfecf2..ff9d0098294fa 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); }; struct imx_pcie { @@ -585,21 +586,19 @@ static int imx_pcie_attach_pd(struct device *dev) return 0; } -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - unsigned int offset; - int ret = 0; + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); - break; - case IMX6QP: - case IMX6Q: + return 0; +} + +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + if (enable) { /* power up core phy and enable ref clock */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); /* * the async reset input need ref clock to sync internally, * when the ref clock comes after reset, internal synced @@ -608,54 +607,34 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) */ usleep_range(10, 100); regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - break; - case IMX7D: - case IMX95: - case IMX95_EP: - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - offset = imx_pcie_grp_offset(imx_pcie); - /* - * Set the over ride low and enabled - * make sure that REF_CLK is turned on. - */ - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, - 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); - break; + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN); + } else { + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); } - return ret; + return 0; } -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - switch (imx_pcie->drvdata->variant) { - case IMX6QP: - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, - IMX6Q_GPR1_PCIE_TEST_PD); - break; - case IMX7D: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); - break; - default: - break; - } + int offset = imx_pcie_grp_offset(imx_pcie); + + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/ + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); + return 0; +} + +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + return 0; } static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) @@ -668,10 +647,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) if (ret) return ret; - ret = imx_pcie_enable_ref_clk(imx_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie ref clock\n"); - goto err_ref_clk; + if (imx_pcie->drvdata->set_ref_clk) { + ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true); + if (ret) { + dev_err(dev, "Failed to enable PCIe REFCLK\n"); + goto err_ref_clk; + } } /* allow the clocks to stabilize */ @@ -686,7 +667,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx_pcie_disable_ref_clk(imx_pcie); + if (imx_pcie->drvdata->set_ref_clk) + imx_pcie->drvdata->set_ref_clk(imx_pcie, false); clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } @@ -1475,6 +1457,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .set_ref_clk = imx6q_pcie_set_ref_clk, }, [IMX6SX] = { .variant = IMX6SX, @@ -1489,6 +1472,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, + .set_ref_clk = imx6sx_pcie_set_ref_clk, }, [IMX6QP] = { .variant = IMX6QP, @@ -1504,6 +1488,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .set_ref_clk = imx6q_pcie_set_ref_clk, }, [IMX7D] = { .variant = IMX7D, @@ -1516,6 +1501,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, + .set_ref_clk = imx7d_pcie_set_ref_clk, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1529,6 +1515,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .init_phy = imx8mq_pcie_init_phy, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MM] = { .variant = IMX8MM, @@ -1540,6 +1527,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MP] = { .variant = IMX8MP, @@ -1551,6 +1539,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX95] = { .variant = IMX95, @@ -1577,6 +1566,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, .init_phy = imx8mq_pcie_init_phy, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1589,6 +1579,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1601,6 +1592,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX95_EP] = { .variant = IMX95_EP, -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK 2024-06-17 20:16 ` [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li @ 2024-06-30 16:04 ` Manivannan Sadhasivam 0 siblings, 0 replies; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-06-30 16:04 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Mon, Jun 17, 2024 at 04:16:40PM -0400, Frank Li wrote: > Instead of using the switch case statement to enable/disable the reference > clock handled by this driver itself, let's introduce a new callback > set_ref_clk() and define it for platforms that require it. This simplifies Should this be called 'enable_ref_clk' since the callback is supposed to enable REFCLK? > the code. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 112 ++++++++++++++++------------------ > 1 file changed, 52 insertions(+), 60 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 47134e2dfecf2..ff9d0098294fa 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { > const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; > const struct pci_epc_features *epc_features; > int (*init_phy)(struct imx_pcie *pcie); > + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); > }; > > struct imx_pcie { > @@ -585,21 +586,19 @@ static int imx_pcie_attach_pd(struct device *dev) > return 0; > } > > -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - unsigned int offset; > - int ret = 0; > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, > + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > > - switch (imx_pcie->drvdata->variant) { > - case IMX6SX: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); > - break; > - case IMX6QP: > - case IMX6Q: > + return 0; > +} > + > +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + if (enable) { > /* power up core phy and enable ref clock */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); > /* > * the async reset input need ref clock to sync internally, > * when the ref clock comes after reset, internal synced > @@ -608,54 +607,34 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) > */ > usleep_range(10, 100); > regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); > - break; > - case IMX7D: > - case IMX95: > - case IMX95_EP: > - break; > - case IMX8MM: > - case IMX8MM_EP: > - case IMX8MQ: > - case IMX8MQ_EP: > - case IMX8MP: > - case IMX8MP_EP: > - offset = imx_pcie_grp_offset(imx_pcie); > - /* > - * Set the over ride low and enabled > - * make sure that REF_CLK is turned on. > - */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > - 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); > - break; > + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN); > + } else { > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); > } > > - return ret; > + return 0; > } > > -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - switch (imx_pcie->drvdata->variant) { > - case IMX6QP: > - case IMX6Q: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, > - IMX6Q_GPR1_PCIE_TEST_PD); > - break; > - case IMX7D: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > - break; > - default: > - break; > - } > + int offset = imx_pcie_grp_offset(imx_pcie); > + > + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/ This comment provides no useful info. So please remove it. > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); > + return 0; > +} > + > +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > + return 0; Previously imx6_pcie_enable_ref_clk() was bailing out for IMX7D. But now you are explicitly enabling it. What is the reason? - Mani -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (3 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-30 16:10 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 Frank Li ` (5 subsequent siblings) 10 siblings, 1 reply; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li Instead of using the switch case statement to assert/dassert the core reset handled by this driver itself, let's introduce a new callback core_reset() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 134 ++++++++++++++++++---------------- 1 file changed, 71 insertions(+), 63 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index ff9d0098294fa..6f68bee111029 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -104,6 +104,7 @@ struct imx_pcie_drvdata { const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); + int (*core_reset)(struct imx_pcie *pcie, bool assert); }; struct imx_pcie { @@ -672,35 +673,75 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + if (assert) + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); + + /* Force PCIe PHY reset */ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0); + return 0; +} + +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0); + if (!assert) + usleep_range(200, 500); + + return 0; +} + +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + if (!assert) + return 0; + + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); + + return 0; +} + +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + + if (assert) + return 0; + + /* + * Workaround for ERR010728, failure of PCI-e PLL VCO to + * oscillate, especially when cold. This turns off "Duty-cycle + * Corrector" and other mysterious undocumented things. + */ + + if (likely(imx_pcie->phy_base)) { + /* De-assert DCC_FB_EN */ + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); + /* Assert RX_EQS and RX_EQS_SEL */ + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); + /* Assert ATT_MODE */ + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); + } else { + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); + } + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); + return 0; +} + static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { reset_control_assert(imx_pcie->pciephy_reset); reset_control_assert(imx_pcie->apps_reset); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - /* Force PCIe PHY reset */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, - IMX6SX_GPR5_PCIE_BTNRST_RESET); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, - IMX6Q_GPR1_PCIE_SW_RST); - break; - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, true); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) @@ -710,47 +751,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx_pcie->pci; - struct device *dev = pci->dev; - reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx_pcie->drvdata->variant) { - case IMX7D: - /* Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. - */ - if (likely(imx_pcie->phy_base)) { - /* De-assert DCC_FB_EN */ - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx_pcie->phy_base + PCIE_PHY_CMN_REG4); - /* Assert RX_EQS and RX_EQS_SEL */ - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL - | PCIE_PHY_CMN_REG24_RX_EQ, - imx_pcie->phy_base + PCIE_PHY_CMN_REG24); - /* Assert ATT_MODE */ - writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx_pcie->phy_base + PCIE_PHY_CMN_REG26); - } else { - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); - } - - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); - break; - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, 0); - - usleep_range(200, 500); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, false); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) { @@ -1458,6 +1462,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6q_pcie_core_reset, }, [IMX6SX] = { .variant = IMX6SX, @@ -1473,6 +1478,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, .set_ref_clk = imx6sx_pcie_set_ref_clk, + .core_reset = imx6sx_pcie_core_reset, }, [IMX6QP] = { .variant = IMX6QP, @@ -1489,6 +1495,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6qp_pcie_core_reset, }, [IMX7D] = { .variant = IMX7D, @@ -1502,6 +1509,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, .set_ref_clk = imx7d_pcie_set_ref_clk, + .core_reset = imx7d_pcie_core_reset, }, [IMX8MQ] = { .variant = IMX8MQ, -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback 2024-06-17 20:16 ` [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li @ 2024-06-30 16:10 ` Manivannan Sadhasivam 0 siblings, 0 replies; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-06-30 16:10 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Mon, Jun 17, 2024 at 04:16:41PM -0400, Frank Li wrote: > Instead of using the switch case statement to assert/dassert the core reset > handled by this driver itself, let's introduce a new callback core_reset() > and define it for platforms that require it. This simplifies the code. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > drivers/pci/controller/dwc/pci-imx6.c | 134 ++++++++++++++++++---------------- > 1 file changed, 71 insertions(+), 63 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index ff9d0098294fa..6f68bee111029 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -104,6 +104,7 @@ struct imx_pcie_drvdata { > const struct pci_epc_features *epc_features; > int (*init_phy)(struct imx_pcie *pcie); > int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); > + int (*core_reset)(struct imx_pcie *pcie, bool assert); > }; > > struct imx_pcie { > @@ -672,35 +673,75 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) > clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); > } > > +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) > +{ > + if (assert) > + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > + > + /* Force PCIe PHY reset */ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, > + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0); > + return 0; > +} > + > +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) > +{ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, > + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0); > + if (!assert) > + usleep_range(200, 500); > + > + return 0; > +} > + > +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) > +{ > + if (!assert) > + return 0; > + > + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); > + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); > + > + return 0; > +} > + > +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) > +{ > + struct dw_pcie *pci = imx_pcie->pci; > + struct device *dev = pci->dev; > + > + if (assert) > + return 0; > + > + /* > + * Workaround for ERR010728, failure of PCI-e PLL VCO to > + * oscillate, especially when cold. This turns off "Duty-cycle > + * Corrector" and other mysterious undocumented things. > + */ > + > + if (likely(imx_pcie->phy_base)) { > + /* De-assert DCC_FB_EN */ > + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); > + /* Assert RX_EQS and RX_EQS_SEL */ > + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, > + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); > + /* Assert ATT_MODE */ > + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); > + } else { > + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); > + } > + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); > + return 0; > +} > + > static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) > { > reset_control_assert(imx_pcie->pciephy_reset); > reset_control_assert(imx_pcie->apps_reset); > > - switch (imx_pcie->drvdata->variant) { > - case IMX6SX: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > - /* Force PCIe PHY reset */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, > - IMX6SX_GPR5_PCIE_BTNRST_RESET, > - IMX6SX_GPR5_PCIE_BTNRST_RESET); > - break; > - case IMX6QP: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_SW_RST, > - IMX6Q_GPR1_PCIE_SW_RST); > - break; > - case IMX6Q: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); > - break; > - default: > - break; > - } > + if (imx_pcie->drvdata->core_reset) > + imx_pcie->drvdata->core_reset(imx_pcie, true); > > /* Some boards don't have PCIe reset GPIO. */ > if (gpio_is_valid(imx_pcie->reset_gpio)) > @@ -710,47 +751,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) > > static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) > { > - struct dw_pcie *pci = imx_pcie->pci; > - struct device *dev = pci->dev; > - > reset_control_deassert(imx_pcie->pciephy_reset); > > - switch (imx_pcie->drvdata->variant) { > - case IMX7D: > - /* Workaround for ERR010728, failure of PCI-e PLL VCO to > - * oscillate, especially when cold. This turns off "Duty-cycle > - * Corrector" and other mysterious undocumented things. > - */ > - if (likely(imx_pcie->phy_base)) { > - /* De-assert DCC_FB_EN */ > - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, > - imx_pcie->phy_base + PCIE_PHY_CMN_REG4); > - /* Assert RX_EQS and RX_EQS_SEL */ > - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL > - | PCIE_PHY_CMN_REG24_RX_EQ, > - imx_pcie->phy_base + PCIE_PHY_CMN_REG24); > - /* Assert ATT_MODE */ > - writel(PCIE_PHY_CMN_REG26_ATT_MODE, > - imx_pcie->phy_base + PCIE_PHY_CMN_REG26); > - } else { > - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); > - } > - > - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); > - break; > - case IMX6SX: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, > - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); > - break; > - case IMX6QP: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_SW_RST, 0); > - > - usleep_range(200, 500); > - break; > - default: > - break; > - } > + if (imx_pcie->drvdata->core_reset) > + imx_pcie->drvdata->core_reset(imx_pcie, false); > > /* Some boards don't have PCIe reset GPIO. */ > if (gpio_is_valid(imx_pcie->reset_gpio)) { > @@ -1458,6 +1462,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .init_phy = imx_pcie_init_phy, > .set_ref_clk = imx6q_pcie_set_ref_clk, > + .core_reset = imx6q_pcie_core_reset, > }, > [IMX6SX] = { > .variant = IMX6SX, > @@ -1473,6 +1478,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .init_phy = imx6sx_pcie_init_phy, > .set_ref_clk = imx6sx_pcie_set_ref_clk, > + .core_reset = imx6sx_pcie_core_reset, > }, > [IMX6QP] = { > .variant = IMX6QP, > @@ -1489,6 +1495,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .init_phy = imx_pcie_init_phy, > .set_ref_clk = imx6q_pcie_set_ref_clk, > + .core_reset = imx6qp_pcie_core_reset, > }, > [IMX7D] = { > .variant = IMX7D, > @@ -1502,6 +1509,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .init_phy = imx7d_pcie_init_phy, > .set_ref_clk = imx7d_pcie_set_ref_clk, > + .core_reset = imx7d_pcie_core_reset, > }, > [IMX8MQ] = { > .variant = IMX8MQ, > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (4 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-30 16:13 ` Manivannan Sadhasivam 2024-07-01 0:10 ` Fabio Estevam 2024-06-17 20:16 ` [PATCH v6 07/10] PCI: imx6: Consolidate redundant if-checks Frank Li ` (4 subsequent siblings) 10 siblings, 2 replies; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li Improve comment about workaround ERR010727 by using official errata document content. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 6f68bee111029..6e3ac3fc33745 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -715,9 +715,25 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) return 0; /* - * Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. + * Workaround for ERR010728 (IMX7DS_2N09P, Rev. 1.1, 4/2023): + * + * PCIe: PLL may fail to lock under corner conditions Initial VCO + * oscillation may fail under corner conditions such as cold + * temperature which will cause the PCIe PLL fail to lock in the + * initialization phase. + * + * The Duty-cycle Corrector calibration must be disabled. + * + * 1. De-assert the G_RST signal by clearing + * SRC_PCIEPHY_RCR[PCIEPHY_G_RST]. + * 2. De-assert DCC_FB_EN by writing data “0x29” to the register + * address 0x306d0014 (PCIE_PHY_CMN_REG4). + * 3. Assert RX_EQS, RX_EQ_SEL by writing data “0x48” to the register + * address 0x306d0090 (PCIE_PHY_CMN_REG24). + * 4. Assert ATT_MODE by writing data “0xbc” to the register + * address 0x306d0098 (PCIE_PHY_CMN_REG26). + * 5. De-assert the CMN_RST signal by clearing register bit + * SRC_PCIEPHY_RCR[PCIEPHY_BTN] */ if (likely(imx_pcie->phy_base)) { -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 2024-06-17 20:16 ` [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 Frank Li @ 2024-06-30 16:13 ` Manivannan Sadhasivam 2024-07-01 0:10 ` Fabio Estevam 1 sibling, 0 replies; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-06-30 16:13 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Mon, Jun 17, 2024 at 04:16:42PM -0400, Frank Li wrote: > Improve comment about workaround ERR010727 by using official errata > document content. > It is useful to provide a link to the errata document in the commit message. > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 6f68bee111029..6e3ac3fc33745 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -715,9 +715,25 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) > return 0; > > /* > - * Workaround for ERR010728, failure of PCI-e PLL VCO to > - * oscillate, especially when cold. This turns off "Duty-cycle > - * Corrector" and other mysterious undocumented things. > + * Workaround for ERR010728 (IMX7DS_2N09P, Rev. 1.1, 4/2023): > + * > + * PCIe: PLL may fail to lock under corner conditions Initial VCO Missing full stop after 'conditions'? - Mani -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 2024-06-17 20:16 ` [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 Frank Li 2024-06-30 16:13 ` Manivannan Sadhasivam @ 2024-07-01 0:10 ` Fabio Estevam 1 sibling, 0 replies; 24+ messages in thread From: Fabio Estevam @ 2024-07-01 0:10 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Mon, Jun 17, 2024 at 5:17 PM Frank Li <Frank.Li@nxp.com> wrote: > > Improve comment about workaround ERR010727 by using official errata This should be ERR010728, not ERR010727. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 07/10] PCI: imx6: Consolidate redundant if-checks 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (5 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-17 20:16 ` [PATCH v6 08/10] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li ` (3 subsequent siblings) 10 siblings, 0 replies; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li Consolidated redundant if-checks pertaining to imx_pcie->phy. Instead of two separate checks, merged them into one to improve code readability. if (imx_pcie->phy) { ... code 1 } if (imx_pcie->phy) { ... code 2 } Merge into one if block. if (imx_pcie->phy) { ... code 1 ... code 2 } Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 6e3ac3fc33745..ab0ed7ab3007a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -954,9 +954,7 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) dev_err(dev, "pcie PHY power up failed\n"); goto err_clk_disable; } - } - if (imx_pcie->phy) { ret = phy_power_on(imx_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 08/10] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (6 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 07/10] PCI: imx6: Consolidate redundant if-checks Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-17 20:16 ` [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li ` (2 subsequent siblings) 10 siblings, 0 replies; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li, Conor Dooley From: Richard Zhu <hongxing.zhu@nxp.com> Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. clock-names align dwc common naming convension. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 8b8d77b1154b5..1e05c560d7975 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -30,6 +30,7 @@ properties: - fsl,imx8mm-pcie - fsl,imx8mp-pcie - fsl,imx95-pcie + - fsl,imx8q-pcie clocks: minItems: 3 @@ -184,6 +185,21 @@ allOf: - const: pcie_bus - const: pcie_aux + - if: + properties: + compatible: + enum: + - fsl,imx8q-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + unevaluatedProperties: false examples: -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (7 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 08/10] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-30 16:23 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Frank Li 2024-06-25 14:47 ` [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li 10 siblings, 1 reply; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li Invoke the common PHY API to configure mode, speed, and submode. While these functions are optional in the PHY interface, they are necessary for certain PHY drivers. Lack of support for these functions in a PHY driver does not cause harm. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index ab0ed7ab3007a..18c133f5a56fc 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -30,6 +30,7 @@ #include <linux/interrupt.h> #include <linux/reset.h> #include <linux/phy/phy.h> +#include <linux/phy/pcie.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> @@ -229,6 +230,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) id = imx_pcie->controller_id; + /* If mode_mask[0] is 0, means use phy driver to set mode */ + if (!drvdata->mode_mask[0]) + return; + /* If mode_mask[id] is zero, means each controller have its individual gpr */ if (!drvdata->mode_mask[id]) id = 0; @@ -808,6 +813,7 @@ static void imx_pcie_ltssm_enable(struct device *dev) struct imx_pcie *imx_pcie = dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB); if (drvdata->ltssm_mask) regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, drvdata->ltssm_mask); @@ -820,6 +826,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) struct imx_pcie *imx_pcie = dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; + phy_set_speed(imx_pcie->phy, 0); if (drvdata->ltssm_mask) regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 0); @@ -955,6 +962,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) goto err_clk_disable; } + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) { + dev_err(dev, "unable to set pcie PHY mode\n"); + goto err_phy_off; + } + ret = phy_power_on(imx_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode 2024-06-17 20:16 ` [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li @ 2024-06-30 16:23 ` Manivannan Sadhasivam 2024-07-08 16:01 ` Frank Li 0 siblings, 1 reply; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-06-30 16:23 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Mon, Jun 17, 2024 at 04:16:45PM -0400, Frank Li wrote: You don't need the colon after 'Call' in subject. > Invoke the common PHY API to configure mode, speed, and submode. While > these functions are optional in the PHY interface, they are necessary for > certain PHY drivers. Lack of support for these functions in a PHY driver > does not cause harm. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index ab0ed7ab3007a..18c133f5a56fc 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -30,6 +30,7 @@ > #include <linux/interrupt.h> > #include <linux/reset.h> > #include <linux/phy/phy.h> > +#include <linux/phy/pcie.h> This should be moved one entry above. > #include <linux/pm_domain.h> > #include <linux/pm_runtime.h> > > @@ -229,6 +230,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) > > id = imx_pcie->controller_id; > > + /* If mode_mask[0] is 0, means use phy driver to set mode */ /* If mode_mask is 0, then generic PHY driver is used to set the mode */ > + if (!drvdata->mode_mask[0]) > + return; > + > /* If mode_mask[id] is zero, means each controller have its individual gpr */ > if (!drvdata->mode_mask[id]) > id = 0; > @@ -808,6 +813,7 @@ static void imx_pcie_ltssm_enable(struct device *dev) > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB); Is this setting really universal? This looks like applicable only to specific platforms supporting this link speed. > if (drvdata->ltssm_mask) > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, > drvdata->ltssm_mask); > @@ -820,6 +826,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > + phy_set_speed(imx_pcie->phy, 0); > if (drvdata->ltssm_mask) > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, > drvdata->ltssm_mask, 0); > @@ -955,6 +962,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > goto err_clk_disable; > } > > + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); > + if (ret) { > + dev_err(dev, "unable to set pcie PHY mode\n"); s/pcie/PCIe - Mani -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode 2024-06-30 16:23 ` Manivannan Sadhasivam @ 2024-07-08 16:01 ` Frank Li 0 siblings, 0 replies; 24+ messages in thread From: Frank Li @ 2024-07-08 16:01 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Sun, Jun 30, 2024 at 09:53:37PM +0530, Manivannan Sadhasivam wrote: > On Mon, Jun 17, 2024 at 04:16:45PM -0400, Frank Li wrote: > > You don't need the colon after 'Call' in subject. > > > Invoke the common PHY API to configure mode, speed, and submode. While > > these functions are optional in the PHY interface, they are necessary for > > certain PHY drivers. Lack of support for these functions in a PHY driver > > does not cause harm. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index ab0ed7ab3007a..18c133f5a56fc 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -30,6 +30,7 @@ > > #include <linux/interrupt.h> > > #include <linux/reset.h> > > #include <linux/phy/phy.h> > > +#include <linux/phy/pcie.h> > > This should be moved one entry above. > > > #include <linux/pm_domain.h> > > #include <linux/pm_runtime.h> > > > > @@ -229,6 +230,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) > > > > id = imx_pcie->controller_id; > > > > + /* If mode_mask[0] is 0, means use phy driver to set mode */ > > /* If mode_mask is 0, then generic PHY driver is used to set the mode */ > > > + if (!drvdata->mode_mask[0]) > > + return; > > + > > /* If mode_mask[id] is zero, means each controller have its individual gpr */ > > if (!drvdata->mode_mask[id]) > > id = 0; > > @@ -808,6 +813,7 @@ static void imx_pcie_ltssm_enable(struct device *dev) > > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > > > + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB); > > Is this setting really universal? This looks like applicable only to specific > platforms supporting this link speed. phy layer just ignore it if phy driver don't support set_speed, like other phy API. Check platform will make code complex and without benefit. But it should be better to set SPEED as the same as CAP register. > > > if (drvdata->ltssm_mask) > > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, > > drvdata->ltssm_mask); > > @@ -820,6 +826,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) > > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > > > + phy_set_speed(imx_pcie->phy, 0); > > if (drvdata->ltssm_mask) > > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, > > drvdata->ltssm_mask, 0); > > @@ -955,6 +962,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > > goto err_clk_disable; > > } > > > > + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); > > + if (ret) { > > + dev_err(dev, "unable to set pcie PHY mode\n"); > > s/pcie/PCIe > > - Mani > > -- > மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (8 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li @ 2024-06-17 20:16 ` Frank Li 2024-06-30 16:51 ` Manivannan Sadhasivam 2024-06-25 14:47 ` [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li 10 siblings, 1 reply; 24+ messages in thread From: Frank Li @ 2024-06-17 20:16 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Frank Li From: Richard Zhu <hongxing.zhu@nxp.com> Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While the controller resembles that of iMX8MP, the PHY differs significantly. Notably, there's a distinction between PCI bus addresses and CPU addresses. Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus address conversion according to "range" property. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 18c133f5a56fc..d2533d889d120 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -66,6 +66,7 @@ enum imx_pcie_variants { IMX8MQ, IMX8MM, IMX8MP, + IMX8Q, IMX95, IMX8MQ_EP, IMX8MM_EP, @@ -81,6 +82,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) #define imx_check_flag(pci, val) (pci->drvdata->flags & val) @@ -1012,6 +1014,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) +{ + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); + struct dw_pcie_rp *pp = &pcie->pp; + struct resource_entry *entry; + unsigned int offset; + + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) + return cpu_addr; + + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + offset = entry->offset; + + return (cpu_addr - offset); +} + static const struct dw_pcie_host_ops imx_pcie_host_ops = { .init = imx_pcie_host_init, .deinit = imx_pcie_host_exit, @@ -1020,6 +1038,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { static const struct dw_pcie_ops dw_pcie_ops = { .start_link = imx_pcie_start_link, .stop_link = imx_pcie_stop_link, + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, }; static void imx_pcie_ep_init(struct dw_pcie_ep *ep) @@ -1449,6 +1468,13 @@ static int imx_pcie_probe(struct platform_device *pdev) if (ret < 0) return ret; + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) { + if (!resource_list_first_type(&pci->pp.bridge->windows, IORESOURCE_MEM)) { + dw_pcie_host_deinit(&pci->pp); + return dev_err_probe(dev, -EINVAL, "DTS Miss PCI memory range"); + } + } + if (pci_msi_enabled()) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); @@ -1473,6 +1499,7 @@ static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; +static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"}; static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { @@ -1576,6 +1603,13 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .set_ref_clk = imx8mm_pcie_set_ref_clk, }, + [IMX8Q] = { + .variant = IMX8Q, + .flags = IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_CPU_ADDR_FIXUP, + .clk_names = imx8q_clks, + .clks_cnt = ARRAY_SIZE(imx8q_clks), + }, [IMX95] = { .variant = IMX95, .flags = IMX_PCIE_FLAG_HAS_SERDES, @@ -1653,6 +1687,7 @@ static const struct of_device_id imx_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, + { .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], }, { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, -- 2.34.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support 2024-06-17 20:16 ` [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Frank Li @ 2024-06-30 16:51 ` Manivannan Sadhasivam 2024-07-01 18:28 ` Frank Li 0 siblings, 1 reply; 24+ messages in thread From: Manivannan Sadhasivam @ 2024-06-30 16:51 UTC (permalink / raw) To: Frank Li Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Mon, Jun 17, 2024 at 04:16:46PM -0400, Frank Li wrote: > From: Richard Zhu <hongxing.zhu@nxp.com> > > Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While > the controller resembles that of iMX8MP, the PHY differs significantly. > Notably, there's a distinction between PCI bus addresses and CPU addresses. Do we know the reason? > > Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver > need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus > address conversion according to "range" property. 'ranges' > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 18c133f5a56fc..d2533d889d120 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -66,6 +66,7 @@ enum imx_pcie_variants { > IMX8MQ, > IMX8MM, > IMX8MP, > + IMX8Q, > IMX95, > IMX8MQ_EP, > IMX8MM_EP, > @@ -81,6 +82,7 @@ enum imx_pcie_variants { > #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) > #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) > #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) > +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) > > #define imx_check_flag(pci, val) (pci->drvdata->flags & val) > > @@ -1012,6 +1014,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) > regulator_disable(imx_pcie->vpcie); > } > > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > +{ > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); > + struct dw_pcie_rp *pp = &pcie->pp; > + struct resource_entry *entry; > + unsigned int offset; > + > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) > + return cpu_addr; > + > + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); > + offset = entry->offset; > + > + return (cpu_addr - offset); > +} > + > static const struct dw_pcie_host_ops imx_pcie_host_ops = { > .init = imx_pcie_host_init, > .deinit = imx_pcie_host_exit, > @@ -1020,6 +1038,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { > static const struct dw_pcie_ops dw_pcie_ops = { > .start_link = imx_pcie_start_link, > .stop_link = imx_pcie_stop_link, > + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, > }; > > static void imx_pcie_ep_init(struct dw_pcie_ep *ep) > @@ -1449,6 +1468,13 @@ static int imx_pcie_probe(struct platform_device *pdev) > if (ret < 0) > return ret; > > + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) { > + if (!resource_list_first_type(&pci->pp.bridge->windows, IORESOURCE_MEM)) { > + dw_pcie_host_deinit(&pci->pp); > + return dev_err_probe(dev, -EINVAL, "DTS Miss PCI memory range"); -ENODEV - Mani -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support 2024-06-30 16:51 ` Manivannan Sadhasivam @ 2024-07-01 18:28 ` Frank Li 0 siblings, 0 replies; 24+ messages in thread From: Frank Li @ 2024-07-01 18:28 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley, linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree On Sun, Jun 30, 2024 at 10:21:03PM +0530, Manivannan Sadhasivam wrote: > On Mon, Jun 17, 2024 at 04:16:46PM -0400, Frank Li wrote: > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While > > the controller resembles that of iMX8MP, the PHY differs significantly. > > Notably, there's a distinction between PCI bus addresses and CPU addresses. > > Do we know the reason? It is IC hardware design. Some high bits of address was changed in HSIO subsystem. Frank > > > > > Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver > > need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus > > address conversion according to "range" property. > > 'ranges' > > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++++++++++ > > 1 file changed, 35 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index 18c133f5a56fc..d2533d889d120 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -66,6 +66,7 @@ enum imx_pcie_variants { > > IMX8MQ, > > IMX8MM, > > IMX8MP, > > + IMX8Q, > > IMX95, > > IMX8MQ_EP, > > IMX8MM_EP, > > @@ -81,6 +82,7 @@ enum imx_pcie_variants { > > #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) > > #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) > > #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) > > > > #define imx_check_flag(pci, val) (pci->drvdata->flags & val) > > > > @@ -1012,6 +1014,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) > > regulator_disable(imx_pcie->vpcie); > > } > > > > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > > +{ > > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); > > + struct dw_pcie_rp *pp = &pcie->pp; > > + struct resource_entry *entry; > > + unsigned int offset; > > + > > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) > > + return cpu_addr; > > + > > + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); > > + offset = entry->offset; > > + > > + return (cpu_addr - offset); > > +} > > + > > static const struct dw_pcie_host_ops imx_pcie_host_ops = { > > .init = imx_pcie_host_init, > > .deinit = imx_pcie_host_exit, > > @@ -1020,6 +1038,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { > > static const struct dw_pcie_ops dw_pcie_ops = { > > .start_link = imx_pcie_start_link, > > .stop_link = imx_pcie_stop_link, > > + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, > > }; > > > > static void imx_pcie_ep_init(struct dw_pcie_ep *ep) > > @@ -1449,6 +1468,13 @@ static int imx_pcie_probe(struct platform_device *pdev) > > if (ret < 0) > > return ret; > > > > + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) { > > + if (!resource_list_first_type(&pci->pp.bridge->windows, IORESOURCE_MEM)) { > > + dw_pcie_host_deinit(&pci->pp); > > + return dev_err_probe(dev, -EINVAL, "DTS Miss PCI memory range"); > > -ENODEV > > - Mani > > -- > மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li ` (9 preceding siblings ...) 2024-06-17 20:16 ` [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Frank Li @ 2024-06-25 14:47 ` Frank Li 10 siblings, 0 replies; 24+ messages in thread From: Frank Li @ 2024-06-25 14:47 UTC (permalink / raw) To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown, Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree, Jason Liu, Conor Dooley On Mon, Jun 17, 2024 at 04:16:36PM -0400, Frank Li wrote: > Fixed 8mp EP mode problem. > > imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid > confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to > pci-imx.c to avoid confuse. > > Using callback to reduce switch case for core reset and refclk. > > Add iMX8QXP and iMX8QM support. PHY driver ref: > https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git/commit/?h=next&id=82c56b6dd24fcdf811f2b47b72e5585c8a79b685 > > Base on linux 6.10-rc1 Krzysztof Wilczyński and mani: Do you have chance to check these patch? I removed imx95 Lut patch, which need more time to discussion. At least first 2 fix patch is important, which fix some function issue. Frank Li > > To: Richard Zhu <hongxing.zhu@nxp.com> > To: Lucas Stach <l.stach@pengutronix.de> > To: Lorenzo Pieralisi <lpieralisi@kernel.org> > To: Krzysztof Wilczyński <kw@linux.com> > To: Rob Herring <robh@kernel.org> > To: Bjorn Helgaas <bhelgaas@google.com> > To: Shawn Guo <shawnguo@kernel.org> > To: Sascha Hauer <s.hauer@pengutronix.de> > To: Pengutronix Kernel Team <kernel@pengutronix.de> > To: Fabio Estevam <festevam@gmail.com> > To: NXP Linux Team <linux-imx@nxp.com> > To: Philipp Zabel <p.zabel@pengutronix.de> > To: Liam Girdwood <lgirdwood@gmail.com> > To: Mark Brown <broonie@kernel.org> > To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > To: Conor Dooley <conor+dt@kernel.org> > Cc: linux-pci@vger.kernel.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: bpf@vger.kernel.org > Cc: devicetree@vger.kernel.org > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > Changes in v6: > - Base on Linux 6.10-rc1 by Bjorn's required. > - Remove imx95 LUT patch because it need more time to work out the > solution. This patch add 8qxp and 8qm and support and some bug fixes. > - Link to v5: https://lore.kernel.org/r/20240528-pci2_upstream-v5-0-750aa7edb8e2@nxp.com > > Changes in v5: > - Rebase to linux-pci next. fix conflict with gpiod change > - Add rob and cornor's review tag > - Link to v4: https://lore.kernel.org/r/20240507-pci2_upstream-v4-0-e8c80d874057@nxp.com > > Changes in v4: > - Improve comment message for patch 1 and 2. > - Rework commit message for patch 3 and add mani's review tag > - Remove file rename patch and update maintainer patch > - [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback > remove extra space. > keep original comments format (wrap at 80 column width) > update error message "'Failed to enable PCIe REFCLK'" > - PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback > keep exact the logic as original code > - Add patch to update comment about workaround ERR010728 > - Add patch about help function imx_pcie_match_device() > - Using bus device notify to update LUT information for imx95 to avoid > parse iommu-map and msi-map in driver code. Bus notify will better and > only update lut when device added. > - split patch call PHY interface function. > - Improve commit message for imx8q. remove local-address dts proptery. and > use standard "range" to convert cpu address to bus address. > - Check entry in cpu_fix function is too late. Check it at probe > - Link to v3: https://lore.kernel.org/r/20240402-pci2_upstream-v3-0-803414bdb430@nxp.com > > Changes in v3: > - Add an EP fixed patch > PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode > PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI > - Add 8qxp rc support > dt-bing yaml pass binding check > make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml > LINT Documentation/devicetree/bindings > DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts > CHKDT Documentation/devicetree/bindings/processed-schema.json > SCHEMA Documentation/devicetree/bindings/processed-schema.json > DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb > > - Link to v2: https://lore.kernel.org/r/20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com > > Changes in v2: > - remove file to 'pcie-imx.c' > - keep CONFIG unchange. > - Link to v1: https://lore.kernel.org/r/20240227-pci2_upstream-v1-0-b952f8333606@nxp.com > > --- > Frank Li (6): > PCI: imx6: Rename imx6_* with imx_* > PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK > PCI: imx6: Simplify switch-case logic by involve core_reset callback > PCI: imx6: Improve comment for workaround ERR010728 > PCI: imx6: Consolidate redundant if-checks > PCI: imx6: Call: Common PHY API to set mode, speed, and submode > > Richard Zhu (4): > PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP > PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI > dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string > PCI: imx6: Add i.MX8Q PCIe root complex (RC) support > > .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 + > drivers/pci/controller/dwc/pci-imx6.c | 1004 +++++++++++--------- > 2 files changed, 551 insertions(+), 469 deletions(-) > --- > base-commit: d9b6deec8e0a49b3ade6559b68c6a77ded0f4a8d > change-id: 20240227-pci2_upstream-0cdd19a15163 > > Best regards, > --- > Frank Li <Frank.Li@nxp.com> > ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2024-07-08 16:02 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li 2024-06-17 20:16 ` [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li 2024-06-29 12:23 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Frank Li 2024-06-29 13:05 ` Manivannan Sadhasivam 2024-07-01 18:32 ` Frank Li 2024-07-06 17:39 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 03/10] PCI: imx6: Rename imx6_* with imx_* Frank Li 2024-06-17 20:16 ` [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li 2024-06-30 16:04 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li 2024-06-30 16:10 ` Manivannan Sadhasivam 2024-06-17 20:16 ` [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 Frank Li 2024-06-30 16:13 ` Manivannan Sadhasivam 2024-07-01 0:10 ` Fabio Estevam 2024-06-17 20:16 ` [PATCH v6 07/10] PCI: imx6: Consolidate redundant if-checks Frank Li 2024-06-17 20:16 ` [PATCH v6 08/10] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li 2024-06-17 20:16 ` [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li 2024-06-30 16:23 ` Manivannan Sadhasivam 2024-07-08 16:01 ` Frank Li 2024-06-17 20:16 ` [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Frank Li 2024-06-30 16:51 ` Manivannan Sadhasivam 2024-07-01 18:28 ` Frank Li 2024-06-25 14:47 ` [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
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