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From: Alexey Charkov <alchark@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
	 Dragan Simic <dsimic@manjaro.org>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	 Chen-Yu Tsai <wens@kernel.org>,
	Diederik de Haas <didi.debian@cknow.org>,
	 devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	 linux-rockchip@lists.infradead.org,
	linux-kernel@vger.kernel.org,  Alexey Charkov <alchark@gmail.com>
Subject: [PATCH v5 1/8] arm64: dts: rockchip: add thermal zones information on RK3588
Date: Mon, 17 Jun 2024 22:28:51 +0400	[thread overview]
Message-ID: <20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com> (raw)
In-Reply-To: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com>

This includes the necessary device tree data to allow thermal
monitoring on RK3588(s) using the on-chip TSADC device, along with
trip points for automatic thermal management.

Each of the CPU clusters (one for the little cores and two for
the big cores) get a passive cooling trip point at 85C, which
will trigger DVFS throttling of the respective cluster upon
reaching a high temperature condition.

All zones also have a critical trip point at 115C, which will
trigger a reset.

Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 147 ++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 629049f3dc16..574359279867 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/ata/ahci.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	compatible = "rockchip,rk3588";
@@ -2368,6 +2369,152 @@ pwm15: pwm@febf0030 {
 		status = "disabled";
 	};
 
+	thermal_zones: thermal-zones {
+		/* sensor near the center of the SoC */
+		package_thermal: package-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsadc 0>;
+
+			trips {
+				package_crit: package-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		/* sensor between A76 cores 0 and 1 */
+		bigcore0_thermal: bigcore0-thermal {
+			polling-delay-passive = <100>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsadc 1>;
+
+			trips {
+				bigcore0_alert: bigcore0-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				bigcore0_crit: bigcore0-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&bigcore0_alert>;
+					cooling-device =
+						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		/* sensor between A76 cores 2 and 3 */
+		bigcore2_thermal: bigcore2-thermal {
+			polling-delay-passive = <100>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsadc 2>;
+
+			trips {
+				bigcore2_alert: bigcore2-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				bigcore2_crit: bigcore2-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&bigcore2_alert>;
+					cooling-device =
+						<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		/* sensor between the four A55 cores */
+		little_core_thermal: littlecore-thermal {
+			polling-delay-passive = <100>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsadc 3>;
+
+			trips {
+				littlecore_alert: littlecore-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				littlecore_crit: littlecore-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&littlecore_alert>;
+					cooling-device =
+						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		/* sensor near the PD_CENTER power domain */
+		center_thermal: center-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsadc 4>;
+
+			trips {
+				center_crit: center-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpu_thermal: gpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsadc 5>;
+
+			trips {
+				gpu_crit: gpu-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		npu_thermal: npu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsadc 6>;
+
+			trips {
+				npu_crit: npu-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	tsadc: tsadc@fec00000 {
 		compatible = "rockchip,rk3588-tsadc";
 		reg = <0x0 0xfec00000 0x0 0x400>;

-- 
2.45.2


  reply	other threads:[~2024-06-17 18:29 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-17 18:28 [PATCH v5 0/8] RK3588 and Rock 5B dts additions: thermal, OPP and fan Alexey Charkov
2024-06-17 18:28 ` Alexey Charkov [this message]
2024-06-17 18:28 ` [PATCH v5 2/8] arm64: dts: rockchip: enable thermal management on all RK3588 boards Alexey Charkov
2024-06-17 18:28 ` [PATCH v5 3/8] arm64: dts: rockchip: add passive GPU cooling on RK3588 Alexey Charkov
2024-06-17 18:28 ` [PATCH v5 4/8] arm64: dts: rockchip: enable automatic fan control on Rock 5B Alexey Charkov
2024-06-17 18:28 ` [PATCH v5 5/8] arm64: dts: rockchip: Add CPU/memory regulator coupling for RK3588 Alexey Charkov
2024-06-17 18:28 ` [PATCH v5 6/8] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 Alexey Charkov
2024-06-17 18:28 ` [PATCH v5 7/8] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j Alexey Charkov
2025-02-11 16:32   ` Quentin Schulz
2025-02-15 18:59     ` Alexey Charkov
2025-02-15 20:30       ` Heiko Stübner
2025-02-15 21:26         ` Dragan Simic
2025-02-16 12:32         ` Alexey Charkov
2025-02-17 16:24           ` Quentin Schulz
2025-03-12 10:15           ` Quentin Schulz
2025-03-12 10:34             ` Dragan Simic
2025-03-13 10:42               ` Dragan Simic
2025-03-13 19:00                 ` Heiko Stuebner
2025-03-13 19:43                   ` Dragan Simic
2025-03-21  3:37                     ` Dragan Simic
2024-06-17 18:28 ` [PATCH v5 8/8] arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j Alexey Charkov
2025-02-11 16:34   ` Quentin Schulz
2024-06-17 18:56 ` [PATCH v5 0/8] RK3588 and Rock 5B dts additions: thermal, OPP and fan Dragan Simic
2024-06-20 20:39 ` (subset) " Heiko Stuebner
2024-06-21  6:15   ` Alexey Charkov
2024-06-24 16:20 ` Heiko Stuebner
2024-07-07  9:39 ` Piotr Oniszczuk
2024-07-07 11:11   ` Heiko Stübner
2024-07-07 12:37     ` Piotr Oniszczuk
2024-07-07 18:32       ` Piotr Oniszczuk
2024-07-08  7:59         ` Alexey Charkov
2024-07-08 10:29           ` Piotr Oniszczuk

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