From: Sam Protsenko <semen.protsenko@linaro.org>
To: "Łukasz Stelmach" <l.stelmach@samsung.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>
Cc: Olivia Mackall <olivia@selenic.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
Alim Akhtar <alim.akhtar@samsung.com>,
linux-samsung-soc@vger.kernel.org, linux-crypto@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 4/7] hwrng: exynos: Implement bus clock control
Date: Mon, 17 Jun 2024 19:37:40 -0500 [thread overview]
Message-ID: <20240618003743.2975-5-semen.protsenko@linaro.org> (raw)
In-Reply-To: <20240618003743.2975-1-semen.protsenko@linaro.org>
Some SoCs like Exynos850 might require the SSS bus clock (PCLK) to be
enabled in order to access TRNG registers. Add and handle optional PCLK
clock accordingly to make it possible.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
drivers/char/hw_random/exynos-trng.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c
index 88a5088ed34d..4520a280134c 100644
--- a/drivers/char/hw_random/exynos-trng.c
+++ b/drivers/char/hw_random/exynos-trng.c
@@ -47,7 +47,8 @@
struct exynos_trng_dev {
struct device *dev;
void __iomem *mem;
- struct clk *clk;
+ struct clk *clk; /* operating clock */
+ struct clk *pclk; /* bus clock */
struct hwrng rng;
};
@@ -141,10 +142,23 @@ static int exynos_trng_probe(struct platform_device *pdev)
goto err_clock;
}
+ trng->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
+ if (IS_ERR(trng->pclk)) {
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(trng->pclk),
+ "cannot get pclk");
+ goto err_clock;
+ }
+
+ ret = clk_prepare_enable(trng->pclk);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not enable the pclk.\n");
+ goto err_clock;
+ }
+
ret = clk_prepare_enable(trng->clk);
if (ret) {
dev_err(&pdev->dev, "Could not enable the clk.\n");
- goto err_clock;
+ goto err_clock_enable;
}
ret = devm_hwrng_register(&pdev->dev, &trng->rng);
@@ -160,6 +174,9 @@ static int exynos_trng_probe(struct platform_device *pdev)
err_register:
clk_disable_unprepare(trng->clk);
+err_clock_enable:
+ clk_disable_unprepare(trng->pclk);
+
err_clock:
pm_runtime_put_noidle(&pdev->dev);
@@ -174,6 +191,7 @@ static void exynos_trng_remove(struct platform_device *pdev)
struct exynos_trng_dev *trng = platform_get_drvdata(pdev);
clk_disable_unprepare(trng->clk);
+ clk_disable_unprepare(trng->pclk);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
--
2.39.2
next prev parent reply other threads:[~2024-06-18 0:37 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-18 0:37 [PATCH 0/7] hwrng: exynos: Add support for Exynos850 Sam Protsenko
2024-06-18 0:37 ` [PATCH 1/7] dt-bindings: rng: Rename exynos5250-trng to exynos-trng Sam Protsenko
2024-06-18 6:32 ` Krzysztof Kozlowski
2024-06-18 0:37 ` [PATCH 2/7] dt-bindings: rng: Add Exynos850 support " Sam Protsenko
2024-06-18 6:33 ` Krzysztof Kozlowski
2024-06-18 0:37 ` [PATCH 3/7] hwrng: exynos: Improve coding style Sam Protsenko
2024-06-18 6:34 ` Krzysztof Kozlowski
2024-06-18 0:37 ` Sam Protsenko [this message]
2024-06-18 4:26 ` [PATCH 4/7] hwrng: exynos: Implement bus clock control Anand Moon
2024-06-18 19:26 ` Sam Protsenko
2024-06-18 0:37 ` [PATCH 5/7] hwrng: exynos: Add SMC based TRNG operation Sam Protsenko
2024-06-18 6:37 ` Krzysztof Kozlowski
2024-06-18 0:37 ` [PATCH 6/7] hwrng: exynos: Enable Exynos850 support Sam Protsenko
2024-06-18 6:39 ` Krzysztof Kozlowski
2024-06-18 20:25 ` Sam Protsenko
2024-06-18 0:37 ` [PATCH 7/7] arm64: dts: exynos850: Enable TRNG Sam Protsenko
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