From: Conor Dooley <conor.dooley@microchip.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
Conor Dooley <conor@kernel.org>,
Yong-Xuan Wang <yongxuan.wang@sifive.com>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<alex@ghiti.fr>, <greentime.hu@sifive.com>,
<vincent.chen@sifive.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
Date: Fri, 21 Jun 2024 11:11:56 +0100 [thread overview]
Message-ID: <20240621-flanking-twiddling-c3b6c9108438@wendy> (raw)
In-Reply-To: <20240621-10d503a9a2e7d54e67db102c@orel>
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On Fri, Jun 21, 2024 at 10:33:03AM +0200, Andrew Jones wrote:
> On Thu, Jun 20, 2024 at 11:55:44AM GMT, Anup Patel wrote:
> > On Wed, Jun 5, 2024 at 10:25 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Wed, Jun 05, 2024 at 08:15:08PM +0800, Yong-Xuan Wang wrote:
> > > > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
> > > > property.
> > > >
> > > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> > > > ---
> > > > .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++++++++++
> > > > 1 file changed, 30 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > index 468c646247aa..1e30988826b9 100644
> > > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > @@ -153,6 +153,36 @@ properties:
> > > > ratified at commit 3f9ed34 ("Add ability to manually trigger
> > > > workflow. (#2)") of riscv-time-compare.
> > > >
> > > > + - const: svade
> > > > + description: |
> > > > + The standard Svade supervisor-level extension for raising page-fault
> > > > + exceptions when PTE A/D bits need be set as ratified in the 20240213
> > > > + version of the privileged ISA specification.
> > > > +
> > > > + Both Svade and Svadu extensions control the hardware behavior when
> > > > + the PTE A/D bits need to be set. The default behavior for the four
> > > > + possible combinations of these extensions in the device tree are:
> > > > + 1. Neither svade nor svadu in DT: default to svade.
> > >
> > > I think this needs to be expanded on, as to why nothing means svade.
> >
> > Actually if both Svade and Svadu are not present in DT then
> > it is left to the platform and OpenSBI does nothing.
>
> This is a good point, and maybe it's worth integrating something that
> states this case is technically unknown into the final text. (Even though
> historically this has been assumed to mean svade.)
If that is assumed to mean svade at the moment, then that's what it has
to mean going forwards also.
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next prev parent reply other threads:[~2024-06-21 10:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240605121512.32083-1-yongxuan.wang@sifive.com>
2024-06-05 12:15 ` [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Yong-Xuan Wang
2024-06-05 16:54 ` Conor Dooley
2024-06-18 10:38 ` Yong-Xuan Wang
2024-06-19 18:11 ` Conor Dooley
2024-06-20 6:25 ` Anup Patel
2024-06-21 8:33 ` Andrew Jones
2024-06-21 10:11 ` Conor Dooley [this message]
2024-06-25 10:15 ` Yong-Xuan Wang
2024-06-21 8:37 ` Alexandre Ghiti
2024-06-21 10:17 ` Conor Dooley
2024-06-21 12:42 ` Alexandre Ghiti
2024-06-21 13:15 ` Andrew Jones
2024-06-21 14:04 ` Conor Dooley
2024-06-21 14:52 ` Andrew Jones
2024-06-21 14:58 ` Conor Dooley
2024-06-21 15:08 ` Andrew Jones
2024-06-22 12:01 ` Conor Dooley
2024-06-25 10:17 ` Yong-Xuan Wang
2024-06-25 10:19 ` Andrew Jones
2024-06-21 7:56 ` Alexandre Ghiti
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