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From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Alexandre Ghiti <alex@ghiti.fr>,
	Conor Dooley <conor.dooley@microchip.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Yong-Xuan Wang <yongxuan.wang@sifive.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	greentime.hu@sifive.com, vincent.chen@sifive.com,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
Date: Fri, 21 Jun 2024 15:58:18 +0100	[thread overview]
Message-ID: <20240621-surging-flounder-58a653747e1d@spud> (raw)
In-Reply-To: <20240621-a56e848050ebbf1f7394e51f@orel>

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On Fri, Jun 21, 2024 at 04:52:09PM +0200, Andrew Jones wrote:
> On Fri, Jun 21, 2024 at 03:04:47PM GMT, Conor Dooley wrote:
> > On Fri, Jun 21, 2024 at 03:15:10PM +0200, Andrew Jones wrote:
> > > On Fri, Jun 21, 2024 at 02:42:15PM GMT, Alexandre Ghiti wrote:

> > > I understand the concern; old SBI implementations will leave svadu in the
> > > DT but not actually enable it. Then, since svade may not be in the DT if
> > > the platform doesn't support it or it was left out on purpose, Linux will
> > > only see svadu and get unexpected exceptions. This is something we could
> > > force easily with QEMU and an SBI implementation which doesn't do anything
> > > for svadu. I hope vendors of real platforms, which typically provide their
> > > own firmware and DTs, would get this right, though, especially since Linux
> > > should fail fast in their testing when they get it wrong.
> > 
> > I'll admit, I wasn't really thinking here about something like QEMU that
> > puts extensions into the dtb before their exact meanings are decided
> > upon. I almost only ever think about "real" systems, and in those cases
> > I would expect that if you can update the representation of the hardware
> > provided to (or by the firmware to Linux) with new properties, then updating
> > the firmware itself should be possible.
> > 
> > Does QEMU have the this exact problem at the moment? I know it puts
> > Svadu in the max cpu, but does it enable the behaviour by default, even
> > without the SBI implementation asking for it?
> 
> Yes, because QEMU has done hardware A/D updating since it first started
> supporting riscv, which means it did svadu when neither svadu nor svade
> were in the DT. The "fix" for that was to ensure we have svadu and !svade
> by default, which means we've perfectly realized Alexandre's concern...
> We should be able to change the named cpu types that don't support svadu
> to only have svade in their DTs, since that would actually be fixing those
> cpu types, but we'll need to discuss how to proceed with the generic cpu
> types like 'max'.

Correct me please, since I think I am misunderstanding: At the moment
QEMU does A/D updating whether or not the SBI implantation asks for it,
with the max CPU. The SBI implementation doesn't understand Svadu and
won't strip it. The kernel will get a DT with Svadu in it, but Svadu will
be enabled, so it is not a problem.

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  reply	other threads:[~2024-06-21 14:58 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20240605121512.32083-1-yongxuan.wang@sifive.com>
2024-06-05 12:15 ` [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Yong-Xuan Wang
2024-06-05 16:54   ` Conor Dooley
2024-06-18 10:38     ` Yong-Xuan Wang
2024-06-19 18:11       ` Conor Dooley
2024-06-20  6:25     ` Anup Patel
2024-06-21  8:33       ` Andrew Jones
2024-06-21 10:11         ` Conor Dooley
2024-06-25 10:15         ` Yong-Xuan Wang
2024-06-21  8:37       ` Alexandre Ghiti
2024-06-21 10:17         ` Conor Dooley
2024-06-21 12:42           ` Alexandre Ghiti
2024-06-21 13:15             ` Andrew Jones
2024-06-21 14:04               ` Conor Dooley
2024-06-21 14:52                 ` Andrew Jones
2024-06-21 14:58                   ` Conor Dooley [this message]
2024-06-21 15:08                     ` Andrew Jones
2024-06-22 12:01                       ` Conor Dooley
2024-06-25 10:17                         ` Yong-Xuan Wang
2024-06-25 10:19                         ` Andrew Jones
2024-06-21  7:56   ` Alexandre Ghiti

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