From: Conor Dooley <conor@kernel.org>
To: Minda Chen <minda.chen@starfivetech.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v2 1/1] riscv: dts: starfive: add PCIe dts configuration for JH7110
Date: Mon, 24 Jun 2024 17:32:32 +0100 [thread overview]
Message-ID: <20240624-abdominal-friction-7de13b1e2c72@spud> (raw)
In-Reply-To: <SHXPR01MB0863A47890F95A45559FD82DE6D42@SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn>
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On Mon, Jun 24, 2024 at 01:18:07AM +0000, Minda Chen wrote:
>
>
> >
> > On Fri, Jun 21, 2024 at 04:22:31PM +0800, Minda Chen wrote:
> > > Add PCIe dts configuraion for JH7110 SoC platform.
> >
> > I think the commit message should mention that the star64 doesn't have a pci
> > port exposed. If nothing else crops up, I'll edit it myself if that's okay?
> >
> > Thanks,
> > Conor.
> >
> Okay. Thanks.
I've queued this Emil, scream if you're not okay with it please...
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prev parent reply other threads:[~2024-06-24 16:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-21 8:22 [PATCH v2 0/1] Add PCIe dts configuration for JH7110 Minda Chen
2024-06-21 8:22 ` [PATCH v2 1/1] riscv: dts: starfive: add " Minda Chen
2024-06-22 12:08 ` Conor Dooley
2024-06-24 1:18 ` Minda Chen
2024-06-24 16:32 ` Conor Dooley [this message]
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