[PATCH 1/7] dt-bindings: interrupt-controller: Add bcm2712 MSI-X DT bindings

[Stanimir Varbanov <svarbanov@suse.de>]

Adds DT bindings for bcm2712 MSI-X interrupt peripheral controller.

Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
 .../brcm,bcm2712-msix.yaml                    | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml
new file mode 100644
index 000000000000..ca610e4467d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
+
+maintainers:
+  - Stanimir Varbanov <svarbanov@suse.de>
+
+description: >
+  This interrupt controller is used to provide intterupt vectors to the
+  generic interrupt controller (GIC) on bcm2712. It will be used as
+  external MSI-X controller for PCIe root complex.
+
+allOf:
+  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - "brcm,bcm2712-mip-intc"
+  reg:
+    maxItems: 1
+    description: >
+      Specifies the base physical address and size of the registers
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+  msi-controller: true
+
+  brcm,msi-base-spi:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The SGI number that MSIs start.
+
+  brcm,msi-num-spis:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The number of SGIs for MSIs.
+
+  brcm,msi-offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Shift the allocated MSIs up by N.
+
+  brcm,msi-pci-addr:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description: MSI-X message address.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - "#interrupt-cells"
+  - msi-controller
+
+examples:
+  - |
+    msi-controller@130000 {
+      compatible = "brcm,bcm2712-mip-intc";
+      reg = <0x00130000 0xc0>;
+      msi-controller;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      brcm,msi-base-spi = <128>;
+      brcm,msi-num-spis = <64>;
+      brcm,msi-offset = <0>;
+      brcm,msi-pci-addr = <0xff 0xfffff000>;
+    };
-- 
2.43.0