* [PATCH 1/3] dt-bindings: soc: mobileye: add EyeQ OLB system controller
2024-06-28 16:11 [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Théo Lebrun
@ 2024-06-28 16:11 ` Théo Lebrun
2024-06-28 16:11 ` [PATCH 2/3] MIPS: mobileye: eyeq5: add OLB system-controller node Théo Lebrun
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Théo Lebrun @ 2024-06-28 16:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, Vladimir Kondratiev,
Grégory Clement, Thomas Petazzoni, Tawfik Bayouk,
Théo Lebrun
Add documentation to describe the "Other Logic Block" system-controller.
It deals with three platforms: EyeQ5, EyeQ6L and EyeQ6H. First two have
a single instance, whereas EyeQ6H has seven named instances.
Features provided are:
- Clocks, children to main crystal. Some PLLs and divider clocks.
- Resets. Some instances DO NOT have reset.
- Pinctrl. Only EyeQ5 has such feature.
Those are NOT the only features exposed in OLB system-controllers! Many
individual registers, related to IP block integration, can be found.
Additional features will be exposed over time.
We simplify devicetree phandles to OLB in two ways:
- Compatibles exposing a single clock do not ask for a index argument.
This means we use EyeQ6H OLB south (it has four clocks):
clocks = <&olb_south EQ6HC_SOUTH_PLL_PER>;
But use EyeQ6H OLB east (it has one clock):
clocks = <&olb_east>;
- Compatibles exposing a single reset domain do not ask for a domain
index, only a reset index.
This means we use EyeQ5 OLB (it has three domains):
resets = <&olb 0 10>;
But use EyeQ6H west reset (it has one domain):
resets = <&olb_west 3>;
About pinctrl subnodes: all pins have two functionality, either GPIO or
something-else. The latter is pin dependent, we express constraints
using many if-then.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
.../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 374 +++++++++++++++++++++
1 file changed, 374 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
new file mode 100644
index 000000000000..f7e606d45ebc
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
@@ -0,0 +1,374 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ SoC system controller
+
+maintainers:
+ - Grégory Clement <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+description:
+ OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks,
+ resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
+ instance. EyeQ6H hosts seven instances.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mobileye,eyeq5-olb
+ - mobileye,eyeq6l-olb
+ - mobileye,eyeq6h-acc-olb
+ - mobileye,eyeq6h-central-olb
+ - mobileye,eyeq6h-east-olb
+ - mobileye,eyeq6h-west-olb
+ - mobileye,eyeq6h-south-olb
+ - mobileye,eyeq6h-ddr0-olb
+ - mobileye,eyeq6h-ddr1-olb
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ description:
+ First cell is domain and optional if compatible has a single reset domain.
+ Second cell is reset index inside that domain.
+ enum: [ 1, 2 ]
+
+ '#clock-cells':
+ description:
+ Cell is clock index. Optional if compatible has a single clock.
+ enum: [ 0, 1 ]
+
+ clocks:
+ maxItems: 1
+ description:
+ Input parent clock to all PLLs. Expected to be the main crystal.
+
+ clock-names:
+ const: ref
+
+patternProperties:
+ '-pins?$':
+ type: object
+ description: Pin muxing configuration.
+ $ref: /schemas/pinctrl/pinmux-node.yaml#
+ additionalProperties: false
+ properties:
+ pins: true
+ function:
+ enum: [gpio,
+ # Bank A
+ timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
+ spi1, refclk0,
+ # Bank B
+ timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ required:
+ - pins
+ - function
+ allOf:
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ pins:
+ items: # PA0 - PA28, PB0 - PB22
+ pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
+ - if:
+ properties:
+ function:
+ const: timer0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA0, PA1]
+ - if:
+ properties:
+ function:
+ const: timer1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA2, PA3]
+ - if:
+ properties:
+ function:
+ const: timer2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA4, PA5]
+ - if:
+ properties:
+ function:
+ const: timer5
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA6, PA7, PA8, PA9]
+ - if:
+ properties:
+ function:
+ const: uart0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA10, PA11]
+ - if:
+ properties:
+ function:
+ const: uart1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA12, PA13]
+ - if:
+ properties:
+ function:
+ const: can0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA14, PA15]
+ - if:
+ properties:
+ function:
+ const: can1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA16, PA17]
+ - if:
+ properties:
+ function:
+ const: spi0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA18, PA19, PA20, PA21, PA22]
+ - if:
+ properties:
+ function:
+ const: spi1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA23, PA24, PA25, PA26, PA27]
+ - if:
+ properties:
+ function:
+ const: refclk0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA28]
+ - if:
+ properties:
+ function:
+ const: timer3
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB0, PB1]
+ - if:
+ properties:
+ function:
+ const: timer4
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB2, PB3]
+ - if:
+ properties:
+ function:
+ const: timer6
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB4, PB5, PB6, PB7]
+ - if:
+ properties:
+ function:
+ const: uart2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB8, PB9]
+ - if:
+ properties:
+ function:
+ const: can2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB10, PB11]
+ - if:
+ properties:
+ function:
+ const: spi2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB12, PB13, PB14, PB15, PB16]
+ - if:
+ properties:
+ function:
+ const: spi3
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB17, PB18, PB19, PB20, PB21]
+ - if:
+ properties:
+ function:
+ const: mclk0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB22]
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+allOf:
+ # Compatibles exposing a single reset domain.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq6h-acc-olb
+ - mobileye,eyeq6h-east-olb
+ - mobileye,eyeq6h-west-olb
+ then:
+ properties:
+ '#reset-cells':
+ const: 1
+ required:
+ - '#reset-cells'
+
+ # Compatibles exposing two reset domains.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq5-olb
+ - mobileye,eyeq6l-olb
+ then:
+ properties:
+ '#reset-cells':
+ const: 2
+ required:
+ - '#reset-cells'
+
+ # Compatibles not exposing resets.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq6h-central-olb
+ - mobileye,eyeq6h-south-olb
+ - mobileye,eyeq6h-ddr0-olb
+ - mobileye,eyeq6h-ddr1-olb
+ then:
+ properties:
+ '#reset-cells': false
+
+ # Compatibles exposing a single clock.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq6h-central-olb
+ - mobileye,eyeq6h-east-olb
+ - mobileye,eyeq6h-west-olb
+ - mobileye,eyeq6h-ddr0-olb
+ - mobileye,eyeq6h-ddr1-olb
+ then:
+ properties:
+ '#clock-cells':
+ const: 0
+ else:
+ properties:
+ '#clock-cells':
+ const: 1
+
+ # Only EyeQ5 has pinctrl in OLB.
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: mobileye,eyeq5-olb
+ then:
+ patternProperties:
+ '-pins?$': false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-controller@e00000 {
+ compatible = "mobileye,eyeq5-olb", "syscon";
+ reg = <0 0xe00000 0x0 0x400>;
+ #reset-cells = <2>;
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "ref";
+ };
+ };
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-controller@d2003000 {
+ compatible = "mobileye,eyeq6h-acc-olb", "syscon";
+ reg = <0x0 0xd2003000 0x0 0x1000>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "ref";
+ };
+ };
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/3] MIPS: mobileye: eyeq5: add OLB system-controller node
2024-06-28 16:11 [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Théo Lebrun
2024-06-28 16:11 ` [PATCH 1/3] dt-bindings: soc: mobileye: add EyeQ OLB system controller Théo Lebrun
@ 2024-06-28 16:11 ` Théo Lebrun
2024-06-28 16:11 ` [PATCH 3/3] MAINTAINERS: Mobileye: add OLB drivers and dt-bindings Théo Lebrun
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Théo Lebrun @ 2024-06-28 16:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, Vladimir Kondratiev,
Grégory Clement, Thomas Petazzoni, Tawfik Bayouk,
Théo Lebrun
The OLB ("Other Logic Block") is a system-controller region hosting
clock, reset and pin controllers. It contains registers such as I2C
speed mode that need to be accessible by other nodes.
Remove fixed-clocks previously used; replace references.
Add parent crystal clock, fixed at 30MHz.
Add pin nodes for all functions.
Add mobileye,eyeq5-olb compatible node, hosting clk, reset and pinctrl.
Add reset and pinctrl references to UART nodes.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
.../{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 54 +++------
arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi | 125 +++++++++++++++++++++
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 22 +++-
3 files changed, 162 insertions(+), 39 deletions(-)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi
similarity index 88%
rename from arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
rename to arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi
index 78f5533a95c6..17a342cc744e 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi
@@ -3,42 +3,20 @@
* Copyright 2023 Mobileye Vision Technologies Ltd.
*/
+#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+
/ {
/* Fixed clock */
- pll_cpu: pll-cpu {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1500000000>;
- };
-
- pll_vdi: pll-vdi {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1280000000>;
- };
-
- pll_per: pll-per {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <2000000000>;
- };
-
- pll_ddr0: pll-ddr0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1857210000>;
- };
-
- pll_ddr1: pll-ddr1 {
+ xtal: xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <1857210000>;
+ clock-frequency = <30000000>;
};
/* PLL_CPU derivatives */
occ_cpu: occ-cpu {
compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
+ clocks = <&olb EQ5C_PLL_CPU>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
@@ -101,7 +79,7 @@ mem_clk: mem-clk {
};
occ_isram: occ-isram {
compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
+ clocks = <&olb EQ5C_PLL_CPU>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
@@ -115,7 +93,7 @@ isram_clk: isram-clk { /* gate ClkRstGen_isram */
};
occ_dbu: occ-dbu {
compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
+ clocks = <&olb EQ5C_PLL_CPU>;
#clock-cells = <0>;
clock-div = <10>;
clock-mult = <1>;
@@ -130,7 +108,7 @@ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
/* PLL_VDI derivatives */
occ_vdi: occ-vdi {
compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
+ clocks = <&olb EQ5C_PLL_VDI>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
@@ -144,7 +122,7 @@ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
};
occ_can_ser: occ-can-ser {
compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
+ clocks = <&olb EQ5C_PLL_VDI>;
#clock-cells = <0>;
clock-div = <16>;
clock-mult = <1>;
@@ -158,7 +136,7 @@ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
};
i2c_ser_clk: i2c-ser-clk {
compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
+ clocks = <&olb EQ5C_PLL_VDI>;
#clock-cells = <0>;
clock-div = <20>;
clock-mult = <1>;
@@ -166,7 +144,7 @@ i2c_ser_clk: i2c-ser-clk {
/* PLL_PER derivatives */
occ_periph: occ-periph {
compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
+ clocks = <&olb EQ5C_PLL_PER>;
#clock-cells = <0>;
clock-div = <16>;
clock-mult = <1>;
@@ -225,7 +203,7 @@ gpio_clk: gpio-clk {
};
emmc_sys_clk: emmc-sys-clk {
compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
+ clocks = <&olb EQ5C_PLL_PER>;
#clock-cells = <0>;
clock-div = <10>;
clock-mult = <1>;
@@ -233,7 +211,7 @@ emmc_sys_clk: emmc-sys-clk {
};
ccf_ctrl_clk: ccf-ctrl-clk {
compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
+ clocks = <&olb EQ5C_PLL_PER>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
@@ -241,7 +219,7 @@ ccf_ctrl_clk: ccf-ctrl-clk {
};
occ_mjpeg_core: occ-mjpeg-core {
compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
+ clocks = <&olb EQ5C_PLL_PER>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
@@ -265,7 +243,7 @@ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
};
fcmu_a_clk: fcmu-a-clk {
compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
+ clocks = <&olb EQ5C_PLL_PER>;
#clock-cells = <0>;
clock-div = <20>;
clock-mult = <1>;
@@ -273,7 +251,7 @@ fcmu_a_clk: fcmu-a-clk {
};
occ_pci_sys: occ-pci-sys {
compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
+ clocks = <&olb EQ5C_PLL_PER>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi
new file mode 100644
index 000000000000..0b3671013ab4
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+/*
+ * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
+ * pin configuration node per function.
+ */
+
+&olb {
+ timer0_pins: timer0-pins {
+ function = "timer0";
+ pins = "PA0", "PA1";
+ };
+ timer1_pins: timer1-pins {
+ function = "timer1";
+ pins = "PA2", "PA3";
+ };
+ timer2_pins: timer2-pins {
+ function = "timer2";
+ pins = "PA4", "PA5";
+ };
+ pps0_pins: pps0-pin {
+ function = "timer2";
+ pins = "PA4";
+ };
+ pps1_pins: pps1-pin {
+ function = "timer2";
+ pins = "PA5";
+ };
+ timer5_ext_pins: timer5-ext-pins {
+ function = "timer5";
+ pins = "PA6", "PA7", "PA8", "PA9";
+ };
+ timer5_ext_input_pins: timer5-ext-input-pins {
+ function = "timer5";
+ pins = "PA6", "PA7";
+ };
+ timer5_ext_incap_a_pins: timer5-ext-incap-a-pin {
+ function = "timer5";
+ pins = "PA6";
+ };
+ timer5_ext_incap_b_pins: timer5-ext-incap-b-pin {
+ function = "timer5";
+ pins = "PA7";
+ };
+ can0_pins: can0-pins {
+ function = "can0";
+ pins = "PA14", "PA15";
+ };
+ can1_pins: can1-pins {
+ function = "can1";
+ pins = "PA16", "PA17";
+ };
+ uart0_pins: uart0-pins {
+ function = "uart0";
+ pins = "PA10", "PA11";
+ };
+ uart1_pins: uart1-pins {
+ function = "uart1";
+ pins = "PA12", "PA13";
+ };
+ spi0_pins: spi0-pins {
+ function = "spi0";
+ pins = "PA18", "PA19", "PA20", "PA21", "PA22";
+ };
+ spi1_pins: spi1-pins {
+ function = "spi1";
+ pins = "PA23", "PA24", "PA25", "PA26", "PA27";
+ };
+ spi1_slave_pins: spi1-slave-pins {
+ function = "spi1";
+ pins = "PA24", "PA25", "PA26";
+ };
+ refclk0_pins: refclk0-pin {
+ function = "refclk0";
+ pins = "PA28";
+ };
+ timer3_pins: timer3-pins {
+ function = "timer3";
+ pins = "PB0", "PB1";
+ };
+ timer4_pins: timer4-pins {
+ function = "timer4";
+ pins = "PB2", "PB3";
+ };
+ timer6_ext_pins: timer6-ext-pins {
+ function = "timer6";
+ pins = "PB4", "PB5", "PB6", "PB7";
+ };
+ timer6_ext_input_pins: timer6-ext-input-pins {
+ function = "timer6";
+ pins = "PB4", "PB5";
+ };
+ timer6_ext_incap_a_pins: timer6-ext-incap-a-pin {
+ function = "timer6";
+ pins = "PB4";
+ };
+ timer6_ext_incap_b_pins: timer6-ext-incap-b-pin {
+ function = "timer6";
+ pins = "PB5";
+ };
+ can2_pins: can2-pins {
+ function = "can2";
+ pins = "PB10", "PB11";
+ };
+ uart2_pins: uart2-pins {
+ function = "uart2";
+ pins = "PB8", "PB9";
+ };
+ spi2_pins: spi2-pins {
+ function = "spi2";
+ pins = "PB12", "PB13", "PB14", "PB15", "PB16";
+ };
+ spi3_pins: spi3-pins {
+ function = "spi3";
+ pins = "PB17", "PB18", "PB19", "PB20", "PB21";
+ };
+ spi3_slave_pins: spi3-slave-pins {
+ function = "spi3";
+ pins = "PB18", "PB19", "PB20";
+ };
+ mclk0_pins: mclk0-pin {
+ function = "mclk0";
+ pins = "PB22";
+ };
+};
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 6cc5980e2fa1..0708771c193d 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -5,7 +5,7 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
-#include "eyeq5-fixed-clocks.dtsi"
+#include "eyeq5-clocks.dtsi"
/ {
#address-cells = <2>;
@@ -78,6 +78,9 @@ uart0: serial@800000 {
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&olb 0 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
};
uart1: serial@900000 {
@@ -88,6 +91,9 @@ uart1: serial@900000 {
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&olb 0 11>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
};
uart2: serial@a00000 {
@@ -98,6 +104,18 @@ uart2: serial@a00000 {
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&olb 0 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ };
+
+ olb: system-controller@e00000 {
+ compatible = "mobileye,eyeq5-olb", "syscon";
+ reg = <0 0xe00000 0x0 0x400>;
+ #reset-cells = <2>;
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "ref";
};
gic: interrupt-controller@140000 {
@@ -122,3 +140,5 @@ timer {
};
};
};
+
+#include "eyeq5-pins.dtsi"
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/3] MAINTAINERS: Mobileye: add OLB drivers and dt-bindings
2024-06-28 16:11 [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Théo Lebrun
2024-06-28 16:11 ` [PATCH 1/3] dt-bindings: soc: mobileye: add EyeQ OLB system controller Théo Lebrun
2024-06-28 16:11 ` [PATCH 2/3] MIPS: mobileye: eyeq5: add OLB system-controller node Théo Lebrun
@ 2024-06-28 16:11 ` Théo Lebrun
2024-07-03 14:35 ` [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Thomas Bogendoerfer
2024-07-03 15:19 ` Thomas Bogendoerfer
4 siblings, 0 replies; 7+ messages in thread
From: Théo Lebrun @ 2024-06-28 16:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, Vladimir Kondratiev,
Grégory Clement, Thomas Petazzoni, Tawfik Bayouk,
Théo Lebrun
Register OLB-related files part of the "MOBILEYE MIPS SOCS" MAINTAINERS
section. Those include:
- drivers (clk-eyeq, reset-eyeq, pinctrl-eyeq5),
- dt-bindings (mobileye,eyeq5-olb.yaml file),
- bindings includes file <dt-bindings/clock/mobileye,eyeq5-clk.h>.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ca8f35dfe03..b3732165b824 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15194,9 +15194,14 @@ M: Théo Lebrun <theo.lebrun@bootlin.com>
L: linux-mips@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/mips/mobileye.yaml
+F: Documentation/devicetree/bindings/soc/mobileye/
F: arch/mips/boot/dts/mobileye/
F: arch/mips/configs/eyeq5_defconfig
F: arch/mips/mobileye/board-epm5.its.S
+F: drivers/clk/clk-eyeq.c
+F: drivers/pinctrl/pinctrl-eyeq5.c
+F: drivers/reset/reset-eyeq.c
+F: include/dt-bindings/clock/mobileye,eyeq5-clk.h
MODULE SUPPORT
M: Luis Chamberlain <mcgrof@kernel.org>
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller
2024-06-28 16:11 [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Théo Lebrun
` (2 preceding siblings ...)
2024-06-28 16:11 ` [PATCH 3/3] MAINTAINERS: Mobileye: add OLB drivers and dt-bindings Théo Lebrun
@ 2024-07-03 14:35 ` Thomas Bogendoerfer
2024-07-03 14:52 ` Théo Lebrun
2024-07-03 15:19 ` Thomas Bogendoerfer
4 siblings, 1 reply; 7+ messages in thread
From: Thomas Bogendoerfer @ 2024-07-03 14:35 UTC (permalink / raw)
To: Théo Lebrun
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-mips,
devicetree, linux-kernel, Vladimir Kondratiev,
Grégory Clement, Thomas Petazzoni, Tawfik Bayouk
On Fri, Jun 28, 2024 at 06:11:49PM +0200, Théo Lebrun wrote:
> This is a new iteration on the Mobileye system-controller series [0].
> It has been split into separate series to facilitate merging.
>
> This series contains a dt-bindings defining the system-controller
> (called OLB) used on EyeQ5, EyeQ6L and EyeQ6H. It then modifies the
> EyeQ5 devicetree to exploit that system-controller.
just to be sure, this replaces the v3 series ? And it's the only
series, which should go through the MIPS tree ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller
2024-07-03 14:35 ` [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Thomas Bogendoerfer
@ 2024-07-03 14:52 ` Théo Lebrun
0 siblings, 0 replies; 7+ messages in thread
From: Théo Lebrun @ 2024-07-03 14:52 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-mips,
devicetree, linux-kernel, Vladimir Kondratiev,
Grégory Clement, Thomas Petazzoni, Tawfik Bayouk
Hello Thomas,
On Wed Jul 3, 2024 at 4:35 PM CEST, Thomas Bogendoerfer wrote:
> On Fri, Jun 28, 2024 at 06:11:49PM +0200, Théo Lebrun wrote:
> > This is a new iteration on the Mobileye system-controller series [0].
> > It has been split into separate series to facilitate merging.
> >
> > This series contains a dt-bindings defining the system-controller
> > (called OLB) used on EyeQ5, EyeQ6L and EyeQ6H. It then modifies the
> > EyeQ5 devicetree to exploit that system-controller.
>
> just to be sure, this replaces the v3 series ? And it's the only
> series, which should go through the MIPS tree ?
Sorry it was not clear enough. I confirm this replaces the V3.
It is the only series that should go through the MIPS tree.
The remaining three series have had their V2 sent a few minutes ago.
Each series contains the removal of the old dt-bindings and the three
clk/reset/pinctrl drivers.
https://lore.kernel.org/lkml/20240703-mbly-clk-v2-0-fe8c6199a579@bootlin.com/
https://lore.kernel.org/lkml/20240703-mbly-reset-v2-0-3fe853d78139@bootlin.com/
https://lore.kernel.org/lkml/20240703-mbly-pinctrl-v2-0-eab5f69f1b01@bootlin.com/
Thanks,
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller
2024-06-28 16:11 [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Théo Lebrun
` (3 preceding siblings ...)
2024-07-03 14:35 ` [PATCH 0/3] MIPS: Add Mobileye EyeQ OLB system-controller Thomas Bogendoerfer
@ 2024-07-03 15:19 ` Thomas Bogendoerfer
4 siblings, 0 replies; 7+ messages in thread
From: Thomas Bogendoerfer @ 2024-07-03 15:19 UTC (permalink / raw)
To: Théo Lebrun
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-mips,
devicetree, linux-kernel, Vladimir Kondratiev,
Grégory Clement, Thomas Petazzoni, Tawfik Bayouk
On Fri, Jun 28, 2024 at 06:11:49PM +0200, Théo Lebrun wrote:
> This is a new iteration on the Mobileye system-controller series [0].
> It has been split into separate series to facilitate merging.
>
> This series contains a dt-bindings defining the system-controller
> (called OLB) used on EyeQ5, EyeQ6L and EyeQ6H. It then modifies the
> EyeQ5 devicetree to exploit that system-controller.
>
> The last patch adds entries in MAINTAINERS for all related files. This
> is done in a single commit to avoid conflicts across trees.
>
> Related series are targeted at clk [1], reset [2] and pinctrl [3].
>
> Have a nice day,
> Théo
>
> [0]: https://lore.kernel.org/lkml/20240620-mbly-olb-v3-0-5f29f8ca289c@bootlin.com/
> [1]: https://lore.kernel.org/lkml/20240628-mbly-clk-v1-0-edb1e29ea4c1@bootlin.com/
> [2]: https://lore.kernel.org/lkml/20240628-mbly-reset-v1-0-2a8294fd4392@bootlin.com/
> [3]: https://lore.kernel.org/lkml/20240628-mbly-pinctrl-v1-0-c878192d6b0a@bootlin.com/
>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> Changes since OLB v3 [0]:
> - MAINTAINERS: Move changes into a separate commit to avoid merge
> conflicts. This commit is in the present series.
> - dt-bindings: Take Reviewed-by: Rob Herring.
>
> ---
> Théo Lebrun (3):
> dt-bindings: soc: mobileye: add EyeQ OLB system controller
> MIPS: mobileye: eyeq5: add OLB system-controller node
> MAINTAINERS: Mobileye: add OLB drivers and dt-bindings
>
> .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 374 +++++++++++++++++++++
> MAINTAINERS | 5 +
> .../{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 54 +--
> arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi | 125 +++++++
> arch/mips/boot/dts/mobileye/eyeq5.dtsi | 22 +-
> 5 files changed, 541 insertions(+), 39 deletions(-)
series applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 7+ messages in thread