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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7086207ed02sm1809877b3a.95.2024.06.28.14.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 14:00:49 -0700 (PDT) Date: Sat, 29 Jun 2024 06:00:47 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Krishna chaitanya chundru Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , quic_vbadigan@quicinc.com, quic_skananth@quicinc.com, quic_nitegupt@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski Subject: Re: [PATCH v15 0/4] PCI: qcom: Add support for OPP Message-ID: <20240628210047.GB2206339@rocinante> References: <20240619-opp_support-v15-0-aa769a2173a3@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240619-opp_support-v15-0-aa769a2173a3@quicinc.com> Hello, > This patch adds support for OPP to vote for the performance state of RPMH > power domain based upon PCIe speed it got enumerated. > > QCOM Resource Power Manager-hardened (RPMh) is a hardware block which > maintains hardware state of a regulator by performing max aggregation of > the requests made by all of the processors. > > PCIe controller can operate on different RPMh performance state of power > domain based up on the speed of the link. And this performance state varies > from target to target. > > It is manadate to scale the performance state based up on the PCIe speed > link operates so that SoC can run under optimum power conditions. > > Add Operating Performance Points(OPP) support to vote for RPMh state based > upon GEN speed link is operating. > > Before link up PCIe driver will vote for the maximum performance state. > > As now we are adding ICC BW vote in OPP, the ICC BW voting depends both > GEN speed and link width using opp-level to indicate the opp entry table > will be difficult. > > In PCIe certain gen speeds like 2.5GT/s x2 & 5.0 GT/s X1 or 8.0 GT/s x2 & > 16GT/s x1 use same ICC bw if we use freq in the OPP table to represent the > PCIe speed number of PCIe entries can reduced. > > So going back to use freq in the OPP table instead of level. > > To access PCIe registers of the host controller and endpoint PCIe > BAR space, config space the CPU-PCIe ICC (interconnect) path should > be voted otherwise it may lead to NoC (Network on chip) timeout. > We are surviving because of other driver voting for this path. > > As there is less access on this path compared to PCIe to mem path > add minimum vote i.e 1KBps bandwidth always which is sufficient enough > to keep the path active and is recommended by HW team. > > In suspend to ram case there can be some DBI access. Except in suspend > to ram case disable CPU-PCIe ICC path after register space access > is done. Applied to controller/qcom, thank you! [01/03] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path https://git.kernel.org/pci/pci/c/18f331d9c6db [02/03] PCI: Bring the PCIe speed to MBps logic to new pcie_dev_speed_mbps() https://git.kernel.org/pci/pci/c/4bf3029dc2a1 [03/03] PCI: qcom: Add OPP support to scale performance https://git.kernel.org/pci/pci/c/78b5f6f8855e Krzysztof