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AJvYcCXHV3z+XRs0UqkzkpY93dcykLcwRkNnl/KpX/czYEtlYgGm+pBLfPsAsh7wh/0LECdVeiOD9sOoxIPoX7/bAE/wVEvzIXhD+PL/9A== X-Gm-Message-State: AOJu0Ywp7E9fmMr/NKHAPTlfRXvdH0T9sByN90uV/6rWESpgPr/8cjNv r3U/O2vgjH1XMtDDTSDnx+wrmIQgDojqfkcHfcW8FWTYUz+/i7tMs2jPDvsryA== X-Google-Smtp-Source: AGHT+IE5aU4sW0gZNOnsBZmQhd5QPQlm2dJswEqAC+AISCYfDs6s10N0soFFT4U1SUdqSjSMRwrfaA== X-Received: by 2002:a17:903:2349:b0:1f7:23ee:d496 with SMTP id d9443c01a7336-1fadbcb2064mr6324365ad.30.1719666333190; Sat, 29 Jun 2024 06:05:33 -0700 (PDT) Received: from thinkpad ([220.158.156.249]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac1598576sm31531345ad.278.2024.06.29.06.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jun 2024 06:05:32 -0700 (PDT) Date: Sat, 29 Jun 2024 18:35:25 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Jason Liu Subject: Re: [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Message-ID: <20240629130525.GC5608@thinkpad> References: <20240617-pci2_upstream-v6-0-e0821238f997@nxp.com> <20240617-pci2_upstream-v6-2-e0821238f997@nxp.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240617-pci2_upstream-v6-2-e0821238f997@nxp.com> On Mon, Jun 17, 2024 at 04:16:38PM -0400, Frank Li wrote: > From: Richard Zhu > > Correct occasional MSI triggering failures in i.MX8MP PCIe EP by apply 64KB > hardware alignment requirement. > > MSI triggering fail if the outbound MSI memory region (ep->msi_mem) is not > aligned to 64KB. > > In dw_pcie_ep_init(): > > ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > epc->mem->window.page_size); > So this is an alignment restriction w.r.t iATU. In that case, we should be passing 'pci_epc_features::align' instead? - Mani > Set ep->page_size to match drvdata::epc_features::align since different > SOCs have different alignment requirements. > > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") > Signed-off-by: Richard Zhu > Acked-by: Jason Liu > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-imx6.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 9a71b8aa09b3c..ca9a000c9a96d 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > + ep->page_size = imx6_pcie->drvdata->epc_features->align; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்