From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Frank Li <Frank.Li@nxp.com>
Cc: "Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>,
"NXP Linux Team" <linux-imx@nxp.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Mark Brown" <broonie@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
linux-pci@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, bpf@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode
Date: Sun, 30 Jun 2024 21:53:37 +0530 [thread overview]
Message-ID: <20240630162337.GD5264@thinkpad> (raw)
In-Reply-To: <20240617-pci2_upstream-v6-9-e0821238f997@nxp.com>
On Mon, Jun 17, 2024 at 04:16:45PM -0400, Frank Li wrote:
You don't need the colon after 'Call' in subject.
> Invoke the common PHY API to configure mode, speed, and submode. While
> these functions are optional in the PHY interface, they are necessary for
> certain PHY drivers. Lack of support for these functions in a PHY driver
> does not cause harm.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index ab0ed7ab3007a..18c133f5a56fc 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -30,6 +30,7 @@
> #include <linux/interrupt.h>
> #include <linux/reset.h>
> #include <linux/phy/phy.h>
> +#include <linux/phy/pcie.h>
This should be moved one entry above.
> #include <linux/pm_domain.h>
> #include <linux/pm_runtime.h>
>
> @@ -229,6 +230,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
>
> id = imx_pcie->controller_id;
>
> + /* If mode_mask[0] is 0, means use phy driver to set mode */
/* If mode_mask is 0, then generic PHY driver is used to set the mode */
> + if (!drvdata->mode_mask[0])
> + return;
> +
> /* If mode_mask[id] is zero, means each controller have its individual gpr */
> if (!drvdata->mode_mask[id])
> id = 0;
> @@ -808,6 +813,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
> struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
Is this setting really universal? This looks like applicable only to specific
platforms supporting this link speed.
> if (drvdata->ltssm_mask)
> regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
> drvdata->ltssm_mask);
> @@ -820,6 +826,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
> struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> + phy_set_speed(imx_pcie->phy, 0);
> if (drvdata->ltssm_mask)
> regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
> drvdata->ltssm_mask, 0);
> @@ -955,6 +962,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> goto err_clk_disable;
> }
>
> + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> + if (ret) {
> + dev_err(dev, "unable to set pcie PHY mode\n");
s/pcie/PCIe
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-06-30 16:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-17 20:16 [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-06-17 20:16 ` [PATCH v6 01/10] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li
2024-06-29 12:23 ` Manivannan Sadhasivam
2024-06-17 20:16 ` [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Frank Li
2024-06-29 13:05 ` Manivannan Sadhasivam
2024-07-01 18:32 ` Frank Li
2024-07-06 17:39 ` Manivannan Sadhasivam
2024-06-17 20:16 ` [PATCH v6 03/10] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-06-17 20:16 ` [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
2024-06-30 16:04 ` Manivannan Sadhasivam
2024-06-17 20:16 ` [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
2024-06-30 16:10 ` Manivannan Sadhasivam
2024-06-17 20:16 ` [PATCH v6 06/10] PCI: imx6: Improve comment for workaround ERR010728 Frank Li
2024-06-30 16:13 ` Manivannan Sadhasivam
2024-07-01 0:10 ` Fabio Estevam
2024-06-17 20:16 ` [PATCH v6 07/10] PCI: imx6: Consolidate redundant if-checks Frank Li
2024-06-17 20:16 ` [PATCH v6 08/10] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li
2024-06-17 20:16 ` [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
2024-06-30 16:23 ` Manivannan Sadhasivam [this message]
2024-07-08 16:01 ` Frank Li
2024-06-17 20:16 ` [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Frank Li
2024-06-30 16:51 ` Manivannan Sadhasivam
2024-07-01 18:28 ` Frank Li
2024-06-25 14:47 ` [PATCH v6 00/10] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
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