From: Yixun Lan <dlan@gentoo.org>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Lubomir Rintel <lkundrak@v3.sk>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@sifive.com>,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
Inochi Amaoto <inochiama@outlook.com>,
Meng Zhang <zhangmeng.kevin@spacemit.com>,
Yangyu Chen <cyy@cyyself.name>
Subject: Re: [PATCH v2 08/10] riscv: dts: add initial SpacemiT K1 SoC device tree
Date: Tue, 2 Jul 2024 01:28:47 +0000 [thread overview]
Message-ID: <20240702012847.GA2447193@ofsar> (raw)
In-Reply-To: <CAJM55Z9jeAQTsVjRiLeofDm1RyMWCuHXC0a-pdKtpUiTkSjJCA@mail.gmail.com>
On 12:49 Mon 01 Jul , Emil Renner Berthing wrote:
> Yixun Lan wrote:
> > From: Yangyu Chen <cyy@cyyself.name>
> >
> > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> >
> > Key features:
> > - 4 cores per cluster, 2 clusters on chip
> > - UART IP is Intel XScale UART
> >
> > Some key considerations:
> > - ISA string is inferred from vendor documentation[2]
> > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > - No coherent DMA on this board
> > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > kernel. Without dma-noncoherent in soc node, the driver fails.
> > - No cache nodes now
> > The parameters from vendor dts are likely to be wrong. It has 512
> > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > When the size of the cache line is 64B, it is a directly mapped
> > cache rather than a set-associative cache, the latter is commonly
> > used. Thus, I didn't use the parameters from vendor dts.
> >
> > Currently only support booting into console with only uart, other
> > features will be added soon later.
> >
...
> > + clint: timer@e4000000 {
> > + compatible = "spacemit,k1-clint", "sifive,clint0";
> > + reg = <0x0 0xe4000000 0x0 0x10000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > + <&cpu1_intc 3>, <&cpu1_intc 7>,
> > + <&cpu2_intc 3>, <&cpu2_intc 7>,
> > + <&cpu3_intc 3>, <&cpu3_intc 7>,
> > + <&cpu4_intc 3>, <&cpu4_intc 7>,
> > + <&cpu5_intc 3>, <&cpu5_intc 7>,
> > + <&cpu6_intc 3>, <&cpu6_intc 7>,
> > + <&cpu7_intc 3>, <&cpu7_intc 7>;
> > + };
> > +
> > + uart0: serial@d4017000 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017000 0x0 0x100>;
> > + interrupts = <42>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + /* note: uart1 skipped */
>
> The datasheet page you link to above says "-UART (×10)", but here you're
> skipping one of them. Why? I can see the vendor tree does the same, but it
> would be nice with an explanation of what's going on.
>
/* note: uart1 in 0xf0612000, reserved for TEE usage */
I would put something like this, does this sound ok to you?
more detail, iomem range from 0xf000,0000 - 0xf080,0000 are dedicated for TEE purpose,
It won't be exposed to Linux once TEE feature is enabled..
skipping uart1 may make people confused but we are trying to follow datasheet..
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
next prev parent reply other threads:[~2024-07-02 1:28 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-27 15:31 [PATCH v2 00/10] riscv: add initial support for SpacemiT K1 Yixun Lan
2024-06-27 15:31 ` [PATCH v2 01/10] dt-bindings: vendor-prefixes: add spacemit Yixun Lan
2024-06-28 7:32 ` Krzysztof Kozlowski
2024-06-27 15:31 ` [PATCH v2 02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles Yixun Lan
2024-07-01 12:25 ` Conor Dooley
2024-06-27 15:31 ` [PATCH v2 03/10] dt-bindings: riscv: add SpacemiT K1 bindings Yixun Lan
2024-06-27 18:00 ` Rob Herring (Arm)
2024-06-28 7:34 ` Krzysztof Kozlowski
2024-06-28 8:44 ` Yixun Lan
2024-07-01 12:24 ` Conor Dooley
2024-07-02 9:42 ` Yixun Lan
2024-06-27 15:31 ` [PATCH v2 04/10] dt-bindings: timer: Add SpacemiT K1 CLINT Yixun Lan
2024-07-01 12:22 ` Conor Dooley
2024-06-27 15:31 ` [PATCH v2 05/10] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC Yixun Lan
2024-06-27 15:31 ` [PATCH v2 06/10] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible Yixun Lan
2024-07-01 12:22 ` Conor Dooley
2024-06-27 15:31 ` [PATCH v2 07/10] riscv: add SpacemiT SOC family Kconfig support Yixun Lan
2024-07-01 12:25 ` Conor Dooley
2024-06-27 15:31 ` [PATCH v2 08/10] riscv: dts: add initial SpacemiT K1 SoC device tree Yixun Lan
2024-07-01 12:49 ` Emil Renner Berthing
2024-07-02 1:28 ` Yixun Lan [this message]
2024-07-02 1:35 ` Inochi Amaoto
2024-07-02 15:25 ` Conor Dooley
2024-07-03 9:40 ` Yixun Lan
2024-07-03 11:22 ` Emil Renner Berthing
2024-07-03 14:22 ` Yixun Lan
2024-06-27 15:31 ` [PATCH v2 09/10] riscv: dts: spacemit: add Banana Pi BPI-F3 board " Yixun Lan
2024-06-27 15:31 ` [PATCH v2 10/10] riscv: defconfig: enable SpacemiT SoC Yixun Lan
2024-07-01 12:21 ` Conor Dooley
2024-06-27 15:39 ` [PATCH v2 00/10] riscv: add initial support for SpacemiT K1 Conor Dooley
2024-06-27 15:56 ` Yixun Lan
2024-06-28 15:41 ` Rob Herring (Arm)
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