[PATCH v5 00/27] Add support for sam9x7 SoC family

[PATCH v5 00/27] Add support for sam9x7 SoC family

[Varshini Rajendran]

This patch series adds support for the new SoC family - sam9x7.
 - The device tree, configs and drivers are added
 - Clock driver for sam9x7 is added
 - Support for basic peripherals is added
 - Target board SAM9X75 Curiosity is added

 Changes in v5:
 --------------

 - Addressed all the review comments in the patches
 - Picked up all Acked-by and Reviewed-by tags
 - Dropped applied patches from the series
 - Addressed the ABI breakage reported in the IRQ patch
 - All the specific changes are captured in the corresponding patches

 Changes in v4:
 --------------

 - Addressed all the review comments in the patches
 - Picked up all Acked-by and Reviewed-by tags
 - Dropped applied patches from the series
 - Added pwm node and related dt binding documentation
 - Added support for exporting some clocks to DT
 - Dropped USB related patches and changes. See NOTE.
 - All the specific changes are captured in the corresponding patches

 NOTE: Owing to the discussion here
 https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=B7t+KS_kOinxaRx38=WxA@mail.gmail.com/
 the USB related changes are dropped from this series in order to enable
 us to work on the mentioned issues before adding new compatibles as
 said. The issues/warnings will be addressed in subsequent patches.
 After which the USB related support for sam9x7 SoCs will be added. Hope
 this works out fine.

 Changes in v3:
 --------------

 - Fixed the DT documentation errors pointed out in v2.
 - Dropped Acked-by tag in tcb DT doc patch as it had to be adapted
   according to sam9x7 correctly.
 - Picked by the previously missed tags.
 - Dropped this patch "dt-bindings: usb: generic-ehci: Document clock-names
   property" as the warning was not found while validating DT-schema for
   at91-sam9x75_curiosity.dtb.
 - Dropped redundant words in the commit message.
 - Fixed the CHECK_DTBS warnings validated against
   at91-sam9x75_curiosity.dtb.
 - Renamed dt nodes according to naming convention.
 - Dropped unwanted status property in dts.
 - Removed nodes that are not in use from the board dts.
 - Removed spi DT doc patch from the series as it was already applied
   and a fix patch was applied subsequently. Added a patch to remove the
   compatible to adapt sam9x7.
 - Added sam9x7 compatibles in usb dt documentation.


 Changes in v2:
 --------------

 - Added sam9x7 specific compatibles in DT with fallbacks
 - Documented all the newly added DT compatible strings
 - Added device tree for the target board sam9x75 curiosity and
   documented the same in the DT bindings documentation
 - Removed the dt nodes that are not supported at the moment
 - Removed the configs added by previous version that are not supported
   at the moment
 - Fixed all the corrections in the commit message
 - Changed all the instances of copyright year to 2023
 - Added sam9x7 flag in PIT64B configuration
 - Moved macro definitions to header file
 - Added another divider in mck characteristics in the pmc driver
 - Fixed the memory leak in the pmc driver
 - Dropped patches that are no longer needed
 - Picked up Acked-by and Reviewed-by tags


Varshini Rajendran (27):
  dt-bindings: atmel-sysreg: add sam9x7
  dt-bindings: atmel-ssc: add microchip,sam9x7-ssc
  dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.
  ARM: at91: pm: add support for sam9x7 SoC family
  ARM: at91: pm: add sam9x7 SoC init config
  ARM: at91: add support in SoC driver for new sam9x7
  dt-bindings: clocks: atmel,at91sam9x5-sckc
  dt-bindings: clocks: atmel,at91rm9200-pmc
  clk: at91: clk-sam9x60-pll: re-factor to support individual core freq
    outputs
  clk: at91: sam9x7: add support for HW PLL freq dividers
  clk: at91: sama7g5: move mux table macros to header file
  dt-bindings: clock: at91: Allow PLLs to be exported and referenced in
    DT
  clk: at91: sam9x7: add sam9x7 pmc driver
  dt-bindings: interrupt-controller: Add support for sam9x7 aic
  dt-bindings: interrupt-controller: Document the property
    microchip,nr-irqs
  irqchip/atmel-aic5: Add support to get nr_irqs from DT for sam9x60 &
    sam9x7
  ARM: dts: at91: sam9x60: Add nirqs property in the dt node
  power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7
  power: reset: at91-reset: add reset support for sam9x7 SoC
  power: reset: at91-reset: add sdhwc support for sam9x7 SoC
  dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7
  dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7
  ARM: at91: Kconfig: add config flag for SAM9X7 SoC
  ARM: configs: at91: enable config flags for sam9x7 SoC family
  ARM: dts: at91: sam9x7: add device tree for SoC
  dt-bindings: arm: add sam9x75 curiosity board
  ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

 .../devicetree/bindings/arm/atmel-at91.yaml   |    6 +
 .../devicetree/bindings/arm/atmel-sysregs.txt |    7 +-
 .../bindings/clock/atmel,at91rm9200-pmc.yaml  |    2 +
 .../bindings/clock/atmel,at91sam9x5-sckc.yaml |    4 +-
 .../interrupt-controller/atmel,aic.yaml       |   28 +-
 .../devicetree/bindings/misc/atmel-ssc.txt    |    1 +
 .../power/reset/atmel,sama5d2-shdwc.yaml      |    3 +
 .../reset/atmel,at91sam9260-reset.yaml        |    4 +
 .../bindings/serial/atmel,at91-usart.yaml     |    9 +-
 arch/arm/boot/dts/microchip/Makefile          |    3 +
 .../dts/microchip/at91-sam9x75_curiosity.dts  |  312 +++++
 arch/arm/boot/dts/microchip/sam9x60.dtsi      |    1 +
 arch/arm/boot/dts/microchip/sam9x7.dtsi       | 1226 +++++++++++++++++
 arch/arm/configs/at91_dt_defconfig            |    1 +
 arch/arm/mach-at91/Kconfig                    |   22 +-
 arch/arm/mach-at91/Makefile                   |    1 +
 arch/arm/mach-at91/generic.h                  |    2 +
 arch/arm/mach-at91/pm.c                       |   29 +
 arch/arm/mach-at91/sam9x7.c                   |   33 +
 drivers/clk/at91/Makefile                     |    1 +
 drivers/clk/at91/clk-sam9x60-pll.c            |   42 +-
 drivers/clk/at91/pmc.h                        |   18 +
 drivers/clk/at91/sam9x60.c                    |    7 +
 drivers/clk/at91/sam9x7.c                     |  946 +++++++++++++
 drivers/clk/at91/sama7g5.c                    |   42 +-
 drivers/irqchip/irq-atmel-aic5.c              |    8 +-
 drivers/power/reset/Kconfig                   |    4 +-
 drivers/power/reset/at91-sama5d2_shdwc.c      |    1 +
 drivers/soc/atmel/soc.c                       |   23 +
 drivers/soc/atmel/soc.h                       |    9 +
 include/dt-bindings/clock/at91.h              |    4 +
 31 files changed, 2750 insertions(+), 49 deletions(-)
 create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
 create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi
 create mode 100644 arch/arm/mach-at91/sam9x7.c
 create mode 100644 drivers/clk/at91/sam9x7.c

-- 
2.25.1

[PATCH v5 01/27] dt-bindings: atmel-sysreg: add sam9x7

[Varshini Rajendran]

Add RAM controller & SFR DT bindings.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 67a66bf74895..1339298203c6 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -11,7 +11,8 @@ PIT Timer required properties:
   shared across all System Controller members.
 
 PIT64B Timer required properties:
-- compatible: Should be "microchip,sam9x60-pit64b"
+- compatible: Should be "microchip,sam9x60-pit64b" or
+			"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt for PIT64B timer
 - clocks: Should contain the available clock sources for PIT64B timer.
@@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties:
 			"atmel,at91sam9g45-ddramc",
 			"atmel,sama5d3-ddramc",
 			"microchip,sam9x60-ddramc",
-			"microchip,sama7g5-uddrc"
+			"microchip,sama7g5-uddrc",
+			"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
 - reg: Should contain registers location and length
 
 Examples:
@@ -63,6 +65,7 @@ required properties:
 	"atmel,<chip>-sfrbu", "syscon"
   <chip> can be "sama5d3", "sama5d4" or "sama5d2".
   It also can be "microchip,sam9x60-sfr", "syscon".
+  It also can be "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon".
 - reg: Should contain registers location and length
 
 	sfr@f0038000 {
-- 
2.25.1

[PATCH v5 02/27] dt-bindings: atmel-ssc: add microchip,sam9x7-ssc

[Varshini Rajendran]

Add microchip,sam9x7-ssc to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
index f9fb412642fe..894875826de9 100644
--- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt
+++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
+	       or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"
 	- atmel,at91rm9200-ssc: support pdc transfer
 	- atmel,at91sam9g45-ssc: support dma transfer
 - reg: Should contain SSC registers location and length
-- 
2.25.1

[PATCH v5 03/27] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Varshini Rajendran]

Add sam9x7 compatible to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Corrected the order of bindings.
- sam9x60 bindings in the dts and dt documentation in future series.
---
 .../devicetree/bindings/serial/atmel,at91-usart.yaml     | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
index eb2992a447d7..f466c38518c4 100644
--- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
+++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
@@ -23,13 +23,20 @@ properties:
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart
       - items:
-          - const: microchip,sam9x60-usart
+          - enum:
+              - microchip,sam9x60-usart
+              - microchip,sam9x7-usart
           - const: atmel,at91sam9260-usart
       - items:
           - const: microchip,sam9x60-dbgu
           - const: microchip,sam9x60-usart
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart
+      - items:
+          - const: microchip,sam9x7-dbgu
+          - const: atmel,at91sam9260-dbgu
+          - const: microchip,sam9x7-usart
+          - const: atmel,at91sam9260-usart
 
   reg:
     maxItems: 1
-- 
2.25.1

Re: [PATCH v5 03/27] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1806 bytes --]

On Wed, Jul 03, 2024 at 03:56:40PM +0530, Varshini Rajendran wrote:
> Add sam9x7 compatible to DT bindings documentation.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v5:
> - Corrected the order of bindings.
> - sam9x60 bindings in the dts and dt documentation in future series.
> ---
>  .../devicetree/bindings/serial/atmel,at91-usart.yaml     | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> index eb2992a447d7..f466c38518c4 100644
> --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> @@ -23,13 +23,20 @@ properties:
>            - const: atmel,at91sam9260-dbgu
>            - const: atmel,at91sam9260-usart
>        - items:
> -          - const: microchip,sam9x60-usart
> +          - enum:
> +              - microchip,sam9x60-usart
> +              - microchip,sam9x7-usart
>            - const: atmel,at91sam9260-usart
>        - items:
>            - const: microchip,sam9x60-dbgu
>            - const: microchip,sam9x60-usart
>            - const: atmel,at91sam9260-dbgu
>            - const: atmel,at91sam9260-usart
> +      - items:
> +          - const: microchip,sam9x7-dbgu
> +          - const: atmel,at91sam9260-dbgu

> +          - const: microchip,sam9x7-usart

I still think that this particular compatible shouldn't be here, but I
did say I would accept this version.
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> +          - const: atmel,at91sam9260-usart
>  
>    reg:
>      maxItems: 1
> -- 
> 2.25.1
> 

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[PATCH v5 07/27] dt-bindings: clocks: atmel,at91sam9x5-sckc

[Varshini Rajendran]

Add bindings for SAM9X7's slow clock controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v5:
- Changed subject according to suggestion.
- Alphanumerically sorted entries.
- Updated Acked-by tag.
---
 .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
index 7be29877e6d2..c2283cd07f05 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
@@ -18,7 +18,9 @@ properties:
           - atmel,sama5d4-sckc
           - microchip,sam9x60-sckc
       - items:
-          - const: microchip,sama7g5-sckc
+          - enum:
+              - microchip,sam9x7-sckc
+              - microchip,sama7g5-sckc
           - const: microchip,sam9x60-sckc
 
   reg:
-- 
2.25.1

Re: [PATCH v5 07/27] dt-bindings: clocks: atmel,at91sam9x5-sckc

[claudiu beznea]

Hi, Varshini,

In my comment from v4 I meant to say:

dt-bindings: clk: at91: add sam9x7 -> dt-bindings: clocks: at91sam9x5-sckc:
add sam9x7

Suggestion was:
s/dt-bindings: clk: at91/dt-bindings: clocks: at91sam9x5-sckc

Anyway, I'll adjust it when applying. No need to resent just for this.

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Add bindings for SAM9X7's slow clock controller.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Other than the title:

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Changed subject according to suggestion.
> - Alphanumerically sorted entries.
> - Updated Acked-by tag.
> ---
>  .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> index 7be29877e6d2..c2283cd07f05 100644
> --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> @@ -18,7 +18,9 @@ properties:
>            - atmel,sama5d4-sckc
>            - microchip,sam9x60-sckc
>        - items:
> -          - const: microchip,sama7g5-sckc
> +          - enum:
> +              - microchip,sam9x7-sckc
> +              - microchip,sama7g5-sckc
>            - const: microchip,sam9x60-sckc
>  
>    reg:

[PATCH v5 08/27] dt-bindings: clocks: atmel,at91rm9200-pmc

[Varshini Rajendran]

Add bindings for SAM9X7's pmc.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v5:
- Changed subject according to suggestion.
- Alphanumerically sorted entries.
- Updated Acked-by tag.
---
 .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml         | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
index c1bdcd9058ed..c9eb60776b4d 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
@@ -42,6 +42,7 @@ properties:
               - atmel,sama5d3-pmc
               - atmel,sama5d4-pmc
               - microchip,sam9x60-pmc
+              - microchip,sam9x7-pmc
               - microchip,sama7g5-pmc
           - const: syscon
 
@@ -88,6 +89,7 @@ allOf:
           contains:
             enum:
               - microchip,sam9x60-pmc
+              - microchip,sam9x7-pmc
               - microchip,sama7g5-pmc
     then:
       properties:
-- 
2.25.1

Re: [PATCH v5 08/27] dt-bindings: clocks: atmel,at91rm9200-pmc

[claudiu beznea]

Same for this one:

dt-bindings: clocks: at91: add sam9x7 clock controller ->
dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller

I'll adjust it when applying.

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Add bindings for SAM9X7's pmc.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Other than the title:

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Changed subject according to suggestion.
> - Alphanumerically sorted entries.
> - Updated Acked-by tag.
> ---
>  .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml         | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> index c1bdcd9058ed..c9eb60776b4d 100644
> --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> @@ -42,6 +42,7 @@ properties:
>                - atmel,sama5d3-pmc
>                - atmel,sama5d4-pmc
>                - microchip,sam9x60-pmc
> +              - microchip,sam9x7-pmc
>                - microchip,sama7g5-pmc
>            - const: syscon
>  
> @@ -88,6 +89,7 @@ allOf:
>            contains:
>              enum:
>                - microchip,sam9x60-pmc
> +              - microchip,sam9x7-pmc
>                - microchip,sama7g5-pmc
>      then:
>        properties:

[PATCH v5 12/27] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT

[Varshini Rajendran]

Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
clock from phandle in DT for sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v5:
- Updated Acked-by tag.
---
 include/dt-bindings/clock/at91.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index 3e3972a814c1..6ede88c3992d 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -38,6 +38,10 @@
 #define PMC_CPU			(PMC_MAIN + 9)
 #define PMC_MCK1		(PMC_MAIN + 10)
 
+/* SAM9X7 */
+#define PMC_PLLADIV2		(PMC_MAIN + 11)
+#define PMC_LVDSPLL		(PMC_MAIN + 12)
+
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
 #define AT91_PMC_LOCKA		1		/* PLLA Lock */
-- 
2.25.1

Re: [PATCH v5 12/27] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT

[claudiu beznea]

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
> clock from phandle in DT for sam9x7 SoC family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Updated Acked-by tag.
> ---
>  include/dt-bindings/clock/at91.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
> index 3e3972a814c1..6ede88c3992d 100644
> --- a/include/dt-bindings/clock/at91.h
> +++ b/include/dt-bindings/clock/at91.h
> @@ -38,6 +38,10 @@
>  #define PMC_CPU			(PMC_MAIN + 9)
>  #define PMC_MCK1		(PMC_MAIN + 10)
>  
> +/* SAM9X7 */
> +#define PMC_PLLADIV2		(PMC_MAIN + 11)
> +#define PMC_LVDSPLL		(PMC_MAIN + 12)
> +
>  #ifndef AT91_PMC_MOSCS
>  #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
>  #define AT91_PMC_LOCKA		1		/* PLLA Lock */

[PATCH v5 14/27] dt-bindings: interrupt-controller: Add support for sam9x7 aic

[Varshini Rajendran]

Document the support added for the Advanced interrupt controller(AIC)
chip in the sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Adapted the patch to the new yaml file.
- Removed the Acked-by tag due to the TXT to schema change.
---
 .../bindings/interrupt-controller/atmel,aic.yaml | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
index d4658fe3867c..9c5af9dbcb6e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
@@ -17,12 +17,16 @@ description:
 
 properties:
   compatible:
-    enum:
-      - atmel,at91rm9200-aic
-      - atmel,sama5d2-aic
-      - atmel,sama5d3-aic
-      - atmel,sama5d4-aic
-      - microchip,sam9x60-aic
+    oneOf:
+      - enum:
+          - atmel,at91rm9200-aic
+          - atmel,sama5d2-aic
+          - atmel,sama5d3-aic
+          - atmel,sama5d4-aic
+          - microchip,sam9x60-aic
+      - items:
+          - const: microchip,sam9x7-aic
+          - const: microchip,sam9x60-aic
 
   reg:
     maxItems: 1
-- 
2.25.1

Re: [PATCH v5 14/27] dt-bindings: interrupt-controller: Add support for sam9x7 aic

[Conor Dooley]

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On Wed, Jul 03, 2024 at 03:58:06PM +0530, Varshini Rajendran wrote:
> Document the support added for the Advanced interrupt controller(AIC)
> chip in the sam9x7 SoC family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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[PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Varshini Rajendran]

Add the description and conditions to the device tree documentation
for the property microchip,nr-irqs.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
index 9c5af9dbcb6e..06e5f92e7d53 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
@@ -54,6 +54,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32-array
     description: u32 array of external irqs.
 
+  microchip,nr-irqs:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: u32 array of nr_irqs.
+
 allOf:
   - $ref: /schemas/interrupt-controller.yaml#
   - if:
@@ -71,6 +75,14 @@ allOf:
         atmel,external-irqs:
           minItems: 1
           maxItems: 1
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: microchip,sam9x7-aic
+    then:
+      required:
+        - microchip,nr-irqs
 
 required:
   - compatible
-- 
2.25.1

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Conor Dooley]

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On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> Add the description and conditions to the device tree documentation
> for the property microchip,nr-irqs.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

This needs to be part of patch 14.

> ---
>  .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> index 9c5af9dbcb6e..06e5f92e7d53 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> @@ -54,6 +54,10 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/uint32-array
>      description: u32 array of external irqs.
>  
> +  microchip,nr-irqs:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description: u32 array of nr_irqs.

This makes no sense, did you just copy from above? Why would the number
of irqs be an array? Why can't you determine this from the compatble?

Thanks,
Conor.

> +
>  allOf:
>    - $ref: /schemas/interrupt-controller.yaml#
>    - if:
> @@ -71,6 +75,14 @@ allOf:
>          atmel,external-irqs:
>            minItems: 1
>            maxItems: 1
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: microchip,sam9x7-aic
> +    then:
> +      required:
> +        - microchip,nr-irqs
>  
>  required:
>    - compatible
> -- 
> 2.25.1
> 

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Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Varshini.Rajendran]

On 03/07/24 9:11 pm, Conor Dooley wrote:
> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
>> Add the description and conditions to the device tree documentation
>> for the property microchip,nr-irqs.
>>
>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
> This needs to be part of patch 14.
> 
>> ---
>>   .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>> index 9c5af9dbcb6e..06e5f92e7d53 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>> @@ -54,6 +54,10 @@ properties:
>>       $ref: /schemas/types.yaml#/definitions/uint32-array
>>       description: u32 array of external irqs.
>>   
>> +  microchip,nr-irqs:
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    description: u32 array of nr_irqs.
> This makes no sense, did you just copy from above? Why would the number
> of irqs be an array? Why can't you determine this from the compatble?
> 
Sorry for the bad description. I will correct it in the next version.

For the second part of the question, this change was done as a step to 
resolve having a new compatible while having practically the same IP 
pointed out in the v3 of the series [1]. It is kind of looping back to 
the initial idea now. Even if this is added as a driver data, it 
overrides the expectation from the comment in [1]. Please suggest. I 
also read Rob's concerns on having a device tree property for number of 
irqs.

[1] 
https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/

> Thanks,
> Conor.
> 
>> +
>>   allOf:
>>     - $ref: /schemas/interrupt-controller.yaml#
>>     - if:
>> @@ -71,6 +75,14 @@ allOf:
>>           atmel,external-irqs:
>>             minItems: 1
>>             maxItems: 1
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: microchip,sam9x7-aic
>> +    then:
>> +      required:
>> +        - microchip,nr-irqs
>>   
>>   required:
>>     - compatible
>> -- 
>> 2.25.1
>>

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Nicolas.Ferre]

On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
> On 03/07/24 9:11 pm, Conor Dooley wrote:
>> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
>>> Add the description and conditions to the device tree documentation
>>> for the property microchip,nr-irqs.
>>>
>>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
>> This needs to be part of patch 14.
>>
>>> ---
>>>    .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>>>    1 file changed, 12 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>> index 9c5af9dbcb6e..06e5f92e7d53 100644
>>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>> @@ -54,6 +54,10 @@ properties:
>>>        $ref: /schemas/types.yaml#/definitions/uint32-array
>>>        description: u32 array of external irqs.
>>>    
>>> +  microchip,nr-irqs:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>>> +    description: u32 array of nr_irqs.
>> This makes no sense, did you just copy from above? Why would the number
>> of irqs be an array? Why can't you determine this from the compatble?
>>
> Sorry for the bad description. I will correct it in the next version.
> 
> For the second part of the question, this change was done as a step to
> resolve having a new compatible while having practically the same IP
> pointed out in the v3 of the series [1]. It is kind of looping back to
> the initial idea now. Even if this is added as a driver data, it
> overrides the expectation from the comment in [1]. Please suggest. I

In your v3 patch, indeed you were extracting the number of IRQs from the 
compatibility string (aka, from device tree...). It's my preferred 
solution as well.

So, come back to v3 [1] and address what Conor said in v4 "...having 
specific $soc_aic5_of_init() functions for each SoC seems silly when 
usually only the number of interrupts changes. The number of IRQs could 
be in the match data and you could use aic5_of_init in your 
IRQCHIP_DECLARE directly"

I think that we can convince Marc/Thomas that it's the best option as it 
prevents introducing another non-standard property to the DT, break the 
ABI (and was used happily for years).

Best regards,
   Nicolas

[1]
https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/


> also read Rob's concerns on having a device tree property for number of
> irqs.
> 
> [1]
> https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/
> 
>> Thanks,
>> Conor.
>>
>>> +
>>>    allOf:
>>>      - $ref: /schemas/interrupt-controller.yaml#
>>>      - if:
>>> @@ -71,6 +75,14 @@ allOf:
>>>            atmel,external-irqs:
>>>              minItems: 1
>>>              maxItems: 1
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: microchip,sam9x7-aic
>>> +    then:
>>> +      required:
>>> +        - microchip,nr-irqs
>>>    
>>>    required:
>>>      - compatible
>>> -- 
>>> 2.25.1
>>>
> 

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Nicolas.Ferre]

On 09/07/2024 at 16:06, Nicolas.Ferre@microchip.com wrote:
> On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:

[..]

> I think that we can convince Marc/Thomas that it's the best option as it
> prevents introducing another non-standard property to the DT, break the
> ABI (and was used happily for years).

s/break the/does not break the/

> Best regards,
>     Nicolas
(sorry for the noise)

[..]

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Marc Zyngier]

On Tue, 09 Jul 2024 15:06:29 +0100,
<Nicolas.Ferre@microchip.com> wrote:
> 
> On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
> > On 03/07/24 9:11 pm, Conor Dooley wrote:
> >> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> >>> Add the description and conditions to the device tree documentation
> >>> for the property microchip,nr-irqs.
> >>>
> >>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
> >> This needs to be part of patch 14.
> >>
> >>> ---
> >>>    .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
> >>>    1 file changed, 12 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> >>> index 9c5af9dbcb6e..06e5f92e7d53 100644
> >>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> >>> @@ -54,6 +54,10 @@ properties:
> >>>        $ref: /schemas/types.yaml#/definitions/uint32-array
> >>>        description: u32 array of external irqs.
> >>>    
> >>> +  microchip,nr-irqs:
> >>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> >>> +    description: u32 array of nr_irqs.
> >> This makes no sense, did you just copy from above? Why would the number
> >> of irqs be an array? Why can't you determine this from the compatble?
> >>
> > Sorry for the bad description. I will correct it in the next version.
> > 
> > For the second part of the question, this change was done as a step to
> > resolve having a new compatible while having practically the same IP
> > pointed out in the v3 of the series [1]. It is kind of looping back to
> > the initial idea now. Even if this is added as a driver data, it
> > overrides the expectation from the comment in [1]. Please suggest. I
> 
> In your v3 patch, indeed you were extracting the number of IRQs from the 
> compatibility string (aka, from device tree...). It's my preferred 
> solution as well.
> 
> So, come back to v3 [1] and address what Conor said in v4 "...having 
> specific $soc_aic5_of_init() functions for each SoC seems silly when 
> usually only the number of interrupts changes. The number of IRQs could 
> be in the match data and you could use aic5_of_init in your 
> IRQCHIP_DECLARE directly"
> 
> I think that we can convince Marc/Thomas that it's the best option as it 
> prevents introducing another non-standard property to the DT, break the 
> ABI (and was used happily for years).

In general, the least cruft we add to the DT after the facts, the
better. If the compatible string is good enough to identify the
device, I don't think we need to overthink it, specially as there is
no upside to non-standard properties here -- from what I understand,
the number of available interrupts is a property of the HW, and not
something that can be configured, making it part of the programming
model, just like the layout of registers.

But I'm not in a deciding position anymore, and this is only my
(educated) opinion.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Nicolas Ferre]

Answering to myself (again) and to Conor...

On 09/07/2024 at 16:06, Nicolas.Ferre@microchip.com wrote:
> On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
>> On 03/07/24 9:11 pm, Conor Dooley wrote:
>>> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
>>>> Add the description and conditions to the device tree documentation
>>>> for the property microchip,nr-irqs.
>>>>
>>>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
>>> This needs to be part of patch 14.
>>>
>>>> ---
>>>>     .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>>>>     1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>>> index 9c5af9dbcb6e..06e5f92e7d53 100644
>>>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>>> @@ -54,6 +54,10 @@ properties:
>>>>         $ref: /schemas/types.yaml#/definitions/uint32-array
>>>>         description: u32 array of external irqs.
>>>>     
>>>> +  microchip,nr-irqs:
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>>>> +    description: u32 array of nr_irqs.
>>> This makes no sense, did you just copy from above? Why would the number
>>> of irqs be an array? Why can't you determine this from the compatble?
>>>
>> Sorry for the bad description. I will correct it in the next version.
>>
>> For the second part of the question, this change was done as a step to
>> resolve having a new compatible while having practically the same IP
>> pointed out in the v3 of the series [1]. It is kind of looping back to
>> the initial idea now. Even if this is added as a driver data, it
>> overrides the expectation from the comment in [1]. Please suggest. I
> 
> In your v3 patch, indeed you were extracting the number of IRQs from the
> compatibility string (aka, from device tree...). It's my preferred
> solution as well.
> 
> So, come back to v3 [1] and address what Conor said in v4 "...having
> specific $soc_aic5_of_init() functions for each SoC seems silly when
> usually only the number of interrupts changes. The number of IRQs could
> be in the match data and you could use aic5_of_init in your
> IRQCHIP_DECLARE directly"

Well, after a brief talk with Varshini and a review of the code, I'm not 
so sure it's worth re-writing this part anymore Conor...
It'll need changing 3-4 files (2 drivers and the "common" .h/.c files, 
because of the type change of ".data"); handling the special case of 
sama5d2 (smr_cache thing) and touching lot more code than what is done 
in v3 of this patch series.

Original design was probably not optimal, but well, it's simple, 
understandable and except if there is a big benefit in moving, I would 
prefer to keep it like this.
If you agree, we can ask Varshini to re-post a separated IRQ-focused 
series for handling sam9x75 changes.

Best regards,
   Nicolas

> I think that we can convince Marc/Thomas that it's the best option as it
> prevents introducing another non-standard property to the DT, does not break
> the ABI (and was used happily for years).
> 
> Best regards,
>     Nicolas
> 
> [1]
> https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/
> 
> 
>> also read Rob's concerns on having a device tree property for number of
>> irqs.
>>
>> [1]
>> https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/
>>
>>> Thanks,
>>> Conor.
>>>
>>>> +
>>>>     allOf:
>>>>       - $ref: /schemas/interrupt-controller.yaml#
>>>>       - if:
>>>> @@ -71,6 +75,14 @@ allOf:
>>>>             atmel,external-irqs:
>>>>               minItems: 1
>>>>               maxItems: 1
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            const: microchip,sam9x7-aic
>>>> +    then:
>>>> +      required:
>>>> +        - microchip,nr-irqs
>>>>     
>>>>     required:
>>>>       - compatible
>>>> -- 
>>>> 2.25.1
>>>>
>>
> 

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3564 bytes --]

On Thu, Jul 11, 2024 at 02:42:01PM +0200, Nicolas Ferre wrote:
> Answering to myself (again) and to Conor...
> 
> On 09/07/2024 at 16:06, Nicolas.Ferre@microchip.com wrote:
> > On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
> > > On 03/07/24 9:11 pm, Conor Dooley wrote:
> > > > On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> > > > > Add the description and conditions to the device tree documentation
> > > > > for the property microchip,nr-irqs.
> > > > > 
> > > > > Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
> > > > This needs to be part of patch 14.
> > > > 
> > > > > ---
> > > > >     .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
> > > > >     1 file changed, 12 insertions(+)
> > > > > 
> > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> > > > > index 9c5af9dbcb6e..06e5f92e7d53 100644
> > > > > --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> > > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> > > > > @@ -54,6 +54,10 @@ properties:
> > > > >         $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > >         description: u32 array of external irqs.
> > > > > +  microchip,nr-irqs:
> > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > +    description: u32 array of nr_irqs.
> > > > This makes no sense, did you just copy from above? Why would the number
> > > > of irqs be an array? Why can't you determine this from the compatble?
> > > > 
> > > Sorry for the bad description. I will correct it in the next version.
> > > 
> > > For the second part of the question, this change was done as a step to
> > > resolve having a new compatible while having practically the same IP
> > > pointed out in the v3 of the series [1]. It is kind of looping back to
> > > the initial idea now. Even if this is added as a driver data, it
> > > overrides the expectation from the comment in [1]. Please suggest. I
> > 
> > In your v3 patch, indeed you were extracting the number of IRQs from the
> > compatibility string (aka, from device tree...). It's my preferred
> > solution as well.
> > 
> > So, come back to v3 [1] and address what Conor said in v4 "...having
> > specific $soc_aic5_of_init() functions for each SoC seems silly when
> > usually only the number of interrupts changes. The number of IRQs could
> > be in the match data and you could use aic5_of_init in your
> > IRQCHIP_DECLARE directly"
> 
> Well, after a brief talk with Varshini and a review of the code, I'm not so
> sure it's worth re-writing this part anymore Conor...
> It'll need changing 3-4 files (2 drivers and the "common" .h/.c files,
> because of the type change of ".data"); handling the special case of sama5d2
> (smr_cache thing) and touching lot more code than what is done in v3 of this
> patch series.
> 
> Original design was probably not optimal, but well, it's simple,
> understandable and except if there is a big benefit in moving, I would
> prefer to keep it like this.
> If you agree, we can ask Varshini to re-post a separated IRQ-focused series
> for handling sam9x75 changes.

I dunno, it's up to the folks that care about the driver whether they
want to do restructuring, not me. The nr-irqs property stays NAKed though,
since the information is determinable from the compatible.

Thanks,
Conor.

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Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Rob Herring]

On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> Add the description and conditions to the device tree documentation
> for the property microchip,nr-irqs.

Why?

Of *all* the other interrupt controller bindings, do you see a property 
for number of interrupts? No (well, maybe a few slipped in). You 
shouldn't need one either.

Rob

[PATCH v5 17/27] ARM: dts: at91: sam9x60: Add nirqs property in the dt node

[Varshini Rajendran]

Add the microchip,nr-irqs property in the DT node and set the value
for the driver to get the value from the DT instead of a hardcoded macro.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Separated the patch from the DT bindings.
---
 arch/arm/boot/dts/microchip/sam9x60.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index 291540e5d81e..7dbe34b7587a 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 {
 				interrupt-controller;
 				reg = <0xfffff100 0x100>;
 				atmel,external-irqs = <31>;
+				microchip,nr-irqs = <50>;
 			};
 
 			dbgu: serial@fffff200 {
-- 
2.25.1

[PATCH v5 21/27] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7

[Varshini Rajendran]

Add documentation for SAM9X7 reset controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml    | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
index 98465d26949e..c3b33bbc7319 100644
--- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
@@ -26,6 +26,10 @@ properties:
       - items:
           - const: atmel,sama5d3-rstc
           - const: atmel,at91sam9g45-rstc
+      - items:
+          - enum:
+              - microchip,sam9x7-rstc
+          - const: microchip,sam9x60-rstc
 
   reg:
     minItems: 1
-- 
2.25.1

[PATCH v5 22/27] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7

[Varshini Rajendran]

Add shutdown controller DT bindings.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml   | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
index 8c58e12cdb60..0735ceb7c103 100644
--- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
+++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
@@ -22,6 +22,9 @@ properties:
       - enum:
           - atmel,sama5d2-shdwc
           - microchip,sam9x60-shdwc
+      - items:
+          - const: microchip,sam9x7-shdwc
+          - const: microchip,sam9x60-shdwc
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH v5 25/27] ARM: dts: at91: sam9x7: add device tree for SoC

[Varshini Rajendran]

Add device tree file for SAM9X7 SoC family.

Co-developed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changed in v5:
- Sorted node properties according dts coding style.
- Removed space before pwn status.
- Fixed DT schema warnings related to usart.
- Aligned <> braces.
- Changed spaces to tabs.
- Changed node names to generic names.
- Corrected the typo in gpbr compatible.
---
 arch/arm/boot/dts/microchip/sam9x7.dtsi | 1226 +++++++++++++++++++++++
 1 file changed, 1226 insertions(+)
 create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi

diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi
new file mode 100644
index 000000000000..0e3fb94f40b6
--- /dev/null
+++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi
@@ -0,0 +1,1226 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+	model = "Microchip SAM9X7 SoC";
+	compatible = "microchip,sam9x7";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,arm926ej-s";
+			reg = <0>;
+			device_type = "cpu";
+		};
+	};
+
+	clocks {
+		slow_xtal: clock-slowxtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: clock-mainxtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	sram: sram@300000 {
+		compatible = "mmio-sram";
+		reg = <0x300000 0x10000>;
+		ranges = <0 0x300000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sdmmc0: mmc@80000000 {
+			compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
+			reg = <0x80000000 0x300>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		sdmmc1: mmc@90000000 {
+			compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+	};
+
+	apb {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flx4: flexcom@f0000000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf0000000 0x200>;
+			ranges = <0x0 0xf0000000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+			status = "disabled";
+
+			uart4: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(8))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(9))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi4: spi@400 {
+				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(8))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(9))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(8))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(9))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx5: flexcom@f0004000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf0004000 0x200>;
+			ranges = <0x0 0xf0004000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+			status = "disabled";
+
+			uart5: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(10))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(11))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi5: spi@400 {
+				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(10))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(11))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(10))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(11))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		dma0: dma-controller@f0008000 {
+			compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma";
+			reg = <0xf0008000 0x1000>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+			#dma-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+			clock-names = "dma_clk";
+			status = "disabled";
+		};
+
+		ssc: ssc@f0010000 {
+			compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc";
+			reg = <0xf0010000 0x4000>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+			clock-names = "pclk";
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(38))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(39))>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		i2s: i2s@f001c000 {
+			compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc";
+			reg = <0xf001c000 0x100>;
+			interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+			clock-names = "pclk", "gclk";
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(36))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(37))>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		flx11: flexcom@f0020000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf0020000 0x200>;
+			ranges = <0x0 0xf0020000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+			status = "disabled";
+
+			uart11: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(22))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(23))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(22))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(23))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx12: flexcom@f0024000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf0024000 0x200>;
+			ranges = <0x0 0xf0024000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+			status = "disabled";
+
+			uart12: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(24))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(25))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c12: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(24))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(25))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		pit64b0: timer@f0028000 {
+			compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
+			reg = <0xf0028000 0x100>;
+			interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+			clock-names = "pclk", "gclk";
+		};
+
+		sha: crypto@f002c000 {
+			compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha";
+			reg = <0xf002c000 0x100>;
+			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+			clock-names = "sha_clk";
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(34))>;
+			dma-names = "tx";
+		};
+
+		trng: rng@f0030000 {
+			compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng";
+			reg = <0xf0030000 0x100>;
+			interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+			status = "disabled";
+		};
+
+		aes: crypto@f0034000 {
+			compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes";
+			reg = <0xf0034000 0x100>;
+			interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+			clock-names = "aes_clk";
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(32))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(33))>;
+			dma-names = "tx", "rx";
+		};
+
+		tdes: crypto@f0038000 {
+			compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes";
+			reg = <0xf0038000 0x100>;
+			interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+			clock-names = "tdes_clk";
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(31))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(30))>;
+			dma-names = "tx", "rx";
+		};
+
+		classd: sound@f003c000 {
+			compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd";
+			reg = <0xf003c000 0x100>;
+			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+			clock-names = "pclk", "gclk";
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(35))>;
+			dma-names = "tx";
+			status = "disabled";
+		};
+
+		pit64b1: timer@f0040000 {
+			compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
+			reg = <0xf0040000 0x100>;
+			interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
+			clock-names = "pclk", "gclk";
+		};
+
+		can0: can@f8000000 {
+			compatible = "bosch,m_can";
+			reg = <0xf8000000 0x100>, <0x300000 0x7800>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <68 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
+			assigned-clock-rates = <480000000>, <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can1: can@f8004000 {
+			compatible = "bosch,m_can";
+			reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <69 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
+			assigned-clock-rates = <480000000>, <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		tcb: timer@f8008000 {
+			compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon";
+			reg = <0xf8008000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>;
+			clock-names = "t0_clk", "gclk", "slow_clk";
+			status = "disabled";
+		};
+
+		flx6: flexcom@f8010000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8010000 0x200>;
+			ranges = <0x0 0xf8010000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+			status = "disabled";
+
+			uart6: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(12))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(13))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c6: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(12))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(13))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx7: flexcom@f8014000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8014000 0x200>;
+			ranges = <0x0 0xf8014000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+			status = "disabled";
+
+			uart7: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(14))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(15))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(14))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(15))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx8: flexcom@f8018000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8018000 0x200>;
+			ranges = <0x0 0xf8018000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+			status = "disabled";
+
+			uart8: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(16))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(17))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(16))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(17))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx0: flexcom@f801c000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf801c000 0x200>;
+			ranges = <0x0 0xf801c000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+			status = "disabled";
+
+			uart0: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(0))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(1))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi0: spi@400 {
+				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(0))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(1))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(0))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(1))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx1: flexcom@f8020000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8020000 0x200>;
+			ranges = <0x0 0xf8020000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+			status = "disabled";
+
+			uart1: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(2))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(3))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi1: spi@400 {
+				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(2))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(3))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(2))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(3))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx2: flexcom@f8024000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8024000 0x200>;
+			ranges = <0x0 0xf8024000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+			status = "disabled";
+
+			uart2: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(4))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(5))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi2: spi@400 {
+				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(4))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(5))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(4))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(5))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx3: flexcom@f8028000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8028000 0x200>;
+			ranges = <0x0 0xf8028000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+			status = "disabled";
+
+			uart3: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(6))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(7))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi3: spi@400 {
+				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(6))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(7))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(6))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(7))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		gmac: ethernet@f802c000 {
+			compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem";
+			reg = <0xf802c000 0x1000>;
+			interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 0 */
+				     <60 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 1 */
+				     <61 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 2 */
+				     <62 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 3 */
+				     <63 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 4 */
+				     <64 IRQ_TYPE_LEVEL_HIGH 3>;	/* Queue 5 */
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>;
+			clock-names = "hclk", "pclk", "tx_clk", "tsu_clk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 67>;
+			status = "disabled";
+		};
+
+		pwm0: pwm@f8034000 {
+			compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm";
+			reg = <0xf8034000 0x300>;
+			interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		flx9: flexcom@f8040000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8040000 0x200>;
+			ranges = <0x0 0xf8040000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+			status = "disabled";
+
+			uart9: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(18))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(19))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(18))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(19))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx10: flexcom@f8044000 {
+			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xf8044000 0x200>;
+			ranges = <0x0 0xf8044000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+			status = "disabled";
+
+			uart10: serial@200 {
+				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(20))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(21))>;
+				dma-names = "tx", "rx";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@600 {
+				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(20))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(21))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		sfr: sfr@f8050000 {
+			compatible = "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon";
+			reg = <0xf8050000 0x100>;
+		};
+
+		matrix: matrix@ffffde00 {
+			compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon";
+			reg = <0xffffde00 0x200>;
+		};
+
+		pmecc: ecc-engine@ffffe000 {
+			compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc";
+			reg = <0xffffe000 0x300>, <0xffffe600 0x100>;
+		};
+
+		mpddrc: mpddrc@ffffe800 {
+			compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc";
+			reg = <0xffffe800 0x200>;
+			clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+			clock-names = "ddrck", "mpddr";
+		};
+
+		smc: smc@ffffea00 {
+			compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon";
+			reg = <0xffffea00 0x100>;
+		};
+
+		aic: interrupt-controller@fffff100 {
+			compatible = "microchip,sam9x7-aic", "microchip,sam9x60-aic";
+			reg = <0xfffff100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			atmel,external-irqs = <31>;
+			microchip,nr-irqs = <70>;
+		};
+
+		dbgu: serial@fffff200 {
+			compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
+			reg = <0xfffff200 0x200>;
+			interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+			clock-names = "usart";
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(28))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(29))>;
+			dma-names = "tx", "rx";
+			atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@fffff400 {
+			compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd";
+			ranges = <0xfffff400 0xfffff400 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */
+			atmel,mux-mask = <
+					 /*  A		B	   C	      D	  */
+					 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000	/* pioA */
+					 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000	/* pioB */
+					 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000	/* pioC */
+					 0x00003fff 0x00003fe0 0x0000003f 0x00000000	/* pioD */
+					 >;
+
+			pioA: gpio@fffff400 {
+				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffff400 0x200>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				#gpio-cells = <2>;
+				gpio-controller;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+			};
+
+			pioB: gpio@fffff600 {
+				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffff600 0x200>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				#gpio-cells = <2>;
+				gpio-controller;
+				#gpio-lines = <26>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+			};
+
+			pioC: gpio@fffff800 {
+				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffff800 0x200>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				#gpio-cells = <2>;
+				gpio-controller;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+			};
+
+			pioD: gpio@fffffa00 {
+				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffffa00 0x200>;
+				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				#gpio-cells = <2>;
+				gpio-controller;
+				#gpio-lines = <22>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+			};
+		};
+
+		pmc: clock-controller@fffffc00 {
+			compatible = "microchip,sam9x7-pmc", "syscon";
+			reg = <0xfffffc00 0x200>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			#clock-cells = <2>;
+			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+			clock-names = "td_slck", "md_slck", "main_xtal";
+		};
+
+		reset_controller: reset-controller@fffffe00 {
+			compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc";
+			reg = <0xfffffe00 0x10>;
+			clocks = <&clk32k 0>;
+		};
+
+		poweroff: poweroff@fffffe10 {
+			compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc";
+			reg = <0xfffffe10 0x10>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk32k 0>;
+			atmel,wakeup-rtc-timer;
+			atmel,wakeup-rtt-timer;
+			status = "disabled";
+		};
+
+		rtt: rtc@fffffe20 {
+			compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt";
+			reg = <0xfffffe20 0x20>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&clk32k 0>;
+		};
+
+		clk32k: clock-controller@fffffe50 {
+			compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc";
+			reg = <0xfffffe50 0x4>;
+			clocks = <&slow_xtal>;
+			#clock-cells = <1>;
+		};
+
+		gpbr: syscon@fffffe60 {
+			compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+			reg = <0xfffffe60 0x10>;
+		};
+
+		rtc: rtc@fffffea8 {
+			compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc";
+			reg = <0xfffffea8 0x100>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&clk32k 0>;
+		};
+
+		watchdog: watchdog@ffffff80 {
+			compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt";
+			reg = <0xffffff80 0x24>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.25.1

Re: [PATCH v5 25/27] ARM: dts: at91: sam9x7: add device tree for SoC

[claudiu beznea]

Hi, Varshini,

On 03.07.2024 13:29, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family.
> 
> Co-developed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changed in v5:
> - Sorted node properties according dts coding style.
> - Removed space before pwn status.
> - Fixed DT schema warnings related to usart.
> - Aligned <> braces.
> - Changed spaces to tabs.
> - Changed node names to generic names.
> - Corrected the typo in gpbr compatible.
> ---
>  arch/arm/boot/dts/microchip/sam9x7.dtsi | 1226 +++++++++++++++++++++++
>  1 file changed, 1226 insertions(+)
>  create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi
> 
> diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi
> new file mode 100644
> index 000000000000..0e3fb94f40b6
> --- /dev/null
> +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi
> @@ -0,0 +1,1226 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/mfd/at91-usart.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +
> +/ {
> +	model = "Microchip SAM9X7 SoC";
> +	compatible = "microchip,sam9x7";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,arm926ej-s";
> +			reg = <0>;
> +			device_type = "cpu";
> +		};
> +	};
> +
> +	clocks {
> +		slow_xtal: clock-slowxtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: clock-mainxtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x300000 0x10000>;
> +		ranges = <0 0x300000 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		ranges;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		sdmmc0: mmc@80000000 {
> +			compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: mmc@90000000 {
> +			compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	apb {
> +		compatible = "simple-bus";
> +		ranges;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		flx4: flexcom@f0000000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf0000000 0x200>;
> +			ranges = <0x0 0xf0000000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +			status = "disabled";
> +
> +			uart4: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;

According to dts coding style that vendor specific properties goes at the
end. I'll adjust it when applying, no need to resend for this. Valid for
all the uart flexcom nodes.

> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi4: spi@400 {
> +				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx5: flexcom@f0004000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf0004000 0x200>;
> +			ranges = <0x0 0xf0004000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +			status = "disabled";
> +
> +			uart5: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@400 {
> +				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c5: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		dma0: dma-controller@f0008000 {
> +			compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma";
> +			reg = <0xf0008000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#dma-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +			clock-names = "dma_clk";
> +			status = "disabled";
> +		};
> +
> +		ssc: ssc@f0010000 {
> +			compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc";
> +			reg = <0xf0010000 0x4000>;
> +			interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +			clock-names = "pclk";
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(38))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(39))>;
> +			dma-names = "tx", "rx";
> +			status = "disabled";
> +		};
> +
> +		i2s: i2s@f001c000 {
> +			compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc";
> +			reg = <0xf001c000 0x100>;
> +			interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
> +			clock-names = "pclk", "gclk";
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(36))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(37))>;
> +			dma-names = "tx", "rx";
> +			status = "disabled";
> +		};
> +
> +		flx11: flexcom@f0020000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf0020000 0x200>;
> +			ranges = <0x0 0xf0020000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +			status = "disabled";
> +
> +			uart11: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c11: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx12: flexcom@f0024000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf0024000 0x200>;
> +			ranges = <0x0 0xf0024000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +			status = "disabled";
> +
> +			uart12: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c12: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		pit64b0: timer@f0028000 {
> +			compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
> +			reg = <0xf0028000 0x100>;
> +			interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
> +			clock-names = "pclk", "gclk";
> +		};
> +
> +		sha: crypto@f002c000 {
> +			compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha";
> +			reg = <0xf002c000 0x100>;
> +			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +			clock-names = "sha_clk";
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(34))>;
> +			dma-names = "tx";
> +		};
> +
> +		trng: rng@f0030000 {
> +			compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng";
> +			reg = <0xf0030000 0x100>;
> +			interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +			status = "disabled";
> +		};
> +
> +		aes: crypto@f0034000 {
> +			compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes";
> +			reg = <0xf0034000 0x100>;
> +			interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +			clock-names = "aes_clk";
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(32))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(33))>;
> +			dma-names = "tx", "rx";
> +		};
> +
> +		tdes: crypto@f0038000 {
> +			compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes";
> +			reg = <0xf0038000 0x100>;
> +			interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
> +			clock-names = "tdes_clk";
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(31))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(30))>;
> +			dma-names = "tx", "rx";
> +		};
> +
> +		classd: sound@f003c000 {
> +			compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd";
> +			reg = <0xf003c000 0x100>;
> +			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
> +			clock-names = "pclk", "gclk";
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(35))>;
> +			dma-names = "tx";
> +			status = "disabled";
> +		};
> +
> +		pit64b1: timer@f0040000 {
> +			compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
> +			reg = <0xf0040000 0x100>;
> +			interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
> +			clock-names = "pclk", "gclk";
> +		};
> +
> +		can0: can@f8000000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xf8000000 0x100>, <0x300000 0x7800>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <68 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
> +			assigned-clock-rates = <480000000>, <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can1: can@f8004000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <69 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
> +			assigned-clock-rates = <480000000>, <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		tcb: timer@f8008000 {
> +			compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon";
> +			reg = <0xf8008000 0x100>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>;
> +			clock-names = "t0_clk", "gclk", "slow_clk";
> +			status = "disabled";
> +		};
> +
> +		flx6: flexcom@f8010000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8010000 0x200>;
> +			ranges = <0x0 0xf8010000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +			status = "disabled";
> +
> +			uart6: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(12))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(13))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c6: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(12))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(13))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx7: flexcom@f8014000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8014000 0x200>;
> +			ranges = <0x0 0xf8014000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +			status = "disabled";
> +
> +			uart7: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(14))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(15))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c7: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(14))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(15))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx8: flexcom@f8018000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8018000 0x200>;
> +			ranges = <0x0 0xf8018000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +			status = "disabled";
> +
> +			uart8: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(16))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(17))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c8: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(16))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(17))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx0: flexcom@f801c000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf801c000 0x200>;
> +			ranges = <0x0 0xf801c000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +			status = "disabled";
> +
> +			uart0: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi0: spi@400 {
> +				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c0: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx1: flexcom@f8020000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8020000 0x200>;
> +			ranges = <0x0 0xf8020000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +			status = "disabled";
> +
> +			uart1: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi1: spi@400 {
> +				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx2: flexcom@f8024000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8024000 0x200>;
> +			ranges = <0x0 0xf8024000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +			status = "disabled";
> +
> +			uart2: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi2: spi@400 {
> +				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx3: flexcom@f8028000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8028000 0x200>;
> +			ranges = <0x0 0xf8028000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +			status = "disabled";
> +
> +			uart3: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi3: spi@400 {
> +				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		gmac: ethernet@f802c000 {
> +			compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem";
> +			reg = <0xf802c000 0x1000>;
> +			interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 0 */
> +				     <60 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 1 */
> +				     <61 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 2 */
> +				     <62 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 3 */
> +				     <63 IRQ_TYPE_LEVEL_HIGH 3>,	/* Queue 4 */
> +				     <64 IRQ_TYPE_LEVEL_HIGH 3>;	/* Queue 5 */
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>;
> +			clock-names = "hclk", "pclk", "tx_clk", "tsu_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 67>;

Is this needed?

> +			status = "disabled";
> +		};
> +
> +		pwm0: pwm@f8034000 {
> +			compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm";
> +			reg = <0xf8034000 0x300>;
> +			interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
> +			#pwm-cells = <3>;
> +			status = "disabled";
> +		};
> +
> +		flx9: flexcom@f8040000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8040000 0x200>;
> +			ranges = <0x0 0xf8040000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +			status = "disabled";
> +
> +			uart9: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(18))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(19))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c9: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(18))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(19))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx10: flexcom@f8044000 {
> +			compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
> +			reg = <0xf8044000 0x200>;
> +			ranges = <0x0 0xf8044000 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +			status = "disabled";
> +
> +			uart10: serial@200 {
> +				compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				clock-names = "usart";
> +				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(20))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(21))>;
> +				dma-names = "tx", "rx";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c10: i2c@600 {
> +				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(20))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(21))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		sfr: sfr@f8050000 {
> +			compatible = "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon";
> +			reg = <0xf8050000 0x100>;
> +		};
> +
> +		matrix: matrix@ffffde00 {
> +			compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon";
> +			reg = <0xffffde00 0x200>;
> +		};
> +
> +		pmecc: ecc-engine@ffffe000 {
> +			compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc";
> +			reg = <0xffffe000 0x300>, <0xffffe600 0x100>;
> +		};
> +
> +		mpddrc: mpddrc@ffffe800 {
> +			compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc";
> +			reg = <0xffffe800 0x200>;
> +			clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			clock-names = "ddrck", "mpddr";
> +		};
> +
> +		smc: smc@ffffea00 {
> +			compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon";
> +			reg = <0xffffea00 0x100>;
> +		};
> +
> +		aic: interrupt-controller@fffff100 {
> +			compatible = "microchip,sam9x7-aic", "microchip,sam9x60-aic";
> +			reg = <0xfffff100 0x100>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			atmel,external-irqs = <31>;
> +			microchip,nr-irqs = <70>;

Ah, this needs to be clarified before applying.

> +		};
> +
> +		dbgu: serial@fffff200 {
> +			compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
> +			reg = <0xfffff200 0x200>;
> +			interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
> +			clock-names = "usart";
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(28))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(29))>;
> +			dma-names = "tx", "rx";
> +			atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> +			status = "disabled";
> +		};
> +
> +		pinctrl: pinctrl@fffff400 {
> +			compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd";
> +			ranges = <0xfffff400 0xfffff400 0x800>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			/* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */
> +			atmel,mux-mask = <
> +					 /*  A		B	   C	      D	  */
> +					 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000	/* pioA */
> +					 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000	/* pioB */
> +					 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000	/* pioC */
> +					 0x00003fff 0x00003fe0 0x0000003f 0x00000000	/* pioD */
> +					 >;
> +
> +			pioA: gpio@fffff400 {
> +				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff400 0x200>;
> +				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#interrupt-cells = <2>;
> +				interrupt-controller;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
> +			};
> +
> +			pioB: gpio@fffff600 {
> +				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff600 0x200>;
> +				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#interrupt-cells = <2>;
> +				interrupt-controller;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				#gpio-lines = <26>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
> +			};
> +
> +			pioC: gpio@fffff800 {
> +				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff800 0x200>;
> +				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#interrupt-cells = <2>;
> +				interrupt-controller;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
> +			};
> +
> +			pioD: gpio@fffffa00 {
> +				compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffffa00 0x200>;
> +				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#interrupt-cells = <2>;
> +				interrupt-controller;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				#gpio-lines = <22>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
> +			};
> +		};
> +
> +		pmc: clock-controller@fffffc00 {
> +			compatible = "microchip,sam9x7-pmc", "syscon";
> +			reg = <0xfffffc00 0x200>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			#clock-cells = <2>;
> +			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
> +			clock-names = "td_slck", "md_slck", "main_xtal";
> +		};
> +
> +		reset_controller: reset-controller@fffffe00 {
> +			compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc";
> +			reg = <0xfffffe00 0x10>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		poweroff: poweroff@fffffe10 {
> +			compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc";
> +			reg = <0xfffffe10 0x10>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&clk32k 0>;
> +			atmel,wakeup-rtc-timer;
> +			atmel,wakeup-rtt-timer;
> +			status = "disabled";
> +		};
> +
> +		rtt: rtc@fffffe20 {
> +			compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt";
> +			reg = <0xfffffe20 0x20>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		clk32k: clock-controller@fffffe50 {
> +			compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc";
> +			reg = <0xfffffe50 0x4>;
> +			clocks = <&slow_xtal>;
> +			#clock-cells = <1>;
> +		};
> +
> +		gpbr: syscon@fffffe60 {
> +			compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon";
> +			reg = <0xfffffe60 0x10>;
> +		};
> +
> +		rtc: rtc@fffffea8 {
> +			compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc";
> +			reg = <0xfffffea8 0x100>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		watchdog: watchdog@ffffff80 {
> +			compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt";
> +			reg = <0xffffff80 0x24>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			status = "disabled";
> +		};
> +	};
> +};

Re: [PATCH v5 25/27] ARM: dts: at91: sam9x7: add device tree for SoC

[Varshini.Rajendran]

Hi Claudiu,

On 14/07/24 7:14 pm, claudiu beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi, Varshini,
> 
> On 03.07.2024 13:29, Varshini Rajendran wrote:
>> Add device tree file for SAM9X7 SoC family.
>>
>> Co-developed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changed in v5:
>> - Sorted node properties according dts coding style.
>> - Removed space before pwn status.
>> - Fixed DT schema warnings related to usart.
>> - Aligned <> braces.
>> - Changed spaces to tabs.
>> - Changed node names to generic names.
>> - Corrected the typo in gpbr compatible.
>> ---
>>   arch/arm/boot/dts/microchip/sam9x7.dtsi | 1226 +++++++++++++++++++++++
>>   1 file changed, 1226 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi
>>
>> diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi
>> new file mode 100644
>> index 000000000000..0e3fb94f40b6
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi
>> @@ -0,0 +1,1226 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
>> + *
>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>> + */
>> +
>> +#include <dt-bindings/clock/at91.h>
>> +#include <dt-bindings/dma/at91.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/mfd/at91-usart.h>
>> +#include <dt-bindings/mfd/atmel-flexcom.h>
>> +#include <dt-bindings/pinctrl/at91.h>
>> +
>> +/ {
>> +     model = "Microchip SAM9X7 SoC";
>> +     compatible = "microchip,sam9x7";
>> +     #address-cells = <1>;
>> +     #size-cells = <1>;
>> +     interrupt-parent = <&aic>;
>> +
>> +     aliases {
>> +             serial0 = &dbgu;
>> +             gpio0 = &pioA;
>> +             gpio1 = &pioB;
>> +             gpio2 = &pioC;
>> +             gpio3 = &pioD;
>> +     };
>> +
>> +     cpus {
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +
>> +             cpu@0 {
>> +                     compatible = "arm,arm926ej-s";
>> +                     reg = <0>;
>> +                     device_type = "cpu";
>> +             };
>> +     };
>> +
>> +     clocks {
>> +             slow_xtal: clock-slowxtal {
>> +                     compatible = "fixed-clock";
>> +                     #clock-cells = <0>;
>> +             };
>> +
>> +             main_xtal: clock-mainxtal {
>> +                     compatible = "fixed-clock";
>> +                     #clock-cells = <0>;
>> +             };
>> +     };
>> +
>> +     sram: sram@300000 {
>> +             compatible = "mmio-sram";
>> +             reg = <0x300000 0x10000>;
>> +             ranges = <0 0x300000 0x10000>;
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +     };
>> +
>> +     ahb {
>> +             compatible = "simple-bus";
>> +             ranges;
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +
>> +             sdmmc0: mmc@80000000 {
>> +                     compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
>> +                     reg = <0x80000000 0x300>;
>> +                     interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
>> +                     clock-names = "hclock", "multclk";
>> +                     assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
>> +                     assigned-clock-rates = <100000000>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             sdmmc1: mmc@90000000 {
>> +                     compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
>> +                     reg = <0x90000000 0x300>;
>> +                     interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
>> +                     clock-names = "hclock", "multclk";
>> +                     assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
>> +                     assigned-clock-rates = <100000000>;
>> +                     status = "disabled";
>> +             };
>> +     };
>> +
>> +     apb {
>> +             compatible = "simple-bus";
>> +             ranges;
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +
>> +             flx4: flexcom@f0000000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf0000000 0x200>;
>> +                     ranges = <0x0 0xf0000000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>> +                     status = "disabled";
>> +
>> +                     uart4: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
> 
> According to dts coding style that vendor specific properties goes at the
> end. I'll adjust it when applying, no need to resend for this. Valid for
> all the uart flexcom nodes.

Thanks Claudiu.
> 
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(8))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(9))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     spi4: spi@400 {
>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>> +                             reg = <0x400 0x200>;
>> +                             interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>> +                             clock-names = "spi_clk";
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(8))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(9))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c4: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(8))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(9))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx5: flexcom@f0004000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf0004000 0x200>;
>> +                     ranges = <0x0 0xf0004000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>> +                     status = "disabled";
>> +
>> +                     uart5: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(10))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(11))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     spi5: spi@400 {
>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>> +                             reg = <0x400 0x200>;
>> +                             interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>> +                             clock-names = "spi_clk";
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(10))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(11))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c5: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(10))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(11))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             dma0: dma-controller@f0008000 {
>> +                     compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma";
>> +                     reg = <0xf0008000 0x1000>;
>> +                     interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     #dma-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
>> +                     clock-names = "dma_clk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             ssc: ssc@f0010000 {
>> +                     compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc";
>> +                     reg = <0xf0010000 0x4000>;
>> +                     interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
>> +                     clock-names = "pclk";
>> +                     dmas = <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(38))>,
>> +                            <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(39))>;
>> +                     dma-names = "tx", "rx";
>> +                     status = "disabled";
>> +             };
>> +
>> +             i2s: i2s@f001c000 {
>> +                     compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc";
>> +                     reg = <0xf001c000 0x100>;
>> +                     interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
>> +                     clock-names = "pclk", "gclk";
>> +                     dmas = <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(36))>,
>> +                            <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(37))>;
>> +                     dma-names = "tx", "rx";
>> +                     status = "disabled";
>> +             };
>> +
>> +             flx11: flexcom@f0020000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf0020000 0x200>;
>> +                     ranges = <0x0 0xf0020000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
>> +                     status = "disabled";
>> +
>> +                     uart11: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(22))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(23))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c11: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(22))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(23))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx12: flexcom@f0024000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf0024000 0x200>;
>> +                     ranges = <0x0 0xf0024000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
>> +                     status = "disabled";
>> +
>> +                     uart12: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(24))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(25))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c12: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(24))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(25))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             pit64b0: timer@f0028000 {
>> +                     compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
>> +                     reg = <0xf0028000 0x100>;
>> +                     interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
>> +                     clock-names = "pclk", "gclk";
>> +             };
>> +
>> +             sha: crypto@f002c000 {
>> +                     compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha";
>> +                     reg = <0xf002c000 0x100>;
>> +                     interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
>> +                     clock-names = "sha_clk";
>> +                     dmas = <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(34))>;
>> +                     dma-names = "tx";
>> +             };
>> +
>> +             trng: rng@f0030000 {
>> +                     compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng";
>> +                     reg = <0xf0030000 0x100>;
>> +                     interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             aes: crypto@f0034000 {
>> +                     compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes";
>> +                     reg = <0xf0034000 0x100>;
>> +                     interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
>> +                     clock-names = "aes_clk";
>> +                     dmas = <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(32))>,
>> +                            <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(33))>;
>> +                     dma-names = "tx", "rx";
>> +             };
>> +
>> +             tdes: crypto@f0038000 {
>> +                     compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes";
>> +                     reg = <0xf0038000 0x100>;
>> +                     interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
>> +                     clock-names = "tdes_clk";
>> +                     dmas = <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(31))>,
>> +                            <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(30))>;
>> +                     dma-names = "tx", "rx";
>> +             };
>> +
>> +             classd: sound@f003c000 {
>> +                     compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd";
>> +                     reg = <0xf003c000 0x100>;
>> +                     interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
>> +                     clock-names = "pclk", "gclk";
>> +                     dmas = <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(35))>;
>> +                     dma-names = "tx";
>> +                     status = "disabled";
>> +             };
>> +
>> +             pit64b1: timer@f0040000 {
>> +                     compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
>> +                     reg = <0xf0040000 0x100>;
>> +                     interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
>> +                     clock-names = "pclk", "gclk";
>> +             };
>> +
>> +             can0: can@f8000000 {
>> +                     compatible = "bosch,m_can";
>> +                     reg = <0xf8000000 0x100>, <0x300000 0x7800>;
>> +                     reg-names = "m_can", "message_ram";
>> +                     interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>,
>> +                                  <68 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     interrupt-names = "int0", "int1";
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
>> +                     clock-names = "hclk", "cclk";
>> +                     assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
>> +                     assigned-clock-rates = <480000000>, <40000000>;
>> +                     assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
>> +                     bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             can1: can@f8004000 {
>> +                     compatible = "bosch,m_can";
>> +                     reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
>> +                     reg-names = "m_can", "message_ram";
>> +                     interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>,
>> +                                  <69 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     interrupt-names = "int0", "int1";
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
>> +                     clock-names = "hclk", "cclk";
>> +                     assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
>> +                     assigned-clock-rates = <480000000>, <40000000>;
>> +                     assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
>> +                     bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             tcb: timer@f8008000 {
>> +                     compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon";
>> +                     reg = <0xf8008000 0x100>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <0>;
>> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>;
>> +                     clock-names = "t0_clk", "gclk", "slow_clk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             flx6: flexcom@f8010000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8010000 0x200>;
>> +                     ranges = <0x0 0xf8010000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
>> +                     status = "disabled";
>> +
>> +                     uart6: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(12))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(13))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c6: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(12))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(13))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx7: flexcom@f8014000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8014000 0x200>;
>> +                     ranges = <0x0 0xf8014000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
>> +                     status = "disabled";
>> +
>> +                     uart7: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(14))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(15))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c7: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(14))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(15))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx8: flexcom@f8018000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8018000 0x200>;
>> +                     ranges = <0x0 0xf8018000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
>> +                     status = "disabled";
>> +
>> +                     uart8: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(16))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(17))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c8: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(16))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(17))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx0: flexcom@f801c000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf801c000 0x200>;
>> +                     ranges = <0x0 0xf801c000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>> +                     status = "disabled";
>> +
>> +                     uart0: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(0))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(1))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     spi0: spi@400 {
>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>> +                             reg = <0x400 0x200>;
>> +                             interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>> +                             clock-names = "spi_clk";
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(0))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(1))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c0: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(0))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(1))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx1: flexcom@f8020000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8020000 0x200>;
>> +                     ranges = <0x0 0xf8020000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>> +                     status = "disabled";
>> +
>> +                     uart1: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(2))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(3))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     spi1: spi@400 {
>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>> +                             reg = <0x400 0x200>;
>> +                             interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>> +                             clock-names = "spi_clk";
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(2))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(3))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c1: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(2))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(3))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx2: flexcom@f8024000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8024000 0x200>;
>> +                     ranges = <0x0 0xf8024000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>> +                     status = "disabled";
>> +
>> +                     uart2: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(4))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(5))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     spi2: spi@400 {
>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>> +                             reg = <0x400 0x200>;
>> +                             interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>> +                             clock-names = "spi_clk";
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(4))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(5))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c2: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(4))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(5))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx3: flexcom@f8028000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8028000 0x200>;
>> +                     ranges = <0x0 0xf8028000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>> +                     status = "disabled";
>> +
>> +                     uart3: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(6))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(7))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     spi3: spi@400 {
>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>> +                             reg = <0x400 0x200>;
>> +                             interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>> +                             clock-names = "spi_clk";
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(6))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(7))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c3: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(6))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(7))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             gmac: ethernet@f802c000 {
>> +                     compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem";
>> +                     reg = <0xf802c000 0x1000>;
>> +                     interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 0 */
>> +                                  <60 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 1 */
>> +                                  <61 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 2 */
>> +                                  <62 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 3 */
>> +                                  <63 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 4 */
>> +                                  <64 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 5 */
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>;
>> +                     clock-names = "hclk", "pclk", "tx_clk", "tsu_clk";
>> +                     assigned-clocks = <&pmc PMC_TYPE_GCK 67>;
> 
> Is this needed?

Sorry I missed to add this line under it. This is needed for the PTP 
functionality.

assigned-clock-rates = <266666666>;

I can send another version if you want me to.
> 
>> +                     status = "disabled";
>> +             };
>> +
>> +             pwm0: pwm@f8034000 {
>> +                     compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm";
>> +                     reg = <0xf8034000 0x300>;
>> +                     interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
>> +                     #pwm-cells = <3>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             flx9: flexcom@f8040000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8040000 0x200>;
>> +                     ranges = <0x0 0xf8040000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
>> +                     status = "disabled";
>> +
>> +                     uart9: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(18))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(19))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c9: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(18))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(19))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             flx10: flexcom@f8044000 {
>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>> +                     reg = <0xf8044000 0x200>;
>> +                     ranges = <0x0 0xf8044000 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
>> +                     status = "disabled";
>> +
>> +                     uart10: serial@200 {
>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                             reg = <0x200 0x200>;
>> +                             interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
>> +                             clock-names = "usart";
>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(20))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(21))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,use-dma-rx;
>> +                             atmel,use-dma-tx;
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +
>> +                     i2c10: i2c@600 {
>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>> +                             reg = <0x600 0x200>;
>> +                             interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
>> +                             dmas = <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(20))>,
>> +                                    <&dma0
>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>> +                                      AT91_XDMAC_DT_PERID(21))>;
>> +                             dma-names = "tx", "rx";
>> +                             atmel,fifo-size = <16>;
>> +                             status = "disabled";
>> +                     };
>> +             };
>> +
>> +             sfr: sfr@f8050000 {
>> +                     compatible = "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon";
>> +                     reg = <0xf8050000 0x100>;
>> +             };
>> +
>> +             matrix: matrix@ffffde00 {
>> +                     compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon";
>> +                     reg = <0xffffde00 0x200>;
>> +             };
>> +
>> +             pmecc: ecc-engine@ffffe000 {
>> +                     compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc";
>> +                     reg = <0xffffe000 0x300>, <0xffffe600 0x100>;
>> +             };
>> +
>> +             mpddrc: mpddrc@ffffe800 {
>> +                     compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc";
>> +                     reg = <0xffffe800 0x200>;
>> +                     clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
>> +                     clock-names = "ddrck", "mpddr";
>> +             };
>> +
>> +             smc: smc@ffffea00 {
>> +                     compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon";
>> +                     reg = <0xffffea00 0x100>;
>> +             };
>> +
>> +             aic: interrupt-controller@fffff100 {
>> +                     compatible = "microchip,sam9x7-aic", "microchip,sam9x60-aic";
>> +                     reg = <0xfffff100 0x100>;
>> +                     #interrupt-cells = <3>;
>> +                     interrupt-controller;
>> +                     atmel,external-irqs = <31>;
>> +                     microchip,nr-irqs = <70>;
> 
> Ah, this needs to be clarified before applying.

Can you discard the property and apply the rest (if this version can be 
applied)? I can resolve the irq number related issue in a separate 
series. Maybe fix the compatibles if required.
> 
>> +             };
>> +
>> +             dbgu: serial@fffff200 {
>> +                     compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>> +                     reg = <0xfffff200 0x200>;
>> +                     interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
>> +                     clock-names = "usart";
>> +                     dmas = <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(28))>,
>> +                            <&dma0
>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>> +                              AT91_XDMAC_DT_PERID(29))>;
>> +                     dma-names = "tx", "rx";
>> +                     atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             pinctrl: pinctrl@fffff400 {
>> +                     compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd";
>> +                     ranges = <0xfffff400 0xfffff400 0x800>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +
>> +                     /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */
>> +                     atmel,mux-mask = <
>> +                                      /*  A          B          C          D   */
>> +                                      0xffffffff 0xffffefc0 0xc0ffd000 0x00000000    /* pioA */
>> +                                      0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000    /* pioB */
>> +                                      0xffffffff 0x07dfffff 0xfa3fffff 0x00000000    /* pioC */
>> +                                      0x00003fff 0x00003fe0 0x0000003f 0x00000000    /* pioD */
>> +                                      >;
>> +
>> +                     pioA: gpio@fffff400 {
>> +                             compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
>> +                             reg = <0xfffff400 0x200>;
>> +                             interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
>> +                             #interrupt-cells = <2>;
>> +                             interrupt-controller;
>> +                             #gpio-cells = <2>;
>> +                             gpio-controller;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
>> +                     };
>> +
>> +                     pioB: gpio@fffff600 {
>> +                             compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
>> +                             reg = <0xfffff600 0x200>;
>> +                             interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
>> +                             #interrupt-cells = <2>;
>> +                             interrupt-controller;
>> +                             #gpio-cells = <2>;
>> +                             gpio-controller;
>> +                             #gpio-lines = <26>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
>> +                     };
>> +
>> +                     pioC: gpio@fffff800 {
>> +                             compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
>> +                             reg = <0xfffff800 0x200>;
>> +                             interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
>> +                             #interrupt-cells = <2>;
>> +                             interrupt-controller;
>> +                             #gpio-cells = <2>;
>> +                             gpio-controller;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
>> +                     };
>> +
>> +                     pioD: gpio@fffffa00 {
>> +                             compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
>> +                             reg = <0xfffffa00 0x200>;
>> +                             interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
>> +                             #interrupt-cells = <2>;
>> +                             interrupt-controller;
>> +                             #gpio-cells = <2>;
>> +                             gpio-controller;
>> +                             #gpio-lines = <22>;
>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
>> +                     };
>> +             };
>> +
>> +             pmc: clock-controller@fffffc00 {
>> +                     compatible = "microchip,sam9x7-pmc", "syscon";
>> +                     reg = <0xfffffc00 0x200>;
>> +                     interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     #clock-cells = <2>;
>> +                     clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
>> +                     clock-names = "td_slck", "md_slck", "main_xtal";
>> +             };
>> +
>> +             reset_controller: reset-controller@fffffe00 {
>> +                     compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc";
>> +                     reg = <0xfffffe00 0x10>;
>> +                     clocks = <&clk32k 0>;
>> +             };
>> +
>> +             poweroff: poweroff@fffffe10 {
>> +                     compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc";
>> +                     reg = <0xfffffe10 0x10>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <0>;
>> +                     clocks = <&clk32k 0>;
>> +                     atmel,wakeup-rtc-timer;
>> +                     atmel,wakeup-rtt-timer;
>> +                     status = "disabled";
>> +             };
>> +
>> +             rtt: rtc@fffffe20 {
>> +                     compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt";
>> +                     reg = <0xfffffe20 0x20>;
>> +                     interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     clocks = <&clk32k 0>;
>> +             };
>> +
>> +             clk32k: clock-controller@fffffe50 {
>> +                     compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc";
>> +                     reg = <0xfffffe50 0x4>;
>> +                     clocks = <&slow_xtal>;
>> +                     #clock-cells = <1>;
>> +             };
>> +
>> +             gpbr: syscon@fffffe60 {
>> +                     compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon";
>> +                     reg = <0xfffffe60 0x10>;
>> +             };
>> +
>> +             rtc: rtc@fffffea8 {
>> +                     compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc";
>> +                     reg = <0xfffffea8 0x100>;
>> +                     interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     clocks = <&clk32k 0>;
>> +             };
>> +
>> +             watchdog: watchdog@ffffff80 {
>> +                     compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt";
>> +                     reg = <0xffffff80 0x24>;
>> +                     interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
>> +                     status = "disabled";
>> +             };
>> +     };
>> +};

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH v5 25/27] ARM: dts: at91: sam9x7: add device tree for SoC

[claudiu beznea]

On 15.07.2024 13:47, Varshini.Rajendran@microchip.com wrote:
> Hi Claudiu,
> 
> On 14/07/24 7:14 pm, claudiu beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Hi, Varshini,
>>
>> On 03.07.2024 13:29, Varshini Rajendran wrote:
>>> Add device tree file for SAM9X7 SoC family.
>>>
>>> Co-developed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>>> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>> Changed in v5:
>>> - Sorted node properties according dts coding style.
>>> - Removed space before pwn status.
>>> - Fixed DT schema warnings related to usart.
>>> - Aligned <> braces.
>>> - Changed spaces to tabs.
>>> - Changed node names to generic names.
>>> - Corrected the typo in gpbr compatible.
>>> ---
>>>   arch/arm/boot/dts/microchip/sam9x7.dtsi | 1226 +++++++++++++++++++++++
>>>   1 file changed, 1226 insertions(+)
>>>   create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi
>>>
>>> diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi
>>> new file mode 100644
>>> index 000000000000..0e3fb94f40b6
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi
>>> @@ -0,0 +1,1226 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +/*
>>> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
>>> + *
>>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>>> + *
>>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> + */
>>> +
>>> +#include <dt-bindings/clock/at91.h>
>>> +#include <dt-bindings/dma/at91.h>
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/mfd/at91-usart.h>
>>> +#include <dt-bindings/mfd/atmel-flexcom.h>
>>> +#include <dt-bindings/pinctrl/at91.h>
>>> +
>>> +/ {
>>> +     model = "Microchip SAM9X7 SoC";
>>> +     compatible = "microchip,sam9x7";
>>> +     #address-cells = <1>;
>>> +     #size-cells = <1>;
>>> +     interrupt-parent = <&aic>;
>>> +
>>> +     aliases {
>>> +             serial0 = &dbgu;
>>> +             gpio0 = &pioA;
>>> +             gpio1 = &pioB;
>>> +             gpio2 = &pioC;
>>> +             gpio3 = &pioD;
>>> +     };
>>> +
>>> +     cpus {
>>> +             #address-cells = <1>;
>>> +             #size-cells = <0>;
>>> +
>>> +             cpu@0 {
>>> +                     compatible = "arm,arm926ej-s";
>>> +                     reg = <0>;
>>> +                     device_type = "cpu";
>>> +             };
>>> +     };
>>> +
>>> +     clocks {
>>> +             slow_xtal: clock-slowxtal {
>>> +                     compatible = "fixed-clock";
>>> +                     #clock-cells = <0>;
>>> +             };
>>> +
>>> +             main_xtal: clock-mainxtal {
>>> +                     compatible = "fixed-clock";
>>> +                     #clock-cells = <0>;
>>> +             };
>>> +     };
>>> +
>>> +     sram: sram@300000 {
>>> +             compatible = "mmio-sram";
>>> +             reg = <0x300000 0x10000>;
>>> +             ranges = <0 0x300000 0x10000>;
>>> +             #address-cells = <1>;
>>> +             #size-cells = <1>;
>>> +     };
>>> +
>>> +     ahb {
>>> +             compatible = "simple-bus";
>>> +             ranges;
>>> +             #address-cells = <1>;
>>> +             #size-cells = <1>;
>>> +
>>> +             sdmmc0: mmc@80000000 {
>>> +                     compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
>>> +                     reg = <0x80000000 0x300>;
>>> +                     interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
>>> +                     clock-names = "hclock", "multclk";
>>> +                     assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
>>> +                     assigned-clock-rates = <100000000>;
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             sdmmc1: mmc@90000000 {
>>> +                     compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci";
>>> +                     reg = <0x90000000 0x300>;
>>> +                     interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
>>> +                     clock-names = "hclock", "multclk";
>>> +                     assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
>>> +                     assigned-clock-rates = <100000000>;
>>> +                     status = "disabled";
>>> +             };
>>> +     };
>>> +
>>> +     apb {
>>> +             compatible = "simple-bus";
>>> +             ranges;
>>> +             #address-cells = <1>;
>>> +             #size-cells = <1>;
>>> +
>>> +             flx4: flexcom@f0000000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf0000000 0x200>;
>>> +                     ranges = <0x0 0xf0000000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart4: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>> According to dts coding style that vendor specific properties goes at the
>> end. I'll adjust it when applying, no need to resend for this. Valid for
>> all the uart flexcom nodes.
> Thanks Claudiu.
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(8))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(9))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     spi4: spi@400 {
>>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>>> +                             reg = <0x400 0x200>;
>>> +                             interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>>> +                             clock-names = "spi_clk";
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(8))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(9))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c4: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(8))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(9))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx5: flexcom@f0004000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf0004000 0x200>;
>>> +                     ranges = <0x0 0xf0004000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart5: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(10))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(11))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     spi5: spi@400 {
>>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>>> +                             reg = <0x400 0x200>;
>>> +                             interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>>> +                             clock-names = "spi_clk";
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(10))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(11))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c5: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(10))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(11))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             dma0: dma-controller@f0008000 {
>>> +                     compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma";
>>> +                     reg = <0xf0008000 0x1000>;
>>> +                     interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     #dma-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
>>> +                     clock-names = "dma_clk";
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             ssc: ssc@f0010000 {
>>> +                     compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc";
>>> +                     reg = <0xf0010000 0x4000>;
>>> +                     interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
>>> +                     clock-names = "pclk";
>>> +                     dmas = <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(38))>,
>>> +                            <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(39))>;
>>> +                     dma-names = "tx", "rx";
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             i2s: i2s@f001c000 {
>>> +                     compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc";
>>> +                     reg = <0xf001c000 0x100>;
>>> +                     interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
>>> +                     clock-names = "pclk", "gclk";
>>> +                     dmas = <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(36))>,
>>> +                            <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(37))>;
>>> +                     dma-names = "tx", "rx";
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             flx11: flexcom@f0020000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf0020000 0x200>;
>>> +                     ranges = <0x0 0xf0020000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart11: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(22))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(23))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c11: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(22))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(23))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx12: flexcom@f0024000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf0024000 0x200>;
>>> +                     ranges = <0x0 0xf0024000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart12: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(24))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(25))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c12: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(24))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(25))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             pit64b0: timer@f0028000 {
>>> +                     compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
>>> +                     reg = <0xf0028000 0x100>;
>>> +                     interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
>>> +                     clock-names = "pclk", "gclk";
>>> +             };
>>> +
>>> +             sha: crypto@f002c000 {
>>> +                     compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha";
>>> +                     reg = <0xf002c000 0x100>;
>>> +                     interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
>>> +                     clock-names = "sha_clk";
>>> +                     dmas = <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(34))>;
>>> +                     dma-names = "tx";
>>> +             };
>>> +
>>> +             trng: rng@f0030000 {
>>> +                     compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng";
>>> +                     reg = <0xf0030000 0x100>;
>>> +                     interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             aes: crypto@f0034000 {
>>> +                     compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes";
>>> +                     reg = <0xf0034000 0x100>;
>>> +                     interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
>>> +                     clock-names = "aes_clk";
>>> +                     dmas = <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(32))>,
>>> +                            <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(33))>;
>>> +                     dma-names = "tx", "rx";
>>> +             };
>>> +
>>> +             tdes: crypto@f0038000 {
>>> +                     compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes";
>>> +                     reg = <0xf0038000 0x100>;
>>> +                     interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
>>> +                     clock-names = "tdes_clk";
>>> +                     dmas = <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(31))>,
>>> +                            <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(30))>;
>>> +                     dma-names = "tx", "rx";
>>> +             };
>>> +
>>> +             classd: sound@f003c000 {
>>> +                     compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd";
>>> +                     reg = <0xf003c000 0x100>;
>>> +                     interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
>>> +                     clock-names = "pclk", "gclk";
>>> +                     dmas = <&dma0
>>> +                             (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
>>> +                              AT91_XDMAC_DT_PERID(35))>;
>>> +                     dma-names = "tx";
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             pit64b1: timer@f0040000 {
>>> +                     compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b";
>>> +                     reg = <0xf0040000 0x100>;
>>> +                     interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
>>> +                     clock-names = "pclk", "gclk";
>>> +             };
>>> +
>>> +             can0: can@f8000000 {
>>> +                     compatible = "bosch,m_can";
>>> +                     reg = <0xf8000000 0x100>, <0x300000 0x7800>;
>>> +                     reg-names = "m_can", "message_ram";
>>> +                     interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>,
>>> +                                  <68 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     interrupt-names = "int0", "int1";
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
>>> +                     clock-names = "hclk", "cclk";
>>> +                     assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
>>> +                     assigned-clock-rates = <480000000>, <40000000>;
>>> +                     assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
>>> +                     bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             can1: can@f8004000 {
>>> +                     compatible = "bosch,m_can";
>>> +                     reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
>>> +                     reg-names = "m_can", "message_ram";
>>> +                     interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>,
>>> +                                  <69 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     interrupt-names = "int0", "int1";
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
>>> +                     clock-names = "hclk", "cclk";
>>> +                     assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
>>> +                     assigned-clock-rates = <480000000>, <40000000>;
>>> +                     assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
>>> +                     bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             tcb: timer@f8008000 {
>>> +                     compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon";
>>> +                     reg = <0xf8008000 0x100>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <0>;
>>> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>;
>>> +                     clock-names = "t0_clk", "gclk", "slow_clk";
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             flx6: flexcom@f8010000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8010000 0x200>;
>>> +                     ranges = <0x0 0xf8010000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart6: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(12))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(13))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c6: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(12))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(13))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx7: flexcom@f8014000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8014000 0x200>;
>>> +                     ranges = <0x0 0xf8014000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart7: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(14))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(15))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c7: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(14))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(15))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx8: flexcom@f8018000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8018000 0x200>;
>>> +                     ranges = <0x0 0xf8018000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart8: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(16))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(17))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c8: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(16))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(17))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx0: flexcom@f801c000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf801c000 0x200>;
>>> +                     ranges = <0x0 0xf801c000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart0: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(0))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(1))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     spi0: spi@400 {
>>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>>> +                             reg = <0x400 0x200>;
>>> +                             interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>>> +                             clock-names = "spi_clk";
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(0))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(1))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c0: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(0))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(1))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx1: flexcom@f8020000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8020000 0x200>;
>>> +                     ranges = <0x0 0xf8020000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart1: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(2))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(3))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     spi1: spi@400 {
>>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>>> +                             reg = <0x400 0x200>;
>>> +                             interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>>> +                             clock-names = "spi_clk";
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(2))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(3))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c1: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(2))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(3))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx2: flexcom@f8024000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8024000 0x200>;
>>> +                     ranges = <0x0 0xf8024000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart2: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(4))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(5))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     spi2: spi@400 {
>>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>>> +                             reg = <0x400 0x200>;
>>> +                             interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>>> +                             clock-names = "spi_clk";
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(4))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(5))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c2: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(4))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(5))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx3: flexcom@f8028000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8028000 0x200>;
>>> +                     ranges = <0x0 0xf8028000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart3: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(6))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(7))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     spi3: spi@400 {
>>> +                             compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
>>> +                             reg = <0x400 0x200>;
>>> +                             interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>>> +                             clock-names = "spi_clk";
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(6))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(7))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c3: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(6))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(7))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             gmac: ethernet@f802c000 {
>>> +                     compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem";
>>> +                     reg = <0xf802c000 0x1000>;
>>> +                     interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 0 */
>>> +                                  <60 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 1 */
>>> +                                  <61 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 2 */
>>> +                                  <62 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 3 */
>>> +                                  <63 IRQ_TYPE_LEVEL_HIGH 3>,        /* Queue 4 */
>>> +                                  <64 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 5 */
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>;
>>> +                     clock-names = "hclk", "pclk", "tx_clk", "tsu_clk";
>>> +                     assigned-clocks = <&pmc PMC_TYPE_GCK 67>;
>> Is this needed?
> Sorry I missed to add this line under it. This is needed for the PTP 
> functionality.
> 
> assigned-clock-rates = <266666666>;
> 
> I can send another version if you want me to.
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             pwm0: pwm@f8034000 {
>>> +                     compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm";
>>> +                     reg = <0xf8034000 0x300>;
>>> +                     interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
>>> +                     #pwm-cells = <3>;
>>> +                     status = "disabled";
>>> +             };
>>> +
>>> +             flx9: flexcom@f8040000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8040000 0x200>;
>>> +                     ranges = <0x0 0xf8040000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart9: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(18))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(19))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c9: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(18))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(19))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             flx10: flexcom@f8044000 {
>>> +                     compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom";
>>> +                     reg = <0xf8044000 0x200>;
>>> +                     ranges = <0x0 0xf8044000 0x800>;
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
>>> +                     status = "disabled";
>>> +
>>> +                     uart10: serial@200 {
>>> +                             compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart";
>>> +                             reg = <0x200 0x200>;
>>> +                             interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
>>> +                             clock-names = "usart";
>>> +                             atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(20))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(21))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,use-dma-rx;
>>> +                             atmel,use-dma-tx;
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +
>>> +                     i2c10: i2c@600 {
>>> +                             compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
>>> +                             reg = <0x600 0x200>;
>>> +                             interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
>>> +                             clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
>>> +                             dmas = <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(20))>,
>>> +                                    <&dma0
>>> +                                     (AT91_XDMAC_DT_MEM_IF(0) |
>>> +                                      AT91_XDMAC_DT_PER_IF(1) |
>>> +                                      AT91_XDMAC_DT_PERID(21))>;
>>> +                             dma-names = "tx", "rx";
>>> +                             atmel,fifo-size = <16>;
>>> +                             status = "disabled";
>>> +                     };
>>> +             };
>>> +
>>> +             sfr: sfr@f8050000 {
>>> +                     compatible = "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon";
>>> +                     reg = <0xf8050000 0x100>;
>>> +             };
>>> +
>>> +             matrix: matrix@ffffde00 {
>>> +                     compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon";
>>> +                     reg = <0xffffde00 0x200>;
>>> +             };
>>> +
>>> +             pmecc: ecc-engine@ffffe000 {
>>> +                     compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc";
>>> +                     reg = <0xffffe000 0x300>, <0xffffe600 0x100>;
>>> +             };
>>> +
>>> +             mpddrc: mpddrc@ffffe800 {
>>> +                     compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc";
>>> +                     reg = <0xffffe800 0x200>;
>>> +                     clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
>>> +                     clock-names = "ddrck", "mpddr";
>>> +             };
>>> +
>>> +             smc: smc@ffffea00 {
>>> +                     compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon";
>>> +                     reg = <0xffffea00 0x100>;
>>> +             };
>>> +
>>> +             aic: interrupt-controller@fffff100 {
>>> +                     compatible = "microchip,sam9x7-aic", "microchip,sam9x60-aic";
>>> +                     reg = <0xfffff100 0x100>;
>>> +                     #interrupt-cells = <3>;
>>> +                     interrupt-controller;
>>> +                     atmel,external-irqs = <31>;
>>> +                     microchip,nr-irqs = <70>;
>> Ah, this needs to be clarified before applying.
> Can you discard the property and apply the rest (if this version can be 
> applied)? 

I think it's not booting anyway w/o microchip,nr-irqs. Am I wrong?

> I can resolve the irq number related issue in a separate 
> series. Maybe fix the compatibles if required.

I prefer to have the driver ready before applying dts.

Thank you,
Claudiu Beznea

[PATCH v5 26/27] dt-bindings: arm: add sam9x75 curiosity board

[Varshini Rajendran]

Add documentation for SAM9X75 Curiosity board.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v5:
- Updated Acked-by tag.
---
 Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index 82f37328cc69..7160ec80ac1b 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -106,6 +106,12 @@ properties:
           - const: microchip,sam9x60
           - const: atmel,at91sam9
 
+      - description: Microchip SAM9X7 Evaluation Boards
+        items:
+          - const: microchip,sam9x75-curiosity
+          - const: microchip,sam9x7
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2
-- 
2.25.1

Re: [PATCH v5 26/27] dt-bindings: arm: add sam9x75 curiosity board

[claudiu beznea]

On 03.07.2024 13:29, Varshini Rajendran wrote:
> Add documentation for SAM9X75 Curiosity board.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Updated Acked-by tag.
> ---
>  Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> index 82f37328cc69..7160ec80ac1b 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> @@ -106,6 +106,12 @@ properties:
>            - const: microchip,sam9x60
>            - const: atmel,at91sam9
>  
> +      - description: Microchip SAM9X7 Evaluation Boards
> +        items:
> +          - const: microchip,sam9x75-curiosity
> +          - const: microchip,sam9x7
> +          - const: atmel,at91sam9
> +
>        - description: Nattis v2 board with Natte v2 power board
>          items:
>            - const: axentia,nattis-2

[PATCH v5 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

[Varshini Rajendran]

Add device tree file for sam9x75 curiosity board.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Update commit message to match the directory structure.
- Alphanumerically sorted Makefile entries.
- Corrected VDDCore minimum voltage.
- Enabled the i2s node.
- Removed additional blank lines.
- Enclosed each entry with separate <>.
- Corrected pinctrl names to match Microchip convention.
- Enabled slewrate in sdmmc node.
- Corrected pinmux mask.
- Added phandle to leds for ease of access with upcoming device entries.
- Updated gpio pin number for red led.
---
 arch/arm/boot/dts/microchip/Makefile          |   3 +
 .../dts/microchip/at91-sam9x75_curiosity.dts  | 312 ++++++++++++++++++
 2 files changed, 315 insertions(+)
 create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts

diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
index 0c45c8d17468..470fe46433a9 100644
--- a/arch/arm/boot/dts/microchip/Makefile
+++ b/arch/arm/boot/dts/microchip/Makefile
@@ -2,6 +2,7 @@
 # Enables support for device-tree overlays
 DTC_FLAGS_at91-sam9x60_curiosity := -@
 DTC_FLAGS_at91-sam9x60ek := -@
+DTC_FLAGS_at91-sam9x75_curiosity := -@
 DTC_FLAGS_at91-sama5d27_som1_ek := -@
 DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
 DTC_FLAGS_at91-sama5d29_curiosity := -@
@@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 dtb-$(CONFIG_SOC_SAM9X60) += \
 	at91-sam9x60_curiosity.dtb \
 	at91-sam9x60ek.dtb
+dtb-$(CONFIG_SOC_SAM9X7) += \
+	at91-sam9x75_curiosity.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
new file mode 100644
index 000000000000..4a4f14f13634
--- /dev/null
+++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x7.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Microchip SAM9X75 Curiosity";
+	compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c6;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+		button-user {
+			label = "USER";
+			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_0>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_red: led-red {
+			label = "red";
+			gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&pinctrl_red_led_gpio_default>;
+		};
+
+		led_green: led-green {
+			label = "green";
+			gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&pinctrl_green_led_gpio_default>;
+		};
+
+		led_blue: led-blue {
+			label = "blue";
+			gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&pinctrl_blue_led_gpio_default>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	memory@20000000 {
+		reg = <0x20000000 0x10000000>;
+		device_type = "memory";
+	};
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd_default>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu_default>;
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+};
+
+&i2c6 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flx6_default>;
+	i2c-analog-filter;
+	i2c-digital-filter;
+	i2c-digital-filter-width-ns = <35>;
+	status = "okay";
+
+	pmic@5b {
+		compatible = "microchip,mcp16502";
+		reg = <0x5b>;
+
+		regulators {
+			vdd_3v3: VDD_IO {
+				regulator-name = "VDD_IO";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vddioddr: VDD_DDR {
+				regulator-name = "VDD_DDR";
+				regulator-min-microvolt = <1283000>;
+				regulator-max-microvolt = <1450000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+			};
+
+			vddcore: VDD_CORE {
+				regulator-name = "VDD_CORE";
+				regulator-min-microvolt = <1140000>;
+				regulator-max-microvolt = <1210000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vddcpu: VDD_OTHER {
+				regulator-name = "VDD_OTHER";
+				regulator-min-microvolt = <1700000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3700000>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3700000>;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&main_xtal {
+	clock-frequency = <24000000>;
+};
+
+&pinctrl {
+	classd {
+		pinctrl_classd_default: classd-default {
+			atmel,pins =
+				<AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
+				<AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu_default: dbgu-default {
+			atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+				     <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx6_default: flx6-default {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+				<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	gpio-keys {
+		pinctrl_key_gpio_default: key-gpio-default {
+			atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s-default {
+			atmel,pins =
+				<AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SCK */
+				<AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SWS */
+				<AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDIN */
+				<AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDOUT */
+				<AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	leds {
+		pinctrl_red_led_gpio_default: red-led-gpio-default {
+			atmel,pins = <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+		pinctrl_green_led_gpio_default: green-led-gpio-default {
+			atmel,pins = <AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+		pinctrl_blue_led_gpio_default: blue-led-gpio-default {
+			atmel,pins = <AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0-default {
+			atmel,pins =
+				<AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,				/* PA2 CK  periph A with pullup */
+				<AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA1 CMD periph A with pullup */
+				<AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA0 DAT0 periph A */
+				<AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA3 DAT1 periph A with pullup */
+				<AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA4 DAT2 periph A with pullup */
+				<AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA5 DAT3 periph A with pullup */
+		};
+	};
+}; /* pinctrl */
+
+&rtt {
+	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	status = "okay";
+};
+
+&slow_xtal {
+	clock-frequency = <32768>;
+};
+
+&poweroff {
+	debounce-delay-us = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&trng {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
-- 
2.25.1

Re: [PATCH v5 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

[claudiu beznea]

Hi, Varshini,

On 03.07.2024 13:29, Varshini Rajendran wrote:
> Add device tree file for sam9x75 curiosity board.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v5:
> - Update commit message to match the directory structure.
> - Alphanumerically sorted Makefile entries.
> - Corrected VDDCore minimum voltage.
> - Enabled the i2s node.
> - Removed additional blank lines.
> - Enclosed each entry with separate <>.
> - Corrected pinctrl names to match Microchip convention.
> - Enabled slewrate in sdmmc node.
> - Corrected pinmux mask.
> - Added phandle to leds for ease of access with upcoming device entries.
> - Updated gpio pin number for red led.
> ---
>  arch/arm/boot/dts/microchip/Makefile          |   3 +
>  .../dts/microchip/at91-sam9x75_curiosity.dts  | 312 ++++++++++++++++++
>  2 files changed, 315 insertions(+)
>  create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> 
> diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
> index 0c45c8d17468..470fe46433a9 100644
> --- a/arch/arm/boot/dts/microchip/Makefile
> +++ b/arch/arm/boot/dts/microchip/Makefile
> @@ -2,6 +2,7 @@
>  # Enables support for device-tree overlays
>  DTC_FLAGS_at91-sam9x60_curiosity := -@
>  DTC_FLAGS_at91-sam9x60ek := -@
> +DTC_FLAGS_at91-sam9x75_curiosity := -@
>  DTC_FLAGS_at91-sama5d27_som1_ek := -@
>  DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
>  DTC_FLAGS_at91-sama5d29_curiosity := -@
> @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>  dtb-$(CONFIG_SOC_SAM9X60) += \
>  	at91-sam9x60_curiosity.dtb \
>  	at91-sam9x60ek.dtb
> +dtb-$(CONFIG_SOC_SAM9X7) += \
> +	at91-sam9x75_curiosity.dtb
>  dtb-$(CONFIG_SOC_SAM_V7) += \
>  	at91-kizbox2-2.dtb \
>  	at91-kizbox3-hs.dtb \
> diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> new file mode 100644
> index 000000000000..4a4f14f13634
> --- /dev/null
> +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> @@ -0,0 +1,312 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +/dts-v1/;
> +#include "sam9x7.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	model = "Microchip SAM9X75 Curiosity";
> +	compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
> +
> +	aliases {
> +		i2c0 = &i2c6;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_key_gpio_default>;
> +
> +		button-user {
> +			label = "USER";
> +			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_0>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led_red: led-red {
> +			label = "red";
> +			gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
> +			pinctrl-0 = <&pinctrl_red_led_gpio_default>;
> +		};
> +
> +		led_green: led-green {
> +			label = "green";
> +			gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
> +			pinctrl-0 = <&pinctrl_green_led_gpio_default>;
> +		};
> +
> +		led_blue: led-blue {
> +			label = "blue";
> +			gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
> +			pinctrl-0 = <&pinctrl_blue_led_gpio_default>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	memory@20000000 {
> +		reg = <0x20000000 0x10000000>;
> +		device_type = "memory";
> +	};
> +};
> +
> +&classd {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_classd_default>;
> +	atmel,pwm-type = "diff";
> +	atmel,non-overlap-time = <10>;
> +	status = "okay";
> +};
> +
> +&dbgu {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_dbgu_default>;
> +	status = "okay";
> +};
> +
> +&dma0 {
> +	status = "okay";
> +};
> +
> +&flx6 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +};
> +
> +&i2c6 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flx6_default>;
> +	i2c-analog-filter;
> +	i2c-digital-filter;
> +	i2c-digital-filter-width-ns = <35>;
> +	status = "okay";
> +
> +	pmic@5b {
> +		compatible = "microchip,mcp16502";
> +		reg = <0x5b>;
> +
> +		regulators {
> +			vdd_3v3: VDD_IO {
> +				regulator-name = "VDD_IO";
> +				regulator-min-microvolt = <3000000>;
> +				regulator-max-microvolt = <3600000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddioddr: VDD_DDR {
> +				regulator-name = "VDD_DDR";
> +				regulator-min-microvolt = <1283000>;
> +				regulator-max-microvolt = <1450000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddcore: VDD_CORE {
> +				regulator-name = "VDD_CORE";
> +				regulator-min-microvolt = <1140000>;
> +				regulator-max-microvolt = <1210000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddcpu: VDD_OTHER {
> +				regulator-name = "VDD_OTHER";
> +				regulator-min-microvolt = <1700000>;
> +				regulator-max-microvolt = <3600000>;

I haven't got any input on question asked in v4 on the regulator values.
Are the values from this version the right ones? Is this board supporting
DVFS or the label name is wrong or maybe the min-max range is still wrong?

> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-ramp-delay = <3125>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vldo1: LDO1 {
> +				regulator-name = "LDO1";
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <3700000>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +				};
> +			};
> +
> +			vldo2: LDO2 {
> +				regulator-name = "LDO2";
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <3700000>;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&i2s {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2s_default>;
> +	#sound-dai-cells = <0>;
> +	status = "okay";
> +};
> +
> +&main_xtal {
> +	clock-frequency = <24000000>;
> +};
> +
> +&pinctrl {
> +	classd {
> +		pinctrl_classd_default: classd-default {
> +			atmel,pins =
> +				<AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
> +				<AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
> +		};
> +	};
> +
> +	dbgu {
> +		pinctrl_dbgu_default: dbgu-default {
> +			atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
> +				     <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	flexcom {
> +		pinctrl_flx6_default: flx6-default {
> +			atmel,pins =
> +				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
> +				<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	gpio-keys {
> +		pinctrl_key_gpio_default: key-gpio-default {
> +			atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	i2s {
> +		pinctrl_i2s_default: i2s-default {
> +			atmel,pins =
> +				<AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SCK */
> +				<AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SWS */
> +				<AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDIN */
> +				<AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDOUT */
> +				<AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;		/* I2SMCK */
> +		};
> +	};
> +
> +	leds {
> +		pinctrl_red_led_gpio_default: red-led-gpio-default {
> +			atmel,pins = <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +		pinctrl_green_led_gpio_default: green-led-gpio-default {
> +			atmel,pins = <AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +		pinctrl_blue_led_gpio_default: blue-led-gpio-default {
> +			atmel,pins = <AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	sdmmc0 {
> +		pinctrl_sdmmc0_default: sdmmc0-default {
> +			atmel,pins =
> +				<AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,				/* PA2 CK  periph A with pullup */
> +				<AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA1 CMD periph A with pullup */
> +				<AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA0 DAT0 periph A */
> +				<AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA3 DAT1 periph A with pullup */
> +				<AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA4 DAT2 periph A with pullup */
> +				<AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA5 DAT3 periph A with pullup */
> +		};
> +	};
> +}; /* pinctrl */
> +
> +&rtt {
> +	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sdmmc0_default>;
> +	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	status = "okay";
> +};
> +
> +&slow_xtal {
> +	clock-frequency = <32768>;
> +};
> +
> +&poweroff {
> +	debounce-delay-us = <976>;
> +	status = "okay";
> +
> +	input@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +&trng {
> +	status = "okay";
> +};
> +
> +&watchdog {
> +	status = "okay";
> +};

Re: [PATCH v5 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

[Varshini.Rajendran]

On 14/07/24 7:16 pm, claudiu beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi, Varshini,
> 
> On 03.07.2024 13:29, Varshini Rajendran wrote:
>> Add device tree file for sam9x75 curiosity board.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v5:
>> - Update commit message to match the directory structure.
>> - Alphanumerically sorted Makefile entries.
>> - Corrected VDDCore minimum voltage.
>> - Enabled the i2s node.
>> - Removed additional blank lines.
>> - Enclosed each entry with separate <>.
>> - Corrected pinctrl names to match Microchip convention.
>> - Enabled slewrate in sdmmc node.
>> - Corrected pinmux mask.
>> - Added phandle to leds for ease of access with upcoming device entries.
>> - Updated gpio pin number for red led.
>> ---
>>   arch/arm/boot/dts/microchip/Makefile          |   3 +
>>   .../dts/microchip/at91-sam9x75_curiosity.dts  | 312 ++++++++++++++++++
>>   2 files changed, 315 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>>
>> diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
>> index 0c45c8d17468..470fe46433a9 100644
>> --- a/arch/arm/boot/dts/microchip/Makefile
>> +++ b/arch/arm/boot/dts/microchip/Makefile
>> @@ -2,6 +2,7 @@
>>   # Enables support for device-tree overlays
>>   DTC_FLAGS_at91-sam9x60_curiosity := -@
>>   DTC_FLAGS_at91-sam9x60ek := -@
>> +DTC_FLAGS_at91-sam9x75_curiosity := -@
>>   DTC_FLAGS_at91-sama5d27_som1_ek := -@
>>   DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
>>   DTC_FLAGS_at91-sama5d29_curiosity := -@
>> @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>>   dtb-$(CONFIG_SOC_SAM9X60) += \
>>        at91-sam9x60_curiosity.dtb \
>>        at91-sam9x60ek.dtb
>> +dtb-$(CONFIG_SOC_SAM9X7) += \
>> +     at91-sam9x75_curiosity.dtb
>>   dtb-$(CONFIG_SOC_SAM_V7) += \
>>        at91-kizbox2-2.dtb \
>>        at91-kizbox3-hs.dtb \
>> diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>> new file mode 100644
>> index 000000000000..4a4f14f13634
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>> @@ -0,0 +1,312 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
>> + *
>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>> + */
>> +/dts-v1/;
>> +#include "sam9x7.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +
>> +/ {
>> +     model = "Microchip SAM9X75 Curiosity";
>> +     compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
>> +
>> +     aliases {
>> +             i2c0 = &i2c6;
>> +     };
>> +
>> +     chosen {
>> +             stdout-path = "serial0:115200n8";
>> +     };
>> +
>> +     gpio-keys {
>> +             compatible = "gpio-keys";
>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_key_gpio_default>;
>> +
>> +             button-user {
>> +                     label = "USER";
>> +                     gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
>> +                     linux,code = <KEY_0>;
>> +                     wakeup-source;
>> +             };
>> +     };
>> +
>> +     leds {
>> +             compatible = "gpio-leds";
>> +
>> +             led_red: led-red {
>> +                     label = "red";
>> +                     gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
>> +                     pinctrl-0 = <&pinctrl_red_led_gpio_default>;
>> +             };
>> +
>> +             led_green: led-green {
>> +                     label = "green";
>> +                     gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
>> +                     pinctrl-0 = <&pinctrl_green_led_gpio_default>;
>> +             };
>> +
>> +             led_blue: led-blue {
>> +                     label = "blue";
>> +                     gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
>> +                     pinctrl-0 = <&pinctrl_blue_led_gpio_default>;
>> +                     linux,default-trigger = "heartbeat";
>> +             };
>> +     };
>> +
>> +     memory@20000000 {
>> +             reg = <0x20000000 0x10000000>;
>> +             device_type = "memory";
>> +     };
>> +};
>> +
>> +&classd {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_classd_default>;
>> +     atmel,pwm-type = "diff";
>> +     atmel,non-overlap-time = <10>;
>> +     status = "okay";
>> +};
>> +
>> +&dbgu {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_dbgu_default>;
>> +     status = "okay";
>> +};
>> +
>> +&dma0 {
>> +     status = "okay";
>> +};
>> +
>> +&flx6 {
>> +     atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
>> +     status = "okay";
>> +};
>> +
>> +&i2c6 {
>> +     #address-cells = <1>;
>> +     #size-cells = <0>;
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_flx6_default>;
>> +     i2c-analog-filter;
>> +     i2c-digital-filter;
>> +     i2c-digital-filter-width-ns = <35>;
>> +     status = "okay";
>> +
>> +     pmic@5b {
>> +             compatible = "microchip,mcp16502";
>> +             reg = <0x5b>;
>> +
>> +             regulators {
>> +                     vdd_3v3: VDD_IO {
>> +                             regulator-name = "VDD_IO";
>> +                             regulator-min-microvolt = <3000000>;
>> +                             regulator-max-microvolt = <3600000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddioddr: VDD_DDR {
>> +                             regulator-name = "VDD_DDR";
>> +                             regulator-min-microvolt = <1283000>;
>> +                             regulator-max-microvolt = <1450000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddcore: VDD_CORE {
>> +                             regulator-name = "VDD_CORE";
>> +                             regulator-min-microvolt = <1140000>;
>> +                             regulator-max-microvolt = <1210000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddcpu: VDD_OTHER {
>> +                             regulator-name = "VDD_OTHER";
>> +                             regulator-min-microvolt = <1700000>;
>> +                             regulator-max-microvolt = <3600000>;
> 
> I haven't got any input on question asked in v4 on the regulator values.
> Are the values from this version the right ones? Is this board supporting
> DVFS or the label name is wrong or maybe the min-max range is still wrong?

Apologies. I misanalysed the comment before. I will fix the regulator 
values/label with the values from the board schematics. And FYI, this 
board does not support DVFS. The values I set are misleading.

> 
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-ramp-delay = <3125>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vldo1: LDO1 {
>> +                             regulator-name = "LDO1";
>> +                             regulator-min-microvolt = <1200000>;
>> +                             regulator-max-microvolt = <3700000>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                             };
>> +                     };
>> +
>> +                     vldo2: LDO2 {
>> +                             regulator-name = "LDO2";
>> +                             regulator-min-microvolt = <1200000>;
>> +                             regulator-max-microvolt = <3700000>;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                             };
>> +                     };
>> +             };
>> +     };
>> +};
>> +
>> +&i2s {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_i2s_default>;
>> +     #sound-dai-cells = <0>;
>> +     status = "okay";
>> +};
>> +
>> +&main_xtal {
>> +     clock-frequency = <24000000>;
>> +};
>> +
>> +&pinctrl {
>> +     classd {
>> +             pinctrl_classd_default: classd-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
>> +                             <AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
>> +             };
>> +     };
>> +
>> +     dbgu {
>> +             pinctrl_dbgu_default: dbgu-default {
>> +                     atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
>> +                                  <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     flexcom {
>> +             pinctrl_flx6_default: flx6-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
>> +                             <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
>> +             };
>> +     };
>> +
>> +     gpio-keys {
>> +             pinctrl_key_gpio_default: key-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     i2s {
>> +             pinctrl_i2s_default: i2s-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SCK */
>> +                             <AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SWS */
>> +                             <AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SDIN */
>> +                             <AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SDOUT */
>> +                             <AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;         /* I2SMCK */
>> +             };
>> +     };
>> +
>> +     leds {
>> +             pinctrl_red_led_gpio_default: red-led-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +             pinctrl_green_led_gpio_default: green-led-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +             pinctrl_blue_led_gpio_default: blue-led-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     sdmmc0 {
>> +             pinctrl_sdmmc0_default: sdmmc0-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,                               /* PA2 CK  periph A with pullup */
>> +                             <AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA1 CMD periph A with pullup */
>> +                             <AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA0 DAT0 periph A */
>> +                             <AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA3 DAT1 periph A with pullup */
>> +                             <AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA4 DAT2 periph A with pullup */
>> +                             <AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;        /* PA5 DAT3 periph A with pullup */
>> +             };
>> +     };
>> +}; /* pinctrl */
>> +
>> +&rtt {
>> +     atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
>> +};
>> +
>> +&sdmmc0 {
>> +     bus-width = <4>;
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_sdmmc0_default>;
>> +     cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
>> +     disable-wp;
>> +     status = "okay";
>> +};
>> +
>> +&slow_xtal {
>> +     clock-frequency = <32768>;
>> +};
>> +
>> +&poweroff {
>> +     debounce-delay-us = <976>;
>> +     status = "okay";
>> +
>> +     input@0 {
>> +             reg = <0>;
>> +     };
>> +};
>> +
>> +&trng {
>> +     status = "okay";
>> +};
>> +
>> +&watchdog {
>> +     status = "okay";
>> +};

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH v5 00/27] Add support for sam9x7 SoC family

[Rob Herring (Arm)]

On Wed, 03 Jul 2024 15:50:11 +0530, Varshini Rajendran wrote:
> This patch series adds support for the new SoC family - sam9x7.
>  - The device tree, configs and drivers are added
>  - Clock driver for sam9x7 is added
>  - Support for basic peripherals is added
>  - Target board SAM9X75 Curiosity is added
> 
>  Changes in v5:
>  --------------
> 
>  - Addressed all the review comments in the patches
>  - Picked up all Acked-by and Reviewed-by tags
>  - Dropped applied patches from the series
>  - Addressed the ABI breakage reported in the IRQ patch
>  - All the specific changes are captured in the corresponding patches
> 
>  Changes in v4:
>  --------------
> 
>  - Addressed all the review comments in the patches
>  - Picked up all Acked-by and Reviewed-by tags
>  - Dropped applied patches from the series
>  - Added pwm node and related dt binding documentation
>  - Added support for exporting some clocks to DT
>  - Dropped USB related patches and changes. See NOTE.
>  - All the specific changes are captured in the corresponding patches
> 
>  NOTE: Owing to the discussion here
>  https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=B7t+KS_kOinxaRx38=WxA@mail.gmail.com/
>  the USB related changes are dropped from this series in order to enable
>  us to work on the mentioned issues before adding new compatibles as
>  said. The issues/warnings will be addressed in subsequent patches.
>  After which the USB related support for sam9x7 SoCs will be added. Hope
>  this works out fine.
> 
>  Changes in v3:
>  --------------
> 
>  - Fixed the DT documentation errors pointed out in v2.
>  - Dropped Acked-by tag in tcb DT doc patch as it had to be adapted
>    according to sam9x7 correctly.
>  - Picked by the previously missed tags.
>  - Dropped this patch "dt-bindings: usb: generic-ehci: Document clock-names
>    property" as the warning was not found while validating DT-schema for
>    at91-sam9x75_curiosity.dtb.
>  - Dropped redundant words in the commit message.
>  - Fixed the CHECK_DTBS warnings validated against
>    at91-sam9x75_curiosity.dtb.
>  - Renamed dt nodes according to naming convention.
>  - Dropped unwanted status property in dts.
>  - Removed nodes that are not in use from the board dts.
>  - Removed spi DT doc patch from the series as it was already applied
>    and a fix patch was applied subsequently. Added a patch to remove the
>    compatible to adapt sam9x7.
>  - Added sam9x7 compatibles in usb dt documentation.
> 
> 
>  Changes in v2:
>  --------------
> 
>  - Added sam9x7 specific compatibles in DT with fallbacks
>  - Documented all the newly added DT compatible strings
>  - Added device tree for the target board sam9x75 curiosity and
>    documented the same in the DT bindings documentation
>  - Removed the dt nodes that are not supported at the moment
>  - Removed the configs added by previous version that are not supported
>    at the moment
>  - Fixed all the corrections in the commit message
>  - Changed all the instances of copyright year to 2023
>  - Added sam9x7 flag in PIT64B configuration
>  - Moved macro definitions to header file
>  - Added another divider in mck characteristics in the pmc driver
>  - Fixed the memory leak in the pmc driver
>  - Dropped patches that are no longer needed
>  - Picked up Acked-by and Reviewed-by tags
> 
> 
> Varshini Rajendran (27):
>   dt-bindings: atmel-sysreg: add sam9x7
>   dt-bindings: atmel-ssc: add microchip,sam9x7-ssc
>   dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.
>   ARM: at91: pm: add support for sam9x7 SoC family
>   ARM: at91: pm: add sam9x7 SoC init config
>   ARM: at91: add support in SoC driver for new sam9x7
>   dt-bindings: clocks: atmel,at91sam9x5-sckc
>   dt-bindings: clocks: atmel,at91rm9200-pmc
>   clk: at91: clk-sam9x60-pll: re-factor to support individual core freq
>     outputs
>   clk: at91: sam9x7: add support for HW PLL freq dividers
>   clk: at91: sama7g5: move mux table macros to header file
>   dt-bindings: clock: at91: Allow PLLs to be exported and referenced in
>     DT
>   clk: at91: sam9x7: add sam9x7 pmc driver
>   dt-bindings: interrupt-controller: Add support for sam9x7 aic
>   dt-bindings: interrupt-controller: Document the property
>     microchip,nr-irqs
>   irqchip/atmel-aic5: Add support to get nr_irqs from DT for sam9x60 &
>     sam9x7
>   ARM: dts: at91: sam9x60: Add nirqs property in the dt node
>   power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7
>   power: reset: at91-reset: add reset support for sam9x7 SoC
>   power: reset: at91-reset: add sdhwc support for sam9x7 SoC
>   dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7
>   dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7
>   ARM: at91: Kconfig: add config flag for SAM9X7 SoC
>   ARM: configs: at91: enable config flags for sam9x7 SoC family
>   ARM: dts: at91: sam9x7: add device tree for SoC
>   dt-bindings: arm: add sam9x75 curiosity board
>   ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board
> 
>  .../devicetree/bindings/arm/atmel-at91.yaml   |    6 +
>  .../devicetree/bindings/arm/atmel-sysregs.txt |    7 +-
>  .../bindings/clock/atmel,at91rm9200-pmc.yaml  |    2 +
>  .../bindings/clock/atmel,at91sam9x5-sckc.yaml |    4 +-
>  .../interrupt-controller/atmel,aic.yaml       |   28 +-
>  .../devicetree/bindings/misc/atmel-ssc.txt    |    1 +
>  .../power/reset/atmel,sama5d2-shdwc.yaml      |    3 +
>  .../reset/atmel,at91sam9260-reset.yaml        |    4 +
>  .../bindings/serial/atmel,at91-usart.yaml     |    9 +-
>  arch/arm/boot/dts/microchip/Makefile          |    3 +
>  .../dts/microchip/at91-sam9x75_curiosity.dts  |  312 +++++
>  arch/arm/boot/dts/microchip/sam9x60.dtsi      |    1 +
>  arch/arm/boot/dts/microchip/sam9x7.dtsi       | 1226 +++++++++++++++++
>  arch/arm/configs/at91_dt_defconfig            |    1 +
>  arch/arm/mach-at91/Kconfig                    |   22 +-
>  arch/arm/mach-at91/Makefile                   |    1 +
>  arch/arm/mach-at91/generic.h                  |    2 +
>  arch/arm/mach-at91/pm.c                       |   29 +
>  arch/arm/mach-at91/sam9x7.c                   |   33 +
>  drivers/clk/at91/Makefile                     |    1 +
>  drivers/clk/at91/clk-sam9x60-pll.c            |   42 +-
>  drivers/clk/at91/pmc.h                        |   18 +
>  drivers/clk/at91/sam9x60.c                    |    7 +
>  drivers/clk/at91/sam9x7.c                     |  946 +++++++++++++
>  drivers/clk/at91/sama7g5.c                    |   42 +-
>  drivers/irqchip/irq-atmel-aic5.c              |    8 +-
>  drivers/power/reset/Kconfig                   |    4 +-
>  drivers/power/reset/at91-sama5d2_shdwc.c      |    1 +
>  drivers/soc/atmel/soc.c                       |   23 +
>  drivers/soc/atmel/soc.h                       |    9 +
>  include/dt-bindings/clock/at91.h              |    4 +
>  31 files changed, 2750 insertions(+), 49 deletions(-)
>  create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>  create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi
>  create mode 100644 arch/arm/mach-at91/sam9x7.c
>  create mode 100644 drivers/clk/at91/sam9x7.c
> 
> --
> 2.25.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y microchip/at91-sam9x75_curiosity.dtb' for 20240703102011.193343-1-varshini.rajendran@microchip.com:

arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@80000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@80000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@90000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@90000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/dma-controller@f0008000: failed to match any schema with compatible: ['microchip,sam9x7-dma', 'atmel,sama5d4-dma']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/dma-controller@f0008000: failed to match any schema with compatible: ['microchip,sam9x7-dma', 'atmel,sama5d4-dma']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ssc@f0010000: failed to match any schema with compatible: ['microchip,sam9x7-ssc', 'atmel,at91sam9g45-ssc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ssc@f0010000: failed to match any schema with compatible: ['microchip,sam9x7-ssc', 'atmel,at91sam9g45-ssc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0028000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0028000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0040000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0040000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible:0: 'microchip,sam9x7-tcb' is not one of ['atmel,at91rm9200-tcb', 'atmel,at91sam9x5-tcb', 'atmel,sama5d2-tcb']
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible:1: 'simple-mfd' was expected
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible:2: 'syscon' was expected
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible: ['microchip,sam9x7-tcb', 'atmel,sama5d2-tcb', 'simple-mfd', 'syscon'] is too long
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f8008000: failed to match any schema with compatible: ['microchip,sam9x7-tcb', 'atmel,sama5d2-tcb', 'simple-mfd', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/sfr@f8050000: failed to match any schema with compatible: ['microchip,sam9x7-sfr', 'microchip,sam9x60-sfr', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/sfr@f8050000: failed to match any schema with compatible: ['microchip,sam9x7-sfr', 'microchip,sam9x60-sfr', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/matrix@ffffde00: failed to match any schema with compatible: ['microchip,sam9x7-matrix', 'atmel,at91sam9x5-matrix', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/matrix@ffffde00: failed to match any schema with compatible: ['microchip,sam9x7-matrix', 'atmel,at91sam9x5-matrix', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ecc-engine@ffffe000: failed to match any schema with compatible: ['microchip,sam9x7-pmecc', 'atmel,at91sam9g45-pmecc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ecc-engine@ffffe000: failed to match any schema with compatible: ['microchip,sam9x7-pmecc', 'atmel,at91sam9g45-pmecc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/mpddrc@ffffe800: failed to match any schema with compatible: ['microchip,sam9x7-ddramc', 'atmel,sama5d3-ddramc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/mpddrc@ffffe800: failed to match any schema with compatible: ['microchip,sam9x7-ddramc', 'atmel,sama5d3-ddramc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/smc@ffffea00: failed to match any schema with compatible: ['microchip,sam9x7-smc', 'atmel,at91sam9260-smc', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/smc@ffffea00: failed to match any schema with compatible: ['microchip,sam9x7-smc', 'atmel,at91sam9260-smc', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-pinctrl', 'microchip,sam9x60-pinctrl', 'simple-mfd']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-pinctrl', 'microchip,sam9x60-pinctrl', 'simple-mfd']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff600: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff600: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff600: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff800: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff800: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff800: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffffa00: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffffa00: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffffa00: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/syscon@fffffe60: failed to match any schema with compatible: ['microchip,sam9x7-gpbr', 'atmel,at91sam9260-gpbr', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/syscon@fffffe60: failed to match any schema with compatible: ['microchip,sam9x7-gpbr', 'atmel,at91sam9260-gpbr', 'syscon']