* [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-07 13:58 ` Krzysztof Kozlowski
2024-07-05 9:09 ` [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine Liu Ying
` (9 subsequent siblings)
10 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces.
Document some processing units to support two display outputs.
ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend processing units
are in pixel engine. FrameGen and TCon processing units are in display
engine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
.../imx/fsl,imx8qxp-dc-constframe.yaml | 51 +++++++
.../display/imx/fsl,imx8qxp-dc-extdst.yaml | 79 +++++++++++
.../imx/fsl,imx8qxp-dc-fetchlayer.yaml | 37 ++++++
.../imx/fsl,imx8qxp-dc-fetchunit-common.yaml | 125 ++++++++++++++++++
.../display/imx/fsl,imx8qxp-dc-fetchwarp.yaml | 37 ++++++
.../display/imx/fsl,imx8qxp-dc-framegen.yaml | 71 ++++++++++
.../imx/fsl,imx8qxp-dc-layerblend.yaml | 46 +++++++
.../display/imx/fsl,imx8qxp-dc-tcon.yaml | 41 ++++++
8 files changed, 487 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
new file mode 100644
index 000000000000..80f826289309
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-constframe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Constant Frame
+
+description: |
+ The Constant Frame unit is used instead of a Fetch unit where generation of
+ constant color frames only is sufficient. This is the case for the background
+ planes of content and safety streams in a Display Controller.
+
+ The color can be setup to any RGBA value.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-constframe
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: pec
+ - const: cfg
+
+ fsl,dc-cf-id:
+ description: Constant Frame unit instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 4, 5]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - fsl,dc-cf-id
+
+additionalProperties: false
+
+examples:
+ - |
+ constframe@56180960 {
+ compatible = "fsl,imx8qxp-dc-constframe";
+ reg = <0x56180960 0x3>, <0x56184400 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-cf-id = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
new file mode 100644
index 000000000000..45957db3aadf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-extdst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller External Destination Interface
+
+description: |
+ The External Destination unit is the interface between the internal pixel
+ processing pipeline of the Pixel Engine, which is 30-bit RGB plus 8-bit Alpha,
+ and a Display Engine.
+
+ It comprises the following built-in Gamma apply function.
+
+ +------X-----------------------+
+ | | ExtDst Unit |
+ | V |
+ | +-------+ |
+ | | Gamma | |
+ | +-------+ |
+ | | |
+ | V +
+ +------X-----------------------+
+
+ The output format is 24-bit RGB plus 1-bit Alpha. Conversion from 10 to 8
+ bits is done by LSBit truncation. Alpha output bit is 1 for input 255, 0
+ otherwise.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-extdst
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: pec
+ - const: cfg
+
+ interrupts:
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: shdload
+ - const: framecomplete
+ - const: seqcomplete
+
+ fsl,dc-ed-id:
+ description: External Destination unit instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 4, 5]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - fsl,dc-ed-id
+
+additionalProperties: false
+
+examples:
+ - |
+ extdst@56180980 {
+ compatible = "fsl,imx8qxp-dc-extdst";
+ reg = <0x56180980 0x7>, <0x56184800 0x400>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <3>, <4>, <5>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ fsl,dc-ed-id = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
new file mode 100644
index 000000000000..d459573828ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Fetchlayer
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+allOf:
+ - $ref: fsl,imx8qxp-dc-fetchunit-common.yaml#
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-fetchlayer
+
+ fsl,dc-fl-id:
+ description: Fetchlayer unit instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ const: 0
+
+required:
+ - compatible
+ - fsl,dc-fl-id
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ fetchlayer@56180ac0 {
+ compatible = "fsl,imx8qxp-dc-fetchlayer";
+ reg = <0x56180ac0 0x3>, <0x56188400 0x800>;
+ reg-names = "pec", "cfg";
+ fsl,dc-fl-id = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
new file mode 100644
index 000000000000..a7a568672dc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Fetch Unit
+
+description: |
+ The Fetch Unit is the interface between the AXI bus for source buffer access
+ and the internal pixel processing pipeline, which is 30-bit RGB plus 8-bit
+ Alpha.
+
+ It is used to generate foreground planes in Display Controllers and source
+ planes in Blit Engines, and comprises the following built-in functions to
+ convert a wide range of frame buffer types.
+
+ +---------X-----------------------------------------+
+ | | Fetch Unit |
+ | V |
+ | +---------+ |
+ | | | |
+ | | Decode | Decompression [Decode] |
+ | | | |
+ | +---------+ |
+ | | |
+ | V |
+ | +---------+ |
+ | | Clip & | Clip Window [All] |
+ | | Overlay | Plane composition [Layer, Warp] |
+ | | | |
+ | +---------+ |
+ | | |
+ | V |
+ | +---------+ |
+ | | Re- | Flip/Rotate/Repl./Drop [All] |
+ X--> | sample | Perspective/Affine warping [Persp] |
+ | | | | Arbitrary warping [Warp, Persp] |
+ | | +---------+ |
+ | | | |
+ | | V |
+ | | +---------+ |
+ | | | | |
+ | | | Palette | Color Palette [Layer, Decode] |
+ | | | | |
+ | | +---------+ |
+ | | | |
+ | | V |
+ | | +---------+ |
+ | | | Extract | Raw to RGBA/YUV [All] |
+ | | | & | Bit width expansion [All] |
+ | | | Expand | |
+ | | +---------+ |
+ | | | |
+ | | V |
+ | | +---------+ |
+ | | | | Planar to packed |
+ | |->| Combine | [Decode, Warp, Persp] |
+ | | | | |
+ | | +---------+ |
+ | | | |
+ | | V |
+ | | +---------+ |
+ | | | | YUV422 to YUV444 |
+ | | | Chroma | [Decode, Persp] |
+ | | | | |
+ | | +---------+ |
+ | | | |
+ | | V |
+ | | +---------+ |
+ | | | | YUV to RGB |
+ | | | Color | [Warp, Persp, Decode, Layer] |
+ | | | | |
+ | | +---------+ |
+ | | | |
+ | | V |
+ | | +---------+ |
+ | | | | Gamma removal |
+ | | | Gamma | [Warp, Persp, Decode, Layer] |
+ | | | | |
+ | | +---------+ |
+ | | | |
+ | | V |
+ | | +---------+ |
+ | | | | Alpla multiply, RGB pre-multiply |
+ | ->| Multiply| [Warp, Persp, Decode, Layer] |
+ | | | |
+ | --------- |
+ | | |
+ | V |
+ | +---------+ |
+ | | | Bilinear filter |
+ | | Filter | [Warp, Persp] |
+ | | | |
+ | +---------+ |
+ | | |
+ | V |
+ +---------X-----------------------------------------+
+
+ Note that different derivatives of the Fetch Unit exist. Each implements a
+ specific subset only of the pipeline stages shown above. Restrictions for the
+ units are specified in [square brackets].
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: pec
+ - const: cfg
+
+ fsl,prg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Optional Prefetch Resolve Gasket associated with the Fetch Unit.
+
+required:
+ - reg
+ - reg-names
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
new file mode 100644
index 000000000000..5613f84e6112
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Fetchwarp
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+allOf:
+ - $ref: fsl,imx8qxp-dc-fetchunit-common.yaml#
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-fetchwarp
+
+ fsl,dc-fw-id:
+ description: Fetchwarp unit instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [2, 9]
+
+required:
+ - compatible
+ - fsl,dc-fw-id
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ fetchwarp@56180a60 {
+ compatible = "fsl,imx8qxp-dc-fetchwarp";
+ reg = <0x56180a60 0x4>, <0x56186400 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-fw-id = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
new file mode 100644
index 000000000000..3fe666f35a1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-framegen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Frame Generator
+
+description:
+ The Frame Generator (FrameGen) module generates a programmable video timing
+ and optionally allows to synchronize the generated video timing to external
+ synchronization signals.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-framegen
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: int0
+ - const: int1
+ - const: int2
+ - const: int3
+ - const: primsync_on
+ - const: primsync_off
+ - const: secsync_on
+ - const: secsync_off
+
+ fsl,dc-fg-id:
+ description: Frame Generator unit instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - interrupt-names
+ - fsl,dc-fg-id
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+
+ framegen@5618b800 {
+ compatible = "fsl,imx8qxp-dc-framegen";
+ reg = <0x5618b800 0x400>;
+ clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
+ interrupt-names = "int0", "int1", "int2", "int3",
+ "primsync_on", "primsync_off",
+ "secsync_on", "secsync_off";
+ fsl,dc-fg-id = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
new file mode 100644
index 000000000000..7da26d5859d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-layerblend.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Layer Blend Unit
+
+description: Combines two input frames to a single output frame.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-layerblend
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: pec
+ - const: cfg
+
+ fsl,dc-lb-id:
+ description: Layer Blend unit instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - fsl,dc-lb-id
+
+additionalProperties: false
+
+examples:
+ - |
+ layerblend@56180ba0 {
+ compatible = "fsl,imx8qxp-dc-layerblend";
+ reg = <0x56180ba0 0x4>, <0x5618a400 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-lb-id = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
new file mode 100644
index 000000000000..32a57de1038d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-tcon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Timing Controller
+
+description:
+ The TCon can generate a wide range of customized synchronization signals and
+ does the mapping of the color bits to the output.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-tcon
+
+ reg:
+ maxItems: 1
+
+ fsl,dc-tc-id:
+ description: Timing Controller unit instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+ - fsl,dc-tc-id
+
+additionalProperties: false
+
+examples:
+ - |
+ tcon@5618c800 {
+ compatible = "fsl,imx8qxp-dc-tcon";
+ reg = <0x5618c800 0x800>;
+ fsl,dc-tc-id = <0>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units
2024-07-05 9:09 ` [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units Liu Ying
@ 2024-07-07 13:58 ` Krzysztof Kozlowski
2024-07-08 6:30 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-07 13:58 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 05/07/2024 11:09, Liu Ying wrote:
> Freescale i.MX8qxp Display Controller is implemented as construction set of
> building blocks with unified concept and standardized interfaces.
>
> Document some processing units to support two display outputs.
> +maintainers:
> + - Liu Ying <victor.liu@nxp.com>
> +
> +properties:
> + compatible:
> + const: fsl,imx8qxp-dc-tcon
> +
> + reg:
> + maxItems: 1
> +
> + fsl,dc-tc-id:
> + description: Timing Controller unit instance number
No instance numbering. This applies to your entire patchset.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units
2024-07-07 13:58 ` Krzysztof Kozlowski
@ 2024-07-08 6:30 ` Liu Ying
2024-07-08 20:04 ` Rob Herring
0 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-08 6:30 UTC (permalink / raw)
To: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> Freescale i.MX8qxp Display Controller is implemented as construction set of
>> building blocks with unified concept and standardized interfaces.
>>
>> Document some processing units to support two display outputs.
>
>
>> +maintainers:
>> + - Liu Ying <victor.liu@nxp.com>
>> +
>> +properties:
>> + compatible:
>> + const: fsl,imx8qxp-dc-tcon
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + fsl,dc-tc-id:
>> + description: Timing Controller unit instance number
>
> No instance numbering. This applies to your entire patchset.
Then, I'll call of_alias_get_id() from the drivers to get
instance number instead.
As i.MX8qm SoC embeds two Display Controllers, the alias
stem would contain the Display Controller instance
number, like "dc0-tcon" and "dc1-tcon". Is this ok?
>
>
>
> Best regards,
> Krzysztof
>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units
2024-07-08 6:30 ` Liu Ying
@ 2024-07-08 20:04 ` Rob Herring
2024-07-09 7:36 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Rob Herring @ 2024-07-08 20:04 UTC (permalink / raw)
To: Liu Ying
Cc: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel, p.zabel, airlied, daniel, maarten.lankhorst,
mripard, tzimmermann, krzk+dt, conor+dt, shawnguo, s.hauer,
kernel, festevam, tglx
On Mon, Jul 08, 2024 at 02:30:37PM +0800, Liu Ying wrote:
> On 07/07/2024, Krzysztof Kozlowski wrote:
> > On 05/07/2024 11:09, Liu Ying wrote:
> >> Freescale i.MX8qxp Display Controller is implemented as construction set of
> >> building blocks with unified concept and standardized interfaces.
> >>
> >> Document some processing units to support two display outputs.
> >
> >
> >> +maintainers:
> >> + - Liu Ying <victor.liu@nxp.com>
> >> +
> >> +properties:
> >> + compatible:
> >> + const: fsl,imx8qxp-dc-tcon
> >> +
> >> + reg:
> >> + maxItems: 1
> >> +
> >> + fsl,dc-tc-id:
> >> + description: Timing Controller unit instance number
> >
> > No instance numbering. This applies to your entire patchset.
>
> Then, I'll call of_alias_get_id() from the drivers to get
> instance number instead.
Ideally, no.
> As i.MX8qm SoC embeds two Display Controllers, the alias
> stem would contain the Display Controller instance
> number, like "dc0-tcon" and "dc1-tcon". Is this ok?
The format of aliases is fooN, so no. Aliases should also be generic
rather than vendor specific.
If you need to describe the connection of components in the display
pipeline, then use the graph binding.
Rob
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units
2024-07-08 20:04 ` Rob Herring
@ 2024-07-09 7:36 ` Liu Ying
0 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-09 7:36 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel, p.zabel, airlied, daniel, maarten.lankhorst,
mripard, tzimmermann, krzk+dt, conor+dt, shawnguo, s.hauer,
kernel, festevam, tglx
On 07/09/2024, Rob Herring wrote:
> On Mon, Jul 08, 2024 at 02:30:37PM +0800, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
>>>> Freescale i.MX8qxp Display Controller is implemented as construction set of
>>>> building blocks with unified concept and standardized interfaces.
>>>>
>>>> Document some processing units to support two display outputs.
>>>
>>>
>>>> +maintainers:
>>>> + - Liu Ying <victor.liu@nxp.com>
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: fsl,imx8qxp-dc-tcon
>>>> +
>>>> + reg:
>>>> + maxItems: 1
>>>> +
>>>> + fsl,dc-tc-id:
>>>> + description: Timing Controller unit instance number
>>>
>>> No instance numbering. This applies to your entire patchset.
>>
>> Then, I'll call of_alias_get_id() from the drivers to get
>> instance number instead.
>
> Ideally, no.
>
>> As i.MX8qm SoC embeds two Display Controllers, the alias
>> stem would contain the Display Controller instance
>> number, like "dc0-tcon" and "dc1-tcon". Is this ok?
>
> The format of aliases is fooN, so no. Aliases should also be generic
> rather than vendor specific.
>
> If you need to describe the connection of components in the display
> pipeline, then use the graph binding.
I mentioned OF graph in the previous patch set discussion.
"
There are 50+ individual DPU internal units and 20+ unit types.
Do you really mean that each unit should be a separate device in
device tree and each unit type should have it's own compatible
string ?
Almost all units have input/output ports to connect with each other.
Some units have multiple input/output options.
Should we use OF graph ports to tell the connections ?
"
https://lists.infradead.org/pipermail/linux-arm-kernel/2023-August/861811.html
I hope we don't end up using the graph binding, as there are too
many input/output options between processing units in the pixel engine,
e.g.,
"
Selection of the source for the sec input of the layerblend0 module
000000b - Unit layerblend0 input port sec is disabled
010100b - Unit layerblend0 input port sec is connected to output of unit fetchwarp2
010110b - Unit layerblend0 input port sec is connected to output of unit fetchdecode0
011000b - Unit layerblend0 input port sec is connected to output of unit fetchdecode1
011010b - Unit layerblend0 input port sec is connected to output of unit fetchlayer0
011011b - Unit layerblend0 input port sec is connected to output of unit matrix4
011100b - Unit layerblend0 input port sec is connected to output of unit hscaler4
011101b - Unit layerblend0 input port sec is connected to output of unit vscaler4
011110b - Unit layerblend0 input port sec is connected to output of unit matrix5
011111b - Unit layerblend0 input port sec is connected to output of unit hscaler5
100000b - Unit layerblend0 input port sec is connected to output of unit vscaler5
Selection of the source for the prim input of the layerblend0 module
000000b - Unit layerblend0 input port prim is disabled
000000b - Unit layerblend0 input port prim is connected to output of unit constframe1
001010b - Unit layerblend0 input port prim is connected to output of unit blitblend9
001100b - Unit layerblend0 input port prim is connected to output of unit constframe0
001110b - Unit layerblend0 input port prim is connected to output of unit constframe4
010010b - Unit layerblend0 input port prim is connected to output of unit constframe5
011011b - Unit layerblend0 input port prim is connected to output of unit matrix4
011100b - Unit layerblend0 input port prim is connected to output of unit hscaler4
011101b - Unit layerblend0 input port prim is connected to output of unit vscaler4
011110b - Unit layerblend0 input port prim is connected to output of unit matrix5
011111b - Unit layerblend0 input port prim is connected to output of unit hscaler5
100000b - Unit layerblend0 input port prim is connected to output of unit vscaler5
"
Also, Matrix, GammarCor and Dither in the display engine can be bypassed.
Matrix can be put at optional position(1 or 2). Signature can be tapped
after FrameGen, GammaCor, Matrix or Dither.
FrameGen -> Matrix(1) -> GammaCor -> Maxtrix(2) -> Dither -> TCon
Aside from the alias approach, another idea is to specify the instance
number in compatible string, like "fsl,imx8qxp-dc-constframe5", no?
>
> Rob
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
2024-07-05 9:09 ` [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-07 13:59 ` Krzysztof Kozlowski
2024-07-05 9:09 ` [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine Liu Ying
` (8 subsequent siblings)
10 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
.../imx/fsl,imx8qxp-dc-display-engine.yaml | 166 ++++++++++++++++++
1 file changed, 166 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
new file mode 100644
index 000000000000..dc9579897b76
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Display Engine
+
+description:
+ All Processing Units that operate in a display clock domain. Pixel pipeline
+ is driven by a video timing and cannot be stalled. Implements all display
+ specific processing.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-display-engine
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: top
+ - const: cfg
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: shdload
+ - const: framecomplete
+ - const: seqcomplete
+
+ power-domains:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ fsl,dc-de-id:
+ description: Display Engine instance number
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: video output
+
+patternProperties:
+ "^dither@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-dither
+
+ "^framegen@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-framegen
+
+ "^gammacor@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-gammacor
+
+ "^matrix@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-matrix
+
+ "^signature@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-signature
+
+ "^tcon@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-tcon
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - power-domains
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - fsl,dc-de-id
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+
+ display-engine@5618b400 {
+ compatible = "fsl,imx8qxp-dc-display-engine";
+ reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
+ reg-names = "top", "cfg";
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <15>, <16>, <17>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ fsl,dc-de-id = <0>;
+
+ framegen@5618b800 {
+ compatible = "fsl,imx8qxp-dc-framegen";
+ reg = <0x5618b800 0x400>;
+ clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
+ interrupt-names = "int0", "int1", "int2", "int3",
+ "primsync_on", "primsync_off",
+ "secsync_on", "secsync_off";
+ fsl,dc-fg-id = <0>;
+ };
+
+ tcon@5618c800 {
+ compatible = "fsl,imx8qxp-dc-tcon";
+ reg = <0x5618c800 0x800>;
+ fsl,dc-tc-id = <0>;
+ };
+
+ port {
+ dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
+ remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
2024-07-05 9:09 ` [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine Liu Ying
@ 2024-07-07 13:59 ` Krzysztof Kozlowski
2024-07-08 6:40 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-07 13:59 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 05/07/2024 11:09, Liu Ying wrote:
> i.MX8qxp Display Controller display engine consists of all processing units
> that operate in a display clock domain.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> .../imx/fsl,imx8qxp-dc-display-engine.yaml | 166 ++++++++++++++++++
> 1 file changed, 166 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
> new file mode 100644
> index 000000000000..dc9579897b76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
> @@ -0,0 +1,166 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qxp Display Controller Display Engine
> +
> +description:
> + All Processing Units that operate in a display clock domain. Pixel pipeline
> + is driven by a video timing and cannot be stalled. Implements all display
> + specific processing.
> +
> +maintainers:
> + - Liu Ying <victor.liu@nxp.com>
> +
> +properties:
> + compatible:
> + const: fsl,imx8qxp-dc-display-engine
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: top
> + - const: cfg
> +
> + resets:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 3
> +
> + interrupt-names:
> + items:
> + - const: shdload
> + - const: framecomplete
> + - const: seqcomplete
> +
> + power-domains:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> + fsl,dc-de-id:
> + description: Display Engine instance number
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
No, drop. For the same reason as earlier patch.
> +
> + port:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: video output
Eh, mixing children with and without addresses is considered poor design.
> +
> +patternProperties:
> + "^dither@[0-9a-f]+$":
> + type: object
> + additionalProperties: true
> +
> + properties:
> + compatible:
> + const: fsl,imx8qxp-dc-dither
> +
> + "^framegen@[0-9a-f]+$":
> + type: object
> + additionalProperties: true
> +
> + properties:
> + compatible:
> + const: fsl,imx8qxp-dc-framegen
> +
> + "^gammacor@[0-9a-f]+$":
This looks like you are organizing bindings per your driver architecture.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
2024-07-07 13:59 ` Krzysztof Kozlowski
@ 2024-07-08 6:40 ` Liu Ying
2024-07-08 14:04 ` Krzysztof Kozlowski
0 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-08 6:40 UTC (permalink / raw)
To: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller display engine consists of all processing units
>> that operate in a display clock domain.
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>> .../imx/fsl,imx8qxp-dc-display-engine.yaml | 166 ++++++++++++++++++
>> 1 file changed, 166 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
>> new file mode 100644
>> index 000000000000..dc9579897b76
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
>> @@ -0,0 +1,166 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Freescale i.MX8qxp Display Controller Display Engine
>> +
>> +description:
>> + All Processing Units that operate in a display clock domain. Pixel pipeline
>> + is driven by a video timing and cannot be stalled. Implements all display
>> + specific processing.
>> +
>> +maintainers:
>> + - Liu Ying <victor.liu@nxp.com>
>> +
>> +properties:
>> + compatible:
>> + const: fsl,imx8qxp-dc-display-engine
>> +
>> + reg:
>> + maxItems: 2
>> +
>> + reg-names:
>> + items:
>> + - const: top
>> + - const: cfg
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + interrupts:
>> + maxItems: 3
>> +
>> + interrupt-names:
>> + items:
>> + - const: shdload
>> + - const: framecomplete
>> + - const: seqcomplete
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 1
>> +
>> + ranges: true
>> +
>> + fsl,dc-de-id:
>> + description: Display Engine instance number
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + enum: [0, 1]
>
> No, drop. For the same reason as earlier patch.
Call of_alias_get_id() from the driver instead?
>
>> +
>> + port:
>> + $ref: /schemas/graph.yaml#/properties/port
>> + description: video output
>
> Eh, mixing children with and without addresses is considered poor design.
Will move this to the tcon child node as it is the
last processing unit in the display engine.
>
>> +
>> +patternProperties:
>> + "^dither@[0-9a-f]+$":
>> + type: object
>> + additionalProperties: true
>> +
>> + properties:
>> + compatible:
>> + const: fsl,imx8qxp-dc-dither
>> +
>> + "^framegen@[0-9a-f]+$":
>> + type: object
>> + additionalProperties: true
>> +
>> + properties:
>> + compatible:
>> + const: fsl,imx8qxp-dc-framegen
>> +
>> + "^gammacor@[0-9a-f]+$":
>
> This looks like you are organizing bindings per your driver architecture.
As I mentioned in cover letter, this series addresses Maxime's
comment for the previous series - split the display controller
into multiple internal devices. Maxime insisted on doing this.
>
> Best regards,
> Krzysztof
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
2024-07-08 6:40 ` Liu Ying
@ 2024-07-08 14:04 ` Krzysztof Kozlowski
2024-07-08 14:52 ` Maxime Ripard
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-08 14:04 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 08/07/2024 08:40, Liu Ying wrote:
>>> +
>>> + "^framegen@[0-9a-f]+$":
>>> + type: object
>>> + additionalProperties: true
>>> +
>>> + properties:
>>> + compatible:
>>> + const: fsl,imx8qxp-dc-framegen
>>> +
>>> + "^gammacor@[0-9a-f]+$":
>>
>> This looks like you are organizing bindings per your driver architecture.
>
> As I mentioned in cover letter, this series addresses Maxime's
> comment for the previous series - split the display controller
> into multiple internal devices. Maxime insisted on doing this.
But these are not separate devices. Look:
1. parent DC:
reg = <0x56180000 0x40000>;
2. child interrupt controller:
reg = <0x56180040 0x60>;
That address is within parent.
3. Then we go to things like:
reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
Still within parent's range and just few words in address range. That's
a clear indication that you choose few registers and call it a "device".
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
2024-07-08 14:04 ` Krzysztof Kozlowski
@ 2024-07-08 14:52 ` Maxime Ripard
2024-07-09 6:50 ` Krzysztof Kozlowski
0 siblings, 1 reply; 39+ messages in thread
From: Maxime Ripard @ 2024-07-08 14:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel, p.zabel, airlied, daniel, maarten.lankhorst,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, tglx
[-- Attachment #1: Type: text/plain, Size: 1346 bytes --]
On Mon, Jul 08, 2024 at 04:04:21PM GMT, Krzysztof Kozlowski wrote:
> On 08/07/2024 08:40, Liu Ying wrote:
> >>> +
> >>> + "^framegen@[0-9a-f]+$":
> >>> + type: object
> >>> + additionalProperties: true
> >>> +
> >>> + properties:
> >>> + compatible:
> >>> + const: fsl,imx8qxp-dc-framegen
> >>> +
> >>> + "^gammacor@[0-9a-f]+$":
> >>
> >> This looks like you are organizing bindings per your driver architecture.
> >
> > As I mentioned in cover letter, this series addresses Maxime's
> > comment for the previous series - split the display controller
> > into multiple internal devices. Maxime insisted on doing this.
>
> But these are not separate devices. Look:
> 1. parent DC:
> reg = <0x56180000 0x40000>;
>
> 2. child interrupt controller:
> reg = <0x56180040 0x60>;
>
> That address is within parent.
>
> 3. Then we go to things like:
> reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
>
> Still within parent's range and just few words in address range. That's
> a clear indication that you choose few registers and call it a "device".
That's never really been a metric though?
If not, one could just create a "soc" device node covering the entire
register map, and since it would overlap despite clearly defined
features, you would claim it's a single device?
Maxime
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
2024-07-08 14:52 ` Maxime Ripard
@ 2024-07-09 6:50 ` Krzysztof Kozlowski
2024-07-18 15:53 ` Maxime Ripard
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-09 6:50 UTC (permalink / raw)
To: Maxime Ripard
Cc: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel, p.zabel, airlied, daniel, maarten.lankhorst,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, tglx
On 08/07/2024 16:52, Maxime Ripard wrote:
> On Mon, Jul 08, 2024 at 04:04:21PM GMT, Krzysztof Kozlowski wrote:
>> On 08/07/2024 08:40, Liu Ying wrote:
>>>>> +
>>>>> + "^framegen@[0-9a-f]+$":
>>>>> + type: object
>>>>> + additionalProperties: true
>>>>> +
>>>>> + properties:
>>>>> + compatible:
>>>>> + const: fsl,imx8qxp-dc-framegen
>>>>> +
>>>>> + "^gammacor@[0-9a-f]+$":
>>>>
>>>> This looks like you are organizing bindings per your driver architecture.
>>>
>>> As I mentioned in cover letter, this series addresses Maxime's
>>> comment for the previous series - split the display controller
>>> into multiple internal devices. Maxime insisted on doing this.
>>
>> But these are not separate devices. Look:
>> 1. parent DC:
>> reg = <0x56180000 0x40000>;
>>
>> 2. child interrupt controller:
>> reg = <0x56180040 0x60>;
>>
>> That address is within parent.
>>
>> 3. Then we go to things like:
>> reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
>>
>> Still within parent's range and just few words in address range. That's
>> a clear indication that you choose few registers and call it a "device".
>
> That's never really been a metric though?
>
> If not, one could just create a "soc" device node covering the entire
> register map, and since it would overlap despite clearly defined
> features, you would claim it's a single device?
Since I do not create such one-address-soc devices, I claim I have
separate devices in the SoC. Here is not the case: there is a device
covering entire address space.
Soc is a good example, because components/blocks of the SoC are being
re-used among different SoCs. Is the case here?
BTW, it could be that some of the sub-devices here are worth to be
devices, I agree.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
2024-07-09 6:50 ` Krzysztof Kozlowski
@ 2024-07-18 15:53 ` Maxime Ripard
0 siblings, 0 replies; 39+ messages in thread
From: Maxime Ripard @ 2024-07-18 15:53 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel, p.zabel, airlied, daniel, maarten.lankhorst,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, tglx
[-- Attachment #1: Type: text/plain, Size: 2228 bytes --]
On Tue, Jul 09, 2024 at 08:50:35AM GMT, Krzysztof Kozlowski wrote:
> On 08/07/2024 16:52, Maxime Ripard wrote:
> > On Mon, Jul 08, 2024 at 04:04:21PM GMT, Krzysztof Kozlowski wrote:
> >> On 08/07/2024 08:40, Liu Ying wrote:
> >>>>> +
> >>>>> + "^framegen@[0-9a-f]+$":
> >>>>> + type: object
> >>>>> + additionalProperties: true
> >>>>> +
> >>>>> + properties:
> >>>>> + compatible:
> >>>>> + const: fsl,imx8qxp-dc-framegen
> >>>>> +
> >>>>> + "^gammacor@[0-9a-f]+$":
> >>>>
> >>>> This looks like you are organizing bindings per your driver architecture.
> >>>
> >>> As I mentioned in cover letter, this series addresses Maxime's
> >>> comment for the previous series - split the display controller
> >>> into multiple internal devices. Maxime insisted on doing this.
> >>
> >> But these are not separate devices. Look:
> >> 1. parent DC:
> >> reg = <0x56180000 0x40000>;
> >>
> >> 2. child interrupt controller:
> >> reg = <0x56180040 0x60>;
> >>
> >> That address is within parent.
> >>
> >> 3. Then we go to things like:
> >> reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
> >>
> >> Still within parent's range and just few words in address range. That's
> >> a clear indication that you choose few registers and call it a "device".
> >
> > That's never really been a metric though?
> >
> > If not, one could just create a "soc" device node covering the entire
> > register map, and since it would overlap despite clearly defined
> > features, you would claim it's a single device?
>
> Since I do not create such one-address-soc devices, I claim I have
> separate devices in the SoC. Here is not the case: there is a device
> covering entire address space.
>
> Soc is a good example, because components/blocks of the SoC are being
> re-used among different SoCs. Is the case here?
>
> BTW, it could be that some of the sub-devices here are worth to be
> devices, I agree.
This was the binding of the previous version:
https://lore.kernel.org/dri-devel/20230822085949.816844-2-victor.liu@nxp.com/
To me, the duplication of interrupts, clocks and power domains with
different indices kind of proves that it's all separate devices
Maxime
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
2024-07-05 9:09 ` [PATCH 01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units Liu Ying
2024-07-05 9:09 ` [PATCH 02/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-07 14:02 ` Krzysztof Kozlowski
2024-07-05 9:09 ` [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller Liu Ying
` (7 subsequent siblings)
10 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
.../imx/fsl,imx8qxp-dc-pixel-engine.yaml | 264 ++++++++++++++++++
1 file changed, 264 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
new file mode 100644
index 000000000000..29dd7bac6f7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
@@ -0,0 +1,264 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Pixel Engine
+
+description:
+ All Processing Units that operate in the AXI bus clock domain. Pixel
+ pipelines have the ability to stall when a destination is busy. Implements
+ all communication to memory resources and most of the image processing
+ functions. Interconnection of Processing Units is re-configurable.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-pixel-engine
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^blit-engine@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-blit-engine
+
+ "^constframe@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-constframe
+
+ "^extdst@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-extdst
+
+ "^fetchdecode@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-fetchdecode
+
+ "^fetcheco@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-fetcheco
+
+ "^fetchlayer@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-fetchlayer
+
+ "^fetchwarp@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-fetchwarp
+
+ "^hscaler@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-hscaler
+
+ "^layerblend@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-layerblend
+
+ "^matrix@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-matrix
+
+ "^safety@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-safety
+
+ "^vscaler@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-vscaler
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+
+ pixel-engine@56180800 {
+ compatible = "fsl,imx8qxp-dc-pixel-engine";
+ reg = <0x56180800 0xac00>;
+ clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ constframe@56180960 {
+ compatible = "fsl,imx8qxp-dc-constframe";
+ reg = <0x56180960 0x3>, <0x56184400 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-cf-id = <0>;
+ };
+
+ extdst@56180980 {
+ compatible = "fsl,imx8qxp-dc-extdst";
+ reg = <0x56180980 0x7>, <0x56184800 0x400>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <3>, <4>, <5>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ fsl,dc-ed-id = <0>;
+ };
+
+ constframe@561809a0 {
+ compatible = "fsl,imx8qxp-dc-constframe";
+ reg = <0x561809a0 0x3>, <0x56184c00 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-cf-id = <4>;
+ };
+
+ extdst@561809c0 {
+ compatible = "fsl,imx8qxp-dc-extdst";
+ reg = <0x561809c0 0x7>, <0x56185000 0x400>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <6>, <7>, <8>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ fsl,dc-ed-id = <4>;
+ };
+
+ constframe@561809e0 {
+ compatible = "fsl,imx8qxp-dc-constframe";
+ reg = <0x561809e0 0x3>, <0x56185400 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-cf-id = <1>;
+ };
+
+ extdst@56180a00 {
+ compatible = "fsl,imx8qxp-dc-extdst";
+ reg = <0x56180a00 0x7>, <0x56185800 0x400>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <9>, <10>, <11>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ fsl,dc-ed-id = <1>;
+ };
+
+ constframe@56180a20 {
+ compatible = "fsl,imx8qxp-dc-constframe";
+ reg = <0x56180a20 0x3>, <0x56185c00 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-cf-id = <5>;
+ };
+
+ extdst@56180a40 {
+ compatible = "fsl,imx8qxp-dc-extdst";
+ reg = <0x56180a40 0x7>, <0x56186000 0x400>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <12>, <13>, <14>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ fsl,dc-ed-id = <5>;
+ };
+
+ fetchwarp@56180a60 {
+ compatible = "fsl,imx8qxp-dc-fetchwarp";
+ reg = <0x56180a60 0x4>, <0x56186400 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-fw-id = <2>;
+ };
+
+ fetchlayer@56180ac0 {
+ compatible = "fsl,imx8qxp-dc-fetchlayer";
+ reg = <0x56180ac0 0x3>, <0x56188400 0x800>;
+ reg-names = "pec", "cfg";
+ fsl,dc-fl-id = <0>;
+ };
+
+ layerblend@56180ba0 {
+ compatible = "fsl,imx8qxp-dc-layerblend";
+ reg = <0x56180ba0 0x4>, <0x5618a400 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-lb-id = <0>;
+ };
+
+ layerblend@56180bc0 {
+ compatible = "fsl,imx8qxp-dc-layerblend";
+ reg = <0x56180bc0 0x4>, <0x5618a800 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-lb-id = <1>;
+ };
+
+ layerblend@56180be0 {
+ compatible = "fsl,imx8qxp-dc-layerblend";
+ reg = <0x56180be0 0x4>, <0x5618ac00 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-lb-id = <2>;
+ };
+
+ layerblend@56180c00 {
+ compatible = "fsl,imx8qxp-dc-layerblend";
+ reg = <0x56180c00 0x4>, <0x5618b000 0x400>;
+ reg-names = "pec", "cfg";
+ fsl,dc-lb-id = <3>;
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
2024-07-05 9:09 ` [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine Liu Ying
@ 2024-07-07 14:02 ` Krzysztof Kozlowski
2024-07-08 6:47 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-07 14:02 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 05/07/2024 11:09, Liu Ying wrote:
> i.MX8qxp Display Controller pixel engine consists of all processing units
> that operate in the AXI bus clock domain. Command sequencer and interrupt
> controller of the Display Controller work with AXI bus clock, but they are
> not in pixel engine.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> +
> + extdst@56180a40 {
> + compatible = "fsl,imx8qxp-dc-extdst";
> + reg = <0x56180a40 0x7>, <0x56186000 0x400>;
> + reg-names = "pec", "cfg";
> + interrupt-parent = <&dc0_intc>;
> + interrupts = <12>, <13>, <14>;
> + interrupt-names = "shdload", "framecomplete", "seqcomplete";
> + fsl,dc-ed-id = <5>;
> + };
> +
> + fetchwarp@56180a60 {
> + compatible = "fsl,imx8qxp-dc-fetchwarp";
> + reg = <0x56180a60 0x4>, <0x56186400 0x400>;
Aha, one word for address range.
Sorry, these are not separate devices.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
2024-07-07 14:02 ` Krzysztof Kozlowski
@ 2024-07-08 6:47 ` Liu Ying
2024-07-08 14:05 ` Krzysztof Kozlowski
0 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-08 6:47 UTC (permalink / raw)
To: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller pixel engine consists of all processing units
>> that operate in the AXI bus clock domain. Command sequencer and interrupt
>> controller of the Display Controller work with AXI bus clock, but they are
>> not in pixel engine.
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>
>
>> +
>> + extdst@56180a40 {
>> + compatible = "fsl,imx8qxp-dc-extdst";
>> + reg = <0x56180a40 0x7>, <0x56186000 0x400>;
>> + reg-names = "pec", "cfg";
>> + interrupt-parent = <&dc0_intc>;
>> + interrupts = <12>, <13>, <14>;
>> + interrupt-names = "shdload", "framecomplete", "seqcomplete";
>> + fsl,dc-ed-id = <5>;
>> + };
>> +
>> + fetchwarp@56180a60 {
>> + compatible = "fsl,imx8qxp-dc-fetchwarp";
>> + reg = <0x56180a60 0x4>, <0x56186400 0x400>;
>
> Aha, one word for address range.
Sorry, I don't get your idea here.
>
> Sorry, these are not separate devices.
Hmm, again, Maxime suggested to use separate devices.
>
> Best regards,
> Krzysztof
>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
2024-07-08 6:47 ` Liu Ying
@ 2024-07-08 14:05 ` Krzysztof Kozlowski
2024-07-09 6:50 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-08 14:05 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 08/07/2024 08:47, Liu Ying wrote:
> On 07/07/2024, Krzysztof Kozlowski wrote:
>> On 05/07/2024 11:09, Liu Ying wrote:
>>> i.MX8qxp Display Controller pixel engine consists of all processing units
>>> that operate in the AXI bus clock domain. Command sequencer and interrupt
>>> controller of the Display Controller work with AXI bus clock, but they are
>>> not in pixel engine.
>>>
>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>> ---
>>
>>
>>> +
>>> + extdst@56180a40 {
>>> + compatible = "fsl,imx8qxp-dc-extdst";
>>> + reg = <0x56180a40 0x7>, <0x56186000 0x400>;
>>> + reg-names = "pec", "cfg";
>>> + interrupt-parent = <&dc0_intc>;
>>> + interrupts = <12>, <13>, <14>;
>>> + interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> + fsl,dc-ed-id = <5>;
>>> + };
>>> +
>>> + fetchwarp@56180a60 {
>>> + compatible = "fsl,imx8qxp-dc-fetchwarp";
>>> + reg = <0x56180a60 0x4>, <0x56186400 0x400>;
>>
>> Aha, one word for address range.
>
> Sorry, I don't get your idea here.
How many words are in the first IO address range?
One.
That is not a separate device.
>
>>
>> Sorry, these are not separate devices.
>
> Hmm, again, Maxime suggested to use separate devices.
To some level you can create separate devices, but for one register?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
2024-07-08 14:05 ` Krzysztof Kozlowski
@ 2024-07-09 6:50 ` Liu Ying
0 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-09 6:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/08/2024, Krzysztof Kozlowski wrote:
> On 08/07/2024 08:47, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
>>>> i.MX8qxp Display Controller pixel engine consists of all processing units
>>>> that operate in the AXI bus clock domain. Command sequencer and interrupt
>>>> controller of the Display Controller work with AXI bus clock, but they are
>>>> not in pixel engine.
>>>>
>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>> ---
>>>
>>>
>>>> +
>>>> + extdst@56180a40 {
>>>> + compatible = "fsl,imx8qxp-dc-extdst";
>>>> + reg = <0x56180a40 0x7>, <0x56186000 0x400>;
>>>> + reg-names = "pec", "cfg";
>>>> + interrupt-parent = <&dc0_intc>;
>>>> + interrupts = <12>, <13>, <14>;
>>>> + interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>>> + fsl,dc-ed-id = <5>;
>>>> + };
>>>> +
>>>> + fetchwarp@56180a60 {
>>>> + compatible = "fsl,imx8qxp-dc-fetchwarp";
>>>> + reg = <0x56180a60 0x4>, <0x56186400 0x400>;
>>>
>>> Aha, one word for address range.
>>
>> Sorry, I don't get your idea here.
>
> How many words are in the first IO address range?
>
> One.
My bad, the address range should be corrected to
reg = <0x56180a60 0x10>, <0x56186400 0x190>;
Though only 4 words in the first IO address range.
>
> That is not a separate device.
Each processing unit in pixel engine has two IO address
ranges - "pec" and "cfg".
"pec" stands for Pixel Engine Configuration where pixel
engine related stuff is controlled by 4 registers(4 words
in all) - LockUnlock, LockStatus, Dynamic and Status registers.
The first two provide lock and/or privilege protection to this
address block. The last two control/report connection from/to
other processing units.
"cfg" IO address range controls processing unit specific
functions.
As each processing unit has specific functions, it's not
unacceptable to take it as a separate device with it's own
IO address ranges. However, frankly speaking, I'm ok with
the idea of not splitting the main display controller into
multiple devices, but taking it as one single device.
>
>>
>>>
>>> Sorry, these are not separate devices.
>>
>> Hmm, again, Maxime suggested to use separate devices.
>
> To some level you can create separate devices, but for one register?
There are two IO address ranges, so at least a few registers.
Especially, the "cfg" range kind of hints that they could be
taken as separate devices, as it controls specific functions.
>
> Best regards,
> Krzysztof
>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (2 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-07 14:01 ` Krzysztof Kozlowski
2024-07-05 9:09 ` [PATCH 05/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller Liu Ying
` (6 subsequent siblings)
10 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
.../fsl,imx8qxp-dc-intc.yaml | 321 ++++++++++++++++++
1 file changed, 321 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
new file mode 100644
index 000000000000..3d0d11def505
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
@@ -0,0 +1,321 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller interrupt controller
+
+description: |
+ The Display Controller has a built-in interrupt controller with the following
+ features for all relevant HW events:
+
+ * Enable bit (mask)
+ * Status bit (set by an HW event)
+ * Preset bit (can be used by SW to set status)
+ * Clear bit (used by SW to reset the status)
+
+ Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
+ Alternatively the un-masked trigger signals for all HW events are provided,
+ allowing it to use a global interrupt controller instead.
+
+ Each interrupt can be protected against SW running in user mode. In that case,
+ only privileged AHB access can control the interrupt status.
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc-intc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupts:
+ items:
+ - description: |
+ store9 shadow load interrupt(blit engine)
+ - description: |
+ store9 frame complete interrupt(blit engine)
+ - description: |
+ store9 sequence complete interrupt(blit engine)
+ - description: |
+ extdst0 shadow load interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 frame complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 sequence complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst4 shadow load interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 frame complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 sequence complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst1 shadow load interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 frame complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 sequence complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst5 shadow load interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 frame complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 sequence complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ disengcfg0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 frame complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 sequence complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt0
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt1
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt2
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt3
+ (display controller, display stream 0)
+ - description: |
+ signature0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 measurement valid interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 error condition interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 frame complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 sequence complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt0
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt1
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt2
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt3
+ (display controller, display stream 1)
+ - description: |
+ signature1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 measurement valid interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 error condition interrupt
+ (display controller, display stream 1)
+ - description: reserved
+ - description: |
+ command sequencer error condition interrupt(command sequencer)
+ - description: |
+ common control software interrupt0(common control)
+ - description: |
+ common control software interrupt1(common control)
+ - description: |
+ common control software interrupt2(common control)
+ - description: |
+ common control software interrupt3(common control)
+ - description: |
+ framegen0 synchronization status activated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 synchronization status deactivated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 synchronization status activated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen0 synchronization status deactivated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen1 synchronization status activated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 synchronization status deactivated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 synchronization status activated interrupt
+ (display controller, content stream 1)
+ - description: |
+ framegen1 synchronization status deactivated interrupt
+ (display controller, content stream 1)
+ minItems: 49
+
+ interrupt-names:
+ items:
+ - const: store9_shdload
+ - const: store9_framecomplete
+ - const: store9_seqcomplete
+ - const: extdst0_shdload
+ - const: extdst0_framecomplete
+ - const: extdst0_seqcomplete
+ - const: extdst4_shdload
+ - const: extdst4_framecomplete
+ - const: extdst4_seqcomplete
+ - const: extdst1_shdload
+ - const: extdst1_framecomplete
+ - const: extdst1_seqcomplete
+ - const: extdst5_shdload
+ - const: extdst5_framecomplete
+ - const: extdst5_seqcomplete
+ - const: disengcfg_shdload0
+ - const: disengcfg_framecomplete0
+ - const: disengcfg_seqcomplete0
+ - const: framegen0_int0
+ - const: framegen0_int1
+ - const: framegen0_int2
+ - const: framegen0_int3
+ - const: sig0_shdload
+ - const: sig0_valid
+ - const: sig0_error
+ - const: disengcfg_shdload1
+ - const: disengcfg_framecomplete1
+ - const: disengcfg_seqcomplete1
+ - const: framegen1_int0
+ - const: framegen1_int1
+ - const: framegen1_int2
+ - const: framegen1_int3
+ - const: sig1_shdload
+ - const: sig1_valid
+ - const: sig1_error
+ - const: reserved
+ - const: cmdseq_error
+ - const: comctrl_sw0
+ - const: comctrl_sw1
+ - const: comctrl_sw2
+ - const: comctrl_sw3
+ - const: framegen0_primsync_on
+ - const: framegen0_primsync_off
+ - const: framegen0_secsync_on
+ - const: framegen0_secsync_off
+ - const: framegen1_primsync_on
+ - const: framegen1_primsync_off
+ - const: framegen1_secsync_on
+ - const: framegen1_secsync_off
+ minItems: 49
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+
+ interrupt-controller@56180040 {
+ compatible = "fsl,imx8qxp-dc-intc";
+ reg = <0x56180040 0x60>;
+ clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+ interrupt-controller;
+ interrupt-parent = <&dc0_irqsteer>;
+ #interrupt-cells = <1>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <5>,
+ <0>, <1>, <2>, <3>,
+ <4>, <82>, <83>, <84>,
+ <85>, <209>, <210>, <211>,
+ <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "reserved",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2024-07-05 9:09 ` [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller Liu Ying
@ 2024-07-07 14:01 ` Krzysztof Kozlowski
2024-07-08 6:51 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-07 14:01 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 05/07/2024 11:09, Liu Ying wrote:
> i.MX8qxp Display Controller has a built-in interrupt controller to support
> Enable/Status/Preset/Clear interrupt bit.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> .../fsl,imx8qxp-dc-intc.yaml | 321 ++++++++++++++++++
> 1 file changed, 321 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
> new file mode 100644
> index 000000000000..3d0d11def505
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
> @@ -0,0 +1,321 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qxp Display Controller interrupt controller
> +
> +description: |
> + The Display Controller has a built-in interrupt controller with the following
> + features for all relevant HW events:
> +
> + * Enable bit (mask)
> + * Status bit (set by an HW event)
> + * Preset bit (can be used by SW to set status)
> + * Clear bit (used by SW to reset the status)
1. Why this is split from the main node?
2. Who can use this interrupt controller? Children of your display unit?
Then it is not really a separate device, is it?
> +properties:
> + compatible:
> + const: fsl,imx8qxp-dc-intc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 1
> +
> + interrupts:
> + items:
> + - description: |
Do not need '|' unless you need to preserve formatting.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2024-07-07 14:01 ` Krzysztof Kozlowski
@ 2024-07-08 6:51 ` Liu Ying
2024-07-08 14:09 ` Krzysztof Kozlowski
0 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-08 6:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller has a built-in interrupt controller to support
>> Enable/Status/Preset/Clear interrupt bit.
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>> .../fsl,imx8qxp-dc-intc.yaml | 321 ++++++++++++++++++
>> 1 file changed, 321 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>> new file mode 100644
>> index 000000000000..3d0d11def505
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>> @@ -0,0 +1,321 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Freescale i.MX8qxp Display Controller interrupt controller
>> +
>> +description: |
>> + The Display Controller has a built-in interrupt controller with the following
>> + features for all relevant HW events:
>> +
>> + * Enable bit (mask)
>> + * Status bit (set by an HW event)
>> + * Preset bit (can be used by SW to set status)
>> + * Clear bit (used by SW to reset the status)
>
> 1. Why this is split from the main node?
Maxime suggested to do so:
"
But at least the CRTC and the interrupt controller should be split away,
or explained and detailed far better than "well it's just convenient".
"
https://lore.kernel.org/lkml/2k3cc3yfwqlpquxrdmzmaafz55b3lnqomzxjsvtetfriliqj3k@tv6uh7dzc2ea/
>
> 2. Who can use this interrupt controller? Children of your display unit?
Yes, only devices in the main display controller use it.
> Then it is not really a separate device, is it?
Er, per Maxime, it is a separate device.
>
>> +properties:
>> + compatible:
>> + const: fsl,imx8qxp-dc-intc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + interrupt-controller: true
>> +
>> + "#interrupt-cells":
>> + const: 1
>> +
>> + interrupts:
>> + items:
>> + - description: |
>
> Do not need '|' unless you need to preserve formatting.
Will do.
>
>
>
> Best regards,
> Krzysztof
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2024-07-08 6:51 ` Liu Ying
@ 2024-07-08 14:09 ` Krzysztof Kozlowski
2024-07-09 7:05 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-08 14:09 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 08/07/2024 08:51, Liu Ying wrote:
> On 07/07/2024, Krzysztof Kozlowski wrote:
>> On 05/07/2024 11:09, Liu Ying wrote:
>>> i.MX8qxp Display Controller has a built-in interrupt controller to support
>>> Enable/Status/Preset/Clear interrupt bit.
>>>
>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>> ---
>>> .../fsl,imx8qxp-dc-intc.yaml | 321 ++++++++++++++++++
>>> 1 file changed, 321 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>>> new file mode 100644
>>> index 000000000000..3d0d11def505
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>>> @@ -0,0 +1,321 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Freescale i.MX8qxp Display Controller interrupt controller
>>> +
>>> +description: |
>>> + The Display Controller has a built-in interrupt controller with the following
>>> + features for all relevant HW events:
>>> +
>>> + * Enable bit (mask)
>>> + * Status bit (set by an HW event)
>>> + * Preset bit (can be used by SW to set status)
>>> + * Clear bit (used by SW to reset the status)
>>
>> 1. Why this is split from the main node?
>
> Maxime suggested to do so:
>
> "
> But at least the CRTC and the interrupt controller should be split away,
> or explained and detailed far better than "well it's just convenient".
> "
>
> https://lore.kernel.org/lkml/2k3cc3yfwqlpquxrdmzmaafz55b3lnqomzxjsvtetfriliqj3k@tv6uh7dzc2ea/
>
>>
>> 2. Who can use this interrupt controller? Children of your display unit?
>
> Yes, only devices in the main display controller use it.
>
>> Then it is not really a separate device, is it?
>
> Er, per Maxime, it is a separate device.
It's not for me, especially considering small register region used here.
Srsly, with that claim, some I2C device like PMIC also has a separate
interrupt controller, because interrupts are in separate few registers
(e.g. status, mask and ack).
Can any of the children interrupts be routed differently?
Post entire, complete DTS for review.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2024-07-08 14:09 ` Krzysztof Kozlowski
@ 2024-07-09 7:05 ` Liu Ying
0 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-09 7:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/08/2024, Krzysztof Kozlowski wrote:
> On 08/07/2024 08:51, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
>>>> i.MX8qxp Display Controller has a built-in interrupt controller to support
>>>> Enable/Status/Preset/Clear interrupt bit.
>>>>
>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>> ---
>>>> .../fsl,imx8qxp-dc-intc.yaml | 321 ++++++++++++++++++
>>>> 1 file changed, 321 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>>>> new file mode 100644
>>>> index 000000000000..3d0d11def505
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
>>>> @@ -0,0 +1,321 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Freescale i.MX8qxp Display Controller interrupt controller
>>>> +
>>>> +description: |
>>>> + The Display Controller has a built-in interrupt controller with the following
>>>> + features for all relevant HW events:
>>>> +
>>>> + * Enable bit (mask)
>>>> + * Status bit (set by an HW event)
>>>> + * Preset bit (can be used by SW to set status)
>>>> + * Clear bit (used by SW to reset the status)
>>>
>>> 1. Why this is split from the main node?
>>
>> Maxime suggested to do so:
>>
>> "
>> But at least the CRTC and the interrupt controller should be split away,
>> or explained and detailed far better than "well it's just convenient".
>> "
>>
>> https://lore.kernel.org/lkml/2k3cc3yfwqlpquxrdmzmaafz55b3lnqomzxjsvtetfriliqj3k@tv6uh7dzc2ea/
>>
>>>
>>> 2. Who can use this interrupt controller? Children of your display unit?
>>
>> Yes, only devices in the main display controller use it.
>>
>>> Then it is not really a separate device, is it?
>>
>> Er, per Maxime, it is a separate device.
>
> It's not for me, especially considering small register region used here.
Maxime, can you please chime in to discuss whether the interrupt controller
is a separate device?
Maybe register region size doesn't matter.
>
> Srsly, with that claim, some I2C device like PMIC also has a separate
> interrupt controller, because interrupts are in separate few registers
> (e.g. status, mask and ack).
>
> Can any of the children interrupts be routed differently?
No, I don't think they can.
>
> Post entire, complete DTS for review.
Will do that in v2.
>
> Best regards,
> Krzysztof
>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 05/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (3 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-07 14:03 ` Krzysztof Kozlowski
2024-07-05 9:09 ` [PATCH 06/10] drm/imx: Add i.MX8qxp Display Controller display engine Liu Ying
` (5 subsequent siblings)
10 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
.../bindings/display/imx/fsl,imx8qxp-dc.yaml | 243 ++++++++++++++++++
1 file changed, 243 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
new file mode 100644
index 000000000000..a2ad280d2839
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
@@ -0,0 +1,243 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller
+
+description: |
+ The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
+ components that include a blit engine for 2D graphics accelerations, display
+ controller for display output processing, as well as a command sequencer.
+
+ Display buffers Source buffers
+ (AXI read master) (AXI read master)
+ | .......... | | | |
+ +---------------------------+------------+------------------+-+-+------+
+ | Display Controller (DC) | .......... | | | | |
+ | | | | | | |
+ | @@@@@@@@@@@ +----------+------------+------------+ | | | |
+ A | | Command | | V V | | | | |
+ X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
+ I | | (AXI CLK) | | | | | @@@@@@@@@@ |
+ | @@@@@@@@@@@ | | Pixel Engine | | | | |
+ | | | | (AXI CLK) | | | | |
+ | V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | |
+ A | *********** | | | | | | | Blit | |
+ H <-+->| Configure | | V V V V | | Engine | |
+ B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| |
+ | *********** | | Display | | Display | | | | |
+ | | | Engine | | Engine | | | | |
+ | | | (Disp CLK)| | (Disp CLK)| | | | |
+ | @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ |
+ I | | Common | | | | | | |
+ R <-+--| Control | | | Display | | | |
+ Q | | (AXI CLK) | | | Controller | | | |
+ | @@@@@@@@@@@ +------------------------------------+ | |
+ | | | ^ | |
+ +--------------------------+----------------+-------+---------+--------+
+ ^ | | | |
+ | V V | V
+ Clocks & Resets Display Display Panic Destination
+ Output0 Output1 Control buffer
+ (AXI write master)
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-dc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: axi
+ - const: cfg
+
+ power-domains:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^axi-performance-counter@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-axi-performance-counter
+
+ "^command-sequencer@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-command-sequencer
+
+ "^display-engine@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-display-engine
+
+ "^interrupt-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-intc
+
+ "^pixel-engine@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: fsl,imx8qxp-dc-pixel-engine
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+
+ display-controller@56180000 {
+ compatible = "fsl,imx8qxp-dc";
+ reg = <0x56180000 0x40000>;
+ clocks = <&dc0_lpcg IMX_LPCG_CLK_4>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-controller@56180040 {
+ compatible = "fsl,imx8qxp-dc-intc";
+ reg = <0x56180040 0x60>;
+ clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+ interrupt-controller;
+ interrupt-parent = <&dc0_irqsteer>;
+ #interrupt-cells = <1>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <5>,
+ <0>, <1>, <2>, <3>,
+ <4>, <82>, <83>, <84>,
+ <85>, <209>, <210>, <211>,
+ <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "reserved",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ };
+
+ pixel-engine@56180800 {
+ compatible = "fsl,imx8qxp-dc-pixel-engine";
+ reg = <0x56180800 0xac00>;
+ clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
+ display-engine@5618b400 {
+ compatible = "fsl,imx8qxp-dc-display-engine";
+ reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
+ reg-names = "top", "cfg";
+ interrupt-parent = <&dc0_intc>;
+ interrupts = <15>, <16>, <17>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ fsl,dc-de-id = <0>;
+
+ port {
+ dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
+ remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH 05/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller
2024-07-05 9:09 ` [PATCH 05/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller Liu Ying
@ 2024-07-07 14:03 ` Krzysztof Kozlowski
2024-07-08 7:01 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-07 14:03 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 05/07/2024 11:09, Liu Ying wrote:
> i.MX8qxp Display Controller(DC) is comprised of three main components that
> include a blit engine for 2D graphics accelerations, display controller for
> display output processing, as well as a command sequencer.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> .../bindings/display/imx/fsl,imx8qxp-dc.yaml | 243 ++++++++++++++++++
> 1 file changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
> new file mode 100644
> index 000000000000..a2ad280d2839
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
> @@ -0,0 +1,243 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qxp Display Controller
> +
> +description: |
> + The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
> + components that include a blit engine for 2D graphics accelerations, display
> + controller for display output processing, as well as a command sequencer.
> +
> + Display buffers Source buffers
> + (AXI read master) (AXI read master)
> + | .......... | | | |
> + +---------------------------+------------+------------------+-+-+------+
> + | Display Controller (DC) | .......... | | | | |
> + | | | | | | |
> + | @@@@@@@@@@@ +----------+------------+------------+ | | | |
> + A | | Command | | V V | | | | |
> + X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
> + I | | (AXI CLK) | | | | | @@@@@@@@@@ |
> + | @@@@@@@@@@@ | | Pixel Engine | | | | |
> + | | | | (AXI CLK) | | | | |
> + | V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | |
> + A | *********** | | | | | | | Blit | |
> + H <-+->| Configure | | V V V V | | Engine | |
> + B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| |
> + | *********** | | Display | | Display | | | | |
> + | | | Engine | | Engine | | | | |
> + | | | (Disp CLK)| | (Disp CLK)| | | | |
> + | @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ |
> + I | | Common | | | | | | |
> + R <-+--| Control | | | Display | | | |
> + Q | | (AXI CLK) | | | Controller | | | |
> + | @@@@@@@@@@@ +------------------------------------+ | |
> + | | | ^ | |
> + +--------------------------+----------------+-------+---------+--------+
> + ^ | | | |
> + | V V | V
> + Clocks & Resets Display Display Panic Destination
> + Output0 Output1 Control buffer
> + (AXI write master)
> +
> +maintainers:
> + - Liu Ying <victor.liu@nxp.com>
> +
> +properties:
> + compatible:
> + const: fsl,imx8qxp-dc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: axi
> + - const: cfg
> +
> + power-domains:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +patternProperties:
> + "^axi-performance-counter@[0-9a-f]+$":
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Is this a PMU?
> + type: object
> + additionalProperties: true
> +
> + properties:
> + compatible:
> + const: fsl,imx8qxp-dc-axi-performance-counter
> +
> + pixel-engine@56180800 {
> + compatible = "fsl,imx8qxp-dc-pixel-engine";
> + reg = <0x56180800 0xac00>;
> + clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + };
> +
> + display-engine@5618b400 {
> + compatible = "fsl,imx8qxp-dc-display-engine";
> + reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
> + reg-names = "top", "cfg";
> + interrupt-parent = <&dc0_intc>;
Where is this node?
I think this proves that interrupt controller is part of the display
controller.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH 05/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller
2024-07-07 14:03 ` Krzysztof Kozlowski
@ 2024-07-08 7:01 ` Liu Ying
0 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-08 7:01 UTC (permalink / raw)
To: Krzysztof Kozlowski, dri-devel, devicetree, imx, linux-arm-kernel,
linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller(DC) is comprised of three main components that
>> include a blit engine for 2D graphics accelerations, display controller for
>> display output processing, as well as a command sequencer.
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>> .../bindings/display/imx/fsl,imx8qxp-dc.yaml | 243 ++++++++++++++++++
>> 1 file changed, 243 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
>> new file mode 100644
>> index 000000000000..a2ad280d2839
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
>> @@ -0,0 +1,243 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Freescale i.MX8qxp Display Controller
>> +
>> +description: |
>> + The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
>> + components that include a blit engine for 2D graphics accelerations, display
>> + controller for display output processing, as well as a command sequencer.
>> +
>> + Display buffers Source buffers
>> + (AXI read master) (AXI read master)
>> + | .......... | | | |
>> + +---------------------------+------------+------------------+-+-+------+
>> + | Display Controller (DC) | .......... | | | | |
>> + | | | | | | |
>> + | @@@@@@@@@@@ +----------+------------+------------+ | | | |
>> + A | | Command | | V V | | | | |
>> + X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
>> + I | | (AXI CLK) | | | | | @@@@@@@@@@ |
>> + | @@@@@@@@@@@ | | Pixel Engine | | | | |
>> + | | | | (AXI CLK) | | | | |
>> + | V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | |
>> + A | *********** | | | | | | | Blit | |
>> + H <-+->| Configure | | V V V V | | Engine | |
>> + B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| |
>> + | *********** | | Display | | Display | | | | |
>> + | | | Engine | | Engine | | | | |
>> + | | | (Disp CLK)| | (Disp CLK)| | | | |
>> + | @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ |
>> + I | | Common | | | | | | |
>> + R <-+--| Control | | | Display | | | |
>> + Q | | (AXI CLK) | | | Controller | | | |
>> + | @@@@@@@@@@@ +------------------------------------+ | |
>> + | | | ^ | |
>> + +--------------------------+----------------+-------+---------+--------+
>> + ^ | | | |
>> + | V V | V
>> + Clocks & Resets Display Display Panic Destination
>> + Output0 Output1 Control buffer
>> + (AXI write master)
>> +
>> +maintainers:
>> + - Liu Ying <victor.liu@nxp.com>
>> +
>> +properties:
>> + compatible:
>> + const: fsl,imx8qxp-dc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + resets:
>> + maxItems: 2
>> +
>> + reset-names:
>> + items:
>> + - const: axi
>> + - const: cfg
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 1
>> +
>> + ranges: true
>> +
>> +patternProperties:
>> + "^axi-performance-counter@[0-9a-f]+$":
>
> Node names should be generic. See also an explanation and list of
Ok.
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
>
> Is this a PMU?
Will use "^pmu@[0-9a-f]+$". Thanks.
>
>> + type: object
>> + additionalProperties: true
>> +
>> + properties:
>> + compatible:
>> + const: fsl,imx8qxp-dc-axi-performance-counter
>> +
>
>
>> + pixel-engine@56180800 {
>> + compatible = "fsl,imx8qxp-dc-pixel-engine";
>> + reg = <0x56180800 0xac00>;
>> + clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + };
>> +
>> + display-engine@5618b400 {
>> + compatible = "fsl,imx8qxp-dc-display-engine";
>> + reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
>> + reg-names = "top", "cfg";
>> + interrupt-parent = <&dc0_intc>;
>
> Where is this node?
It's the interrupt controller documented in patch 4/10 in this series.
It's a child node in the main display controller node.
>
> I think this proves that interrupt controller is part of the display
> controller.
Yes. But, per Maxime, the interrupt controller is a separate device.
>
> Best regards,
> Krzysztof
>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 06/10] drm/imx: Add i.MX8qxp Display Controller display engine
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (4 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 05/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-05 9:09 ` [PATCH 07/10] drm/imx: Add i.MX8qxp Display Controller pixel engine Liu Ying
` (4 subsequent siblings)
10 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller display engine consists of all processing
units that operate in a display clock domain. Add minimal feature
support with FrameGen and TCon so that the engine can output display
timings. The display engine driver as a master binds FrameGen and
TCon drivers as components. While at it, the display engine driver
is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dc/Kconfig | 5 +
drivers/gpu/drm/imx/dc/Makefile | 5 +
drivers/gpu/drm/imx/dc/dc-de.c | 152 +++++++++++++
drivers/gpu/drm/imx/dc/dc-de.h | 61 ++++++
drivers/gpu/drm/imx/dc/dc-drv.c | 32 +++
drivers/gpu/drm/imx/dc/dc-drv.h | 24 +++
drivers/gpu/drm/imx/dc/dc-fg.c | 367 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/imx/dc/dc-tc.c | 137 ++++++++++++
10 files changed, 785 insertions(+)
create mode 100644 drivers/gpu/drm/imx/dc/Kconfig
create mode 100644 drivers/gpu/drm/imx/dc/Makefile
create mode 100644 drivers/gpu/drm/imx/dc/dc-de.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-de.h
create mode 100644 drivers/gpu/drm/imx/dc/dc-drv.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-drv.h
create mode 100644 drivers/gpu/drm/imx/dc/dc-fg.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-tc.c
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 03535a15dd8f..3e8c6edbc17c 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
+source "drivers/gpu/drm/imx/dc/Kconfig"
source "drivers/gpu/drm/imx/dcss/Kconfig"
source "drivers/gpu/drm/imx/ipuv3/Kconfig"
source "drivers/gpu/drm/imx/lcdc/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 86f38e7c7422..c7b317640d71 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_DRM_IMX8_DC) += dc/
obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
obj-$(CONFIG_DRM_IMX) += ipuv3/
obj-$(CONFIG_DRM_IMX_LCDC) += lcdc/
diff --git a/drivers/gpu/drm/imx/dc/Kconfig b/drivers/gpu/drm/imx/dc/Kconfig
new file mode 100644
index 000000000000..32d7471c49d0
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/Kconfig
@@ -0,0 +1,5 @@
+config DRM_IMX8_DC
+ tristate "Freescale i.MX8 Display Controller Graphics"
+ depends on DRM && COMMON_CLK && OF && (ARCH_MXC || COMPILE_TEST)
+ help
+ enable Freescale i.MX8 Display Controller(DC) graphics support
diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makefile
new file mode 100644
index 000000000000..56de82d53d4d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+imx8-dc-drm-objs := dc-de.o dc-drv.o dc-fg.o dc-tc.o
+
+obj-$(CONFIG_DRM_IMX8_DC) += imx8-dc-drm.o
diff --git a/drivers/gpu/drm/imx/dc/dc-de.c b/drivers/gpu/drm/imx/dc/dc-de.c
new file mode 100644
index 000000000000..047277c55bc1
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-de.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/component.h>
+#include <linux/container_of.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_managed.h>
+
+#include "dc-de.h"
+#include "dc-drv.h"
+
+#define POLARITYCTRL 0xc
+#define POLEN_HIGH BIT(2)
+
+struct dc_de_priv {
+ struct dc_de engine;
+ void __iomem *reg_top;
+};
+
+static inline struct dc_de_priv *to_de_priv(struct dc_de *de)
+{
+ return container_of(de, struct dc_de_priv, engine);
+}
+
+static inline void
+dc_dec_write(struct dc_de *de, unsigned int offset, u32 value)
+{
+ struct dc_de_priv *priv = to_de_priv(de);
+
+ writel(value, priv->reg_top + offset);
+}
+
+static void dc_dec_init(struct dc_de *de)
+{
+ dc_dec_write(de, POLARITYCTRL, POLEN_HIGH);
+}
+
+static int dc_de_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_de_priv *priv;
+ int ret;
+
+ priv = drmm_kzalloc(&dc_drm->base, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg_top = devm_platform_ioremap_resource_byname(pdev, "top");
+ if (IS_ERR(priv->reg_top))
+ return PTR_ERR(priv->reg_top);
+
+ priv->engine.irq_shdld = platform_get_irq_byname(pdev, "shdload");
+ if (priv->engine.irq_shdld < 0)
+ return priv->engine.irq_shdld;
+
+ priv->engine.irq_framecomplete =
+ platform_get_irq_byname(pdev, "framecomplete");
+ if (priv->engine.irq_framecomplete < 0)
+ return priv->engine.irq_framecomplete;
+
+ priv->engine.irq_seqcomplete =
+ platform_get_irq_byname(pdev, "seqcomplete");
+ if (priv->engine.irq_seqcomplete < 0)
+ return priv->engine.irq_seqcomplete;
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-de-id",
+ &priv->engine.id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ priv->engine.dev = dev;
+
+ dev_set_drvdata(dev, priv);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ dc_drm->de[priv->engine.id] = &priv->engine;
+
+ return 0;
+}
+
+static const struct component_ops dc_de_ops = {
+ .bind = dc_de_bind,
+};
+
+static int dc_de_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = devm_of_platform_populate(&pdev->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = component_add(&pdev->dev, &dc_de_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_de_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_de_ops);
+}
+
+static int dc_de_runtime_resume(struct device *dev)
+{
+ struct dc_de_priv *priv = dev_get_drvdata(dev);
+ struct dc_de *engine = &priv->engine;
+
+ dc_dec_init(engine);
+ dc_fg_init(engine->fg);
+ dc_tc_init(engine->tc);
+
+ return 0;
+}
+
+static const struct dev_pm_ops dc_de_pm_ops = {
+ RUNTIME_PM_OPS(NULL, dc_de_runtime_resume, NULL)
+};
+
+static const struct of_device_id dc_de_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-display-engine", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_de_dt_ids);
+
+struct platform_driver dc_de_driver = {
+ .probe = dc_de_probe,
+ .remove_new = dc_de_remove,
+ .driver = {
+ .name = "imx8-dc-display-engine",
+ .of_match_table = dc_de_dt_ids,
+ .pm = pm_sleep_ptr(&dc_de_pm_ops),
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-de.h b/drivers/gpu/drm/imx/dc/dc-de.h
new file mode 100644
index 000000000000..5fe340c88f91
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-de.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DC_DISPLAY_ENGINE_H__
+#define __DC_DISPLAY_ENGINE_H__
+
+#include <linux/device.h>
+#include <drm/drm_modes.h>
+
+#define DC_DISPLAYS 2
+
+enum dc_fg_syncmode {
+ FG_SYNCMODE_OFF, /* No side-by-side synchronization. */
+};
+
+enum dc_fg_dm {
+ FG_DM_CONSTCOL = 0x1, /* Constant Color Background is shown. */
+ FG_DM_SEC_ON_TOP = 0x5, /* Both inputs overlaid with secondary on top. */
+};
+
+struct dc_fg {
+};
+
+struct dc_tc {
+};
+
+struct dc_de {
+ struct device *dev;
+ struct dc_fg *fg;
+ struct dc_tc *tc;
+ int irq_shdld;
+ int irq_framecomplete;
+ int irq_seqcomplete;
+ u32 id;
+};
+
+/* Frame Generator Unit */
+void dc_fg_syncmode(struct dc_fg *fg, enum dc_fg_syncmode mode);
+void dc_fg_cfg_videomode(struct dc_fg *fg, struct drm_display_mode *m);
+void dc_fg_displaymode(struct dc_fg *fg, enum dc_fg_dm mode);
+void dc_fg_panic_displaymode(struct dc_fg *fg, enum dc_fg_dm mode);
+void dc_fg_enable(struct dc_fg *fg);
+void dc_fg_disable(struct dc_fg *fg);
+void dc_fg_shdtokgen(struct dc_fg *fg);
+u32 dc_fg_get_frame_index(struct dc_fg *fg);
+int dc_fg_get_line_index(struct dc_fg *fg);
+bool dc_fg_wait_for_frame_index_moving(struct dc_fg *fg);
+bool dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg *fg);
+void dc_fg_secondary_clear_channel_status(struct dc_fg *fg);
+int dc_fg_wait_for_secondary_syncup(struct dc_fg *fg);
+void dc_fg_enable_clock(struct dc_fg *fg);
+void dc_fg_disable_clock(struct dc_fg *fg);
+enum drm_mode_status dc_fg_check_clock(struct dc_fg *fg, int clk_khz);
+void dc_fg_init(struct dc_fg *fg);
+
+/* Timing Controller Unit */
+void dc_tc_init(struct dc_tc *tc);
+
+#endif /* __DC_DISPLAY_ENGINE_H__ */
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.c b/drivers/gpu/drm/imx/dc/dc-drv.c
new file mode 100644
index 000000000000..e5910a82dd4d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-drv.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "dc-drv.h"
+
+static struct platform_driver * const dc_drivers[] = {
+ &dc_de_driver,
+ &dc_fg_driver,
+ &dc_tc_driver,
+};
+
+static int __init dc_drm_init(void)
+{
+ return platform_register_drivers(dc_drivers, ARRAY_SIZE(dc_drivers));
+}
+
+static void __exit dc_drm_exit(void)
+{
+ platform_unregister_drivers(dc_drivers, ARRAY_SIZE(dc_drivers));
+}
+
+module_init(dc_drm_init);
+module_exit(dc_drm_exit);
+
+MODULE_DESCRIPTION("i.MX8 Display Controller DRM Driver");
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.h b/drivers/gpu/drm/imx/dc/dc-drv.h
new file mode 100644
index 000000000000..e1290d9a0a99
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-drv.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DC_DRV_H__
+#define __DC_DRV_H__
+
+#include <linux/platform_device.h>
+
+#include <drm/drm_device.h>
+
+#include "dc-de.h"
+
+struct dc_drm_device {
+ struct drm_device base;
+ struct dc_de *de[DC_DISPLAYS];
+};
+
+extern struct platform_driver dc_de_driver;
+extern struct platform_driver dc_fg_driver;
+extern struct platform_driver dc_tc_driver;
+
+#endif /* __DC_DRV_H__ */
diff --git a/drivers/gpu/drm/imx/dc/dc-fg.c b/drivers/gpu/drm/imx/dc/dc-fg.c
new file mode 100644
index 000000000000..78491d17dfbd
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-fg.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/container_of.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/jiffies.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_managed.h>
+#include <drm/drm_modes.h>
+
+#include "dc-de.h"
+#include "dc-drv.h"
+
+#define FGSTCTRL 0x8
+#define FGSYNCMODE_MASK 0x6
+#define FGSYNCMODE(n) ((n) << 6)
+#define SHDEN BIT(0)
+
+#define HTCFG1 0xc
+#define HTOTAL(n) ((((n) - 1) & 0x3fff) << 16)
+#define HACT(n) ((n) & 0x3fff)
+
+#define HTCFG2 0x10
+#define HSEN BIT(31)
+#define HSBP(n) ((((n) - 1) & 0x3fff) << 16)
+#define HSYNC(n) (((n) - 1) & 0x3fff)
+
+#define VTCFG1 0x14
+#define VTOTAL(n) ((((n) - 1) & 0x3fff) << 16)
+#define VACT(n) ((n) & 0x3fff)
+
+#define VTCFG2 0x18
+#define VSEN BIT(31)
+#define VSBP(n) ((((n) - 1) & 0x3fff) << 16)
+#define VSYNC(n) (((n) - 1) & 0x3fff)
+
+#define PKICKCONFIG 0x2c
+#define SKICKCONFIG 0x30
+#define EN BIT(31)
+#define ROW(n) (((n) & 0x3fff) << 16)
+#define COL(n) ((n) & 0x3fff)
+
+#define PACFG 0x54
+#define SACFG 0x58
+#define STARTX(n) (((n) + 1) & 0x3fff)
+#define STARTY(n) (((((n) + 1) & 0x3fff)) << 16)
+
+#define FGINCTRL 0x5c
+#define FGINCTRLPANIC 0x60
+#define FGDM_MASK 0x7
+#define ENPRIMALPHA BIT(3)
+#define ENSECALPHA BIT(4)
+
+#define FGCCR 0x64
+#define CCGREEN(g) (((g) & 0x3ff) << 10)
+
+#define FGENABLE 0x68
+#define FGEN BIT(0)
+
+#define FGSLR 0x6c
+#define SHDTOKGEN BIT(0)
+
+#define FGTIMESTAMP 0x74
+#define FRAMEINDEX_SHIFT 14
+#define FRAMEINDEX_MASK (0x3ffff << FRAMEINDEX_SHIFT)
+#define LINEINDEX_MASK 0x3fff
+
+#define FGCHSTAT 0x78
+#define SECSYNCSTAT BIT(24)
+#define SFIFOEMPTY BIT(16)
+
+#define FGCHSTATCLR 0x7c
+#define CLRSECSTAT BIT(16)
+
+#define KHZ 1000
+
+struct dc_fg_priv {
+ struct dc_fg fg;
+ struct device *dev;
+ void __iomem *reg;
+ struct clk *clk_disp;
+};
+
+static inline struct dc_fg_priv *to_fg_priv(struct dc_fg *fg)
+{
+ return container_of(fg, struct dc_fg_priv, fg);
+}
+
+static inline u32 dc_fg_read(struct dc_fg *fg, unsigned int offset)
+{
+ struct dc_fg_priv *priv = to_fg_priv(fg);
+
+ return readl(priv->reg + offset);
+}
+
+static inline void
+dc_fg_write(struct dc_fg *fg, unsigned int offset, u32 value)
+{
+ struct dc_fg_priv *priv = to_fg_priv(fg);
+
+ writel(value, priv->reg + offset);
+}
+
+static inline void
+dc_fg_write_mask(struct dc_fg *fg, unsigned int offset, u32 mask, u32 value)
+{
+ u32 tmp;
+
+ tmp = dc_fg_read(fg, offset);
+ tmp &= ~mask;
+ dc_fg_write(fg, offset, tmp | value);
+}
+
+static void dc_fg_enable_shden(struct dc_fg *fg)
+{
+ dc_fg_write_mask(fg, FGSTCTRL, SHDEN, SHDEN);
+}
+
+void dc_fg_syncmode(struct dc_fg *fg, enum dc_fg_syncmode mode)
+{
+ dc_fg_write_mask(fg, FGSTCTRL, FGSYNCMODE_MASK, FGSYNCMODE(mode));
+}
+
+void dc_fg_cfg_videomode(struct dc_fg *fg, struct drm_display_mode *m)
+{
+ struct dc_fg_priv *priv = to_fg_priv(fg);
+ u32 hact, htotal, hsync, hsbp;
+ u32 vact, vtotal, vsync, vsbp;
+ u32 kick_row, kick_col;
+ int ret;
+
+ hact = m->crtc_hdisplay;
+ htotal = m->crtc_htotal;
+ hsync = m->crtc_hsync_end - m->crtc_hsync_start;
+ hsbp = m->crtc_htotal - m->crtc_hsync_start;
+
+ vact = m->crtc_vdisplay;
+ vtotal = m->crtc_vtotal;
+ vsync = m->crtc_vsync_end - m->crtc_vsync_start;
+ vsbp = m->crtc_vtotal - m->crtc_vsync_start;
+
+ /* video mode */
+ dc_fg_write(fg, HTCFG1, HACT(hact) | HTOTAL(htotal));
+ dc_fg_write(fg, HTCFG2, HSYNC(hsync) | HSBP(hsbp) | HSEN);
+ dc_fg_write(fg, VTCFG1, VACT(vact) | VTOTAL(vtotal));
+ dc_fg_write(fg, VTCFG2, VSYNC(vsync) | VSBP(vsbp) | VSEN);
+
+ kick_col = hact + 1;
+ kick_row = vact;
+
+ /* pkickconfig */
+ dc_fg_write(fg, PKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);
+
+ /* skikconfig */
+ dc_fg_write(fg, SKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);
+
+ /* primary and secondary area position configuration */
+ dc_fg_write(fg, PACFG, STARTX(0) | STARTY(0));
+ dc_fg_write(fg, SACFG, STARTX(0) | STARTY(0));
+
+ /* alpha */
+ dc_fg_write_mask(fg, FGINCTRL, ENPRIMALPHA | ENSECALPHA, 0);
+ dc_fg_write_mask(fg, FGINCTRLPANIC, ENPRIMALPHA | ENSECALPHA, 0);
+
+ /* constant color is green(used in panic mode) */
+ dc_fg_write(fg, FGCCR, CCGREEN(0x3ff));
+
+ ret = clk_set_rate(priv->clk_disp, m->clock * KHZ);
+ if (ret < 0)
+ dev_err(priv->dev,
+ "failed to set display clock rate: %d\n", ret);
+}
+
+void dc_fg_displaymode(struct dc_fg *fg, enum dc_fg_dm mode)
+{
+ dc_fg_write_mask(fg, FGINCTRL, FGDM_MASK, mode);
+}
+
+void dc_fg_panic_displaymode(struct dc_fg *fg, enum dc_fg_dm mode)
+{
+ dc_fg_write_mask(fg, FGINCTRLPANIC, FGDM_MASK, mode);
+}
+
+void dc_fg_enable(struct dc_fg *fg)
+{
+ dc_fg_write(fg, FGENABLE, FGEN);
+}
+
+void dc_fg_disable(struct dc_fg *fg)
+{
+ dc_fg_write(fg, FGENABLE, 0);
+}
+
+void dc_fg_shdtokgen(struct dc_fg *fg)
+{
+ dc_fg_write(fg, FGSLR, SHDTOKGEN);
+}
+
+u32 dc_fg_get_frame_index(struct dc_fg *fg)
+{
+ u32 val = dc_fg_read(fg, FGTIMESTAMP);
+
+ return (val & FRAMEINDEX_MASK) >> FRAMEINDEX_SHIFT;
+}
+
+int dc_fg_get_line_index(struct dc_fg *fg)
+{
+ u32 val = dc_fg_read(fg, FGTIMESTAMP);
+
+ return val & LINEINDEX_MASK;
+}
+
+bool dc_fg_wait_for_frame_index_moving(struct dc_fg *fg)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
+ u32 frame_index, last_frame_index;
+
+ frame_index = dc_fg_get_frame_index(fg);
+ do {
+ last_frame_index = frame_index;
+ frame_index = dc_fg_get_frame_index(fg);
+ } while (last_frame_index == frame_index &&
+ time_before(jiffies, timeout));
+
+ return last_frame_index != frame_index;
+}
+
+bool dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg *fg)
+{
+ u32 val;
+
+ val = dc_fg_read(fg, FGCHSTAT);
+
+ return !!(val & SFIFOEMPTY);
+}
+
+void dc_fg_secondary_clear_channel_status(struct dc_fg *fg)
+{
+ dc_fg_write(fg, FGCHSTATCLR, CLRSECSTAT);
+}
+
+int dc_fg_wait_for_secondary_syncup(struct dc_fg *fg)
+{
+ struct dc_fg_priv *priv = to_fg_priv(fg);
+ u32 val;
+
+ return readl_poll_timeout(priv->reg + FGCHSTAT, val,
+ val & SECSYNCSTAT, 5, 100000);
+}
+
+void dc_fg_enable_clock(struct dc_fg *fg)
+{
+ struct dc_fg_priv *priv = to_fg_priv(fg);
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk_disp);
+ if (ret)
+ dev_err(priv->dev, "failed to enable display clock: %d\n", ret);
+}
+
+void dc_fg_disable_clock(struct dc_fg *fg)
+{
+ struct dc_fg_priv *priv = to_fg_priv(fg);
+
+ clk_disable_unprepare(priv->clk_disp);
+}
+
+enum drm_mode_status dc_fg_check_clock(struct dc_fg *fg, int clk_khz)
+{
+ struct dc_fg_priv *priv = to_fg_priv(fg);
+ unsigned long rounded_rate;
+
+ rounded_rate = clk_round_rate(priv->clk_disp, clk_khz * KHZ);
+
+ if (rounded_rate != clk_khz * KHZ)
+ return MODE_NOCLOCK;
+
+ return MODE_OK;
+}
+
+void dc_fg_init(struct dc_fg *fg)
+{
+ dc_fg_enable_shden(fg);
+ dc_fg_syncmode(fg, FG_SYNCMODE_OFF);
+}
+
+static int dc_fg_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_fg_priv *priv;
+ struct dc_de *de;
+ int ret;
+ u32 id;
+
+ priv = drmm_kzalloc(&dc_drm->base, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->reg))
+ return PTR_ERR(priv->reg);
+
+ priv->clk_disp = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk_disp))
+ return dev_err_probe(dev, PTR_ERR(priv->clk_disp),
+ "failed to get display clock\n");
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-fg-id", &id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ priv->dev = dev;
+
+ de = dc_drm->de[id];
+ de->fg = &priv->fg;
+
+ return 0;
+}
+
+static const struct component_ops dc_fg_ops = {
+ .bind = dc_fg_bind,
+};
+
+static int dc_fg_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_fg_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_fg_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_fg_ops);
+}
+
+static const struct of_device_id dc_fg_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-framegen", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_fg_dt_ids);
+
+struct platform_driver dc_fg_driver = {
+ .probe = dc_fg_probe,
+ .remove_new = dc_fg_remove,
+ .driver = {
+ .name = "imx8-dc-framegen",
+ .of_match_table = dc_fg_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-tc.c b/drivers/gpu/drm/imx/dc/dc-tc.c
new file mode 100644
index 000000000000..9686f3ce95db
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-tc.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/component.h>
+#include <linux/container_of.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_managed.h>
+
+#include "dc-drv.h"
+#include "dc-de.h"
+
+#define TCON_CTRL 0x410
+#define CTRL_RST_VAL 0x01401408
+
+/* red: MAPBIT 29-20, green: MAPBIT 19-10, blue: MAPBIT 9-0 */
+#define MAPBIT3_0 0x418
+#define MAPBIT7_4 0x41c
+#define MAPBIT11_8 0x420
+#define MAPBIT15_12 0x424
+#define MAPBIT19_16 0x428
+#define MAPBIT23_20 0x42c
+#define MAPBIT27_24 0x430
+#define MAPBIT31_28 0x434
+#define MAPBIT34_32 0x438
+
+struct dc_tc_priv {
+ struct dc_tc tc;
+ void __iomem *reg;
+};
+
+static inline struct dc_tc_priv *to_tc_priv(struct dc_tc *tc)
+{
+ return container_of(tc, struct dc_tc_priv, tc);
+}
+
+static inline void dc_tc_write(struct dc_tc *tc, unsigned int offset, u32 value)
+{
+ struct dc_tc_priv *priv = to_tc_priv(tc);
+
+ writel(value, priv->reg + offset);
+}
+
+static void dc_tc_set_fmt(struct dc_tc *tc)
+{
+ /*
+ * The pixels reach TCON are always in 30-bit BGR format.
+ * The first bridge always receives pixels in 30-bit RGB format.
+ * So, map the format to MEDIA_BUS_FMT_RGB101010_1X30.
+ */
+ dc_tc_write(tc, MAPBIT3_0, 0x17161514);
+ dc_tc_write(tc, MAPBIT7_4, 0x1b1a1918);
+ dc_tc_write(tc, MAPBIT11_8, 0x0b0a1d1c);
+ dc_tc_write(tc, MAPBIT15_12, 0x0f0e0d0c);
+ dc_tc_write(tc, MAPBIT19_16, 0x13121110);
+ dc_tc_write(tc, MAPBIT23_20, 0x03020100);
+ dc_tc_write(tc, MAPBIT27_24, 0x07060504);
+ dc_tc_write(tc, MAPBIT31_28, 0x00000908);
+}
+
+void dc_tc_init(struct dc_tc *tc)
+{
+ /* reset TCON_CTRL to POR default so that TCON works in bypass mode */
+ dc_tc_write(tc, TCON_CTRL, CTRL_RST_VAL);
+ dc_tc_set_fmt(tc);
+}
+
+static int dc_tc_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_tc_priv *priv;
+ struct dc_de *de;
+ int ret;
+ u32 id;
+
+ priv = drmm_kzalloc(&dc_drm->base, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->reg))
+ return PTR_ERR(priv->reg);
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-tc-id", &id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ de = dc_drm->de[id];
+ de->tc = &priv->tc;
+
+ return 0;
+}
+
+static const struct component_ops dc_tc_ops = {
+ .bind = dc_tc_bind,
+};
+
+static int dc_tc_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_tc_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_tc_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_tc_ops);
+}
+
+static const struct of_device_id dc_tc_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-tcon", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_tc_dt_ids);
+
+struct platform_driver dc_tc_driver = {
+ .probe = dc_tc_probe,
+ .remove_new = dc_tc_remove,
+ .driver = {
+ .name = "imx8-dc-tcon",
+ .of_match_table = dc_tc_dt_ids,
+ },
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH 07/10] drm/imx: Add i.MX8qxp Display Controller pixel engine
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (5 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 06/10] drm/imx: Add i.MX8qxp Display Controller display engine Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-05 9:09 ` [PATCH 08/10] drm/imx: Add i.MX8qxp Display Controller interrupt controller Liu Ying
` (3 subsequent siblings)
10 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller pixel engine consists of all processing
units that operate in the AXI bus clock domain. Add drivers for
ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as
well as a pixel engine driver, so that two displays with primary
planes can be supported. The pixel engine driver as a master binds
those unit drivers as components. While at it, the pixel engine
driver is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/drm/imx/dc/Makefile | 3 +-
drivers/gpu/drm/imx/dc/dc-cf.c | 158 +++++++++++++++++
drivers/gpu/drm/imx/dc/dc-drv.c | 6 +
drivers/gpu/drm/imx/dc/dc-drv.h | 8 +
drivers/gpu/drm/imx/dc/dc-ed.c | 267 ++++++++++++++++++++++++++++
drivers/gpu/drm/imx/dc/dc-fl.c | 137 +++++++++++++++
drivers/gpu/drm/imx/dc/dc-fu.c | 241 +++++++++++++++++++++++++
drivers/gpu/drm/imx/dc/dc-fu.h | 129 ++++++++++++++
drivers/gpu/drm/imx/dc/dc-fw.c | 150 ++++++++++++++++
drivers/gpu/drm/imx/dc/dc-lb.c | 301 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/imx/dc/dc-pe.c | 140 +++++++++++++++
drivers/gpu/drm/imx/dc/dc-pe.h | 91 ++++++++++
12 files changed, 1630 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/imx/dc/dc-cf.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-ed.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-fl.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-fu.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-fu.h
create mode 100644 drivers/gpu/drm/imx/dc/dc-fw.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-lb.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-pe.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-pe.h
diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makefile
index 56de82d53d4d..2942ae6fd5bd 100644
--- a/drivers/gpu/drm/imx/dc/Makefile
+++ b/drivers/gpu/drm/imx/dc/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-imx8-dc-drm-objs := dc-de.o dc-drv.o dc-fg.o dc-tc.o
+imx8-dc-drm-objs := dc-cf.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o dc-fu.o \
+ dc-fw.o dc-lb.o dc-pe.o dc-tc.o
obj-$(CONFIG_DRM_IMX8_DC) += imx8-dc-drm.o
diff --git a/drivers/gpu/drm/imx/dc/dc-cf.c b/drivers/gpu/drm/imx/dc/dc-cf.c
new file mode 100644
index 000000000000..b438f8e46853
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-cf.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/component.h>
+#include <linux/container_of.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_managed.h>
+
+#include "dc-drv.h"
+#include "dc-pe.h"
+
+#define STATICCONTROL 0x8
+
+#define FRAMEDIMENSIONS 0xc
+#define WIDTH(w) (((w) - 1) & 0x3fff)
+#define HEIGHT(h) ((((h) - 1) & 0x3fff) << 16)
+
+#define CONSTANTCOLOR 0x10
+#define BLUE(b) (((b) & 0xff) << 8)
+
+struct dc_cf_priv {
+ struct dc_cf cf;
+ void __iomem *reg_cfg;
+ u32 id;
+ enum dc_link_id link;
+};
+
+static inline struct dc_cf_priv *to_cf_priv(struct dc_cf *cf)
+{
+ return container_of(cf, struct dc_cf_priv, cf);
+}
+
+static inline void dc_cf_write(struct dc_cf *cf, unsigned int offset, u32 value)
+{
+ struct dc_cf_priv *priv = to_cf_priv(cf);
+
+ writel(value, priv->reg_cfg + offset);
+}
+
+static void dc_cf_enable_shden(struct dc_cf *cf)
+{
+ dc_cf_write(cf, STATICCONTROL, SHDEN);
+}
+
+enum dc_link_id dc_cf_get_link_id(struct dc_cf *cf)
+{
+ struct dc_cf_priv *priv = to_cf_priv(cf);
+
+ return priv->link;
+}
+
+void dc_cf_framedimensions(struct dc_cf *cf, unsigned int w,
+ unsigned int h)
+{
+ dc_cf_write(cf, FRAMEDIMENSIONS, WIDTH(w) | HEIGHT(h));
+}
+
+void dc_cf_constantcolor_black(struct dc_cf *cf)
+{
+ dc_cf_write(cf, CONSTANTCOLOR, 0);
+}
+
+void dc_cf_constantcolor_blue(struct dc_cf *cf)
+{
+ dc_cf_write(cf, CONSTANTCOLOR, BLUE(0xff));
+}
+
+void dc_cf_init(struct dc_cf *cf)
+{
+ dc_cf_enable_shden(cf);
+}
+
+static int dc_cf_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_pe *pe = dc_drm->pe;
+ struct dc_cf_priv *priv;
+ int ret;
+
+ priv = drmm_kzalloc(&dc_drm->base, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg_cfg = devm_platform_ioremap_resource_byname(pdev, "cfg");
+ if (IS_ERR(priv->reg_cfg))
+ return PTR_ERR(priv->reg_cfg);
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-cf-id", &priv->id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ switch (priv->id) {
+ case 0:
+ pe->cf_cont[0] = &priv->cf;
+ priv->link = LINK_ID_CONSTFRAME0;
+ break;
+ case 1:
+ pe->cf_cont[1] = &priv->cf;
+ priv->link = LINK_ID_CONSTFRAME1;
+ break;
+ case 4:
+ pe->cf_safe[0] = &priv->cf;
+ priv->link = LINK_ID_CONSTFRAME4;
+ break;
+ case 5:
+ pe->cf_safe[1] = &priv->cf;
+ priv->link = LINK_ID_CONSTFRAME5;
+ break;
+ }
+
+ return 0;
+}
+
+static const struct component_ops dc_cf_ops = {
+ .bind = dc_cf_bind,
+};
+
+static int dc_cf_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_cf_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_cf_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_cf_ops);
+}
+
+static const struct of_device_id dc_cf_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-constframe", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_cf_dt_ids);
+
+struct platform_driver dc_cf_driver = {
+ .probe = dc_cf_probe,
+ .remove_new = dc_cf_remove,
+ .driver = {
+ .name = "imx8-dc-constframe",
+ .of_match_table = dc_cf_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.c b/drivers/gpu/drm/imx/dc/dc-drv.c
index e5910a82dd4d..7c64acc863ad 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.c
+++ b/drivers/gpu/drm/imx/dc/dc-drv.c
@@ -9,8 +9,14 @@
#include "dc-drv.h"
static struct platform_driver * const dc_drivers[] = {
+ &dc_cf_driver,
&dc_de_driver,
+ &dc_ed_driver,
&dc_fg_driver,
+ &dc_fl_driver,
+ &dc_fw_driver,
+ &dc_lb_driver,
+ &dc_pe_driver,
&dc_tc_driver,
};
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.h b/drivers/gpu/drm/imx/dc/dc-drv.h
index e1290d9a0a99..c687a36b8153 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.h
+++ b/drivers/gpu/drm/imx/dc/dc-drv.h
@@ -11,14 +11,22 @@
#include <drm/drm_device.h>
#include "dc-de.h"
+#include "dc-pe.h"
struct dc_drm_device {
struct drm_device base;
struct dc_de *de[DC_DISPLAYS];
+ struct dc_pe *pe;
};
+extern struct platform_driver dc_cf_driver;
+extern struct platform_driver dc_ed_driver;
extern struct platform_driver dc_de_driver;
extern struct platform_driver dc_fg_driver;
+extern struct platform_driver dc_fl_driver;
+extern struct platform_driver dc_fw_driver;
+extern struct platform_driver dc_lb_driver;
+extern struct platform_driver dc_pe_driver;
extern struct platform_driver dc_tc_driver;
#endif /* __DC_DRV_H__ */
diff --git a/drivers/gpu/drm/imx/dc/dc-ed.c b/drivers/gpu/drm/imx/dc/dc-ed.c
new file mode 100644
index 000000000000..ad9aafd92319
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-ed.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/component.h>
+#include <linux/container_of.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_managed.h>
+
+#include "dc-drv.h"
+#include "dc-pe.h"
+
+#define PIXENGCFG_STATIC 0x8
+#define POWERDOWN BIT(4)
+#define SYNC_MODE BIT(8)
+#define SINGLE 0
+#define DIV_MASK 0xff0000
+#define DIV(n) (((n) & 0xff) << 16)
+#define DIV_RESET 0x80
+
+#define PIXENGCFG_DYNAMIC 0xc
+
+#define PIXENGCFG_TRIGGER 0x14
+#define SYNC_TRIGGER BIT(0)
+
+#define STATICCONTROL 0x8
+#define KICK_MODE BIT(8)
+#define EXTERNAL BIT(8)
+#define PERFCOUNTMODE BIT(12)
+
+#define CONTROL 0xc
+#define GAMMAAPPLYENABLE BIT(0)
+
+struct dc_ed_priv {
+ struct dc_ed ed;
+ void __iomem *reg_pec;
+ void __iomem *reg_cfg;
+ u32 id;
+};
+
+static const enum dc_link_id src_sels[] = {
+ LINK_ID_NONE,
+ LINK_ID_CONSTFRAME0,
+ LINK_ID_CONSTFRAME1,
+ LINK_ID_CONSTFRAME4,
+ LINK_ID_CONSTFRAME5,
+ LINK_ID_LAYERBLEND3,
+ LINK_ID_LAYERBLEND2,
+ LINK_ID_LAYERBLEND1,
+ LINK_ID_LAYERBLEND0,
+};
+
+static inline struct dc_ed_priv *to_ed_priv(struct dc_ed *ed)
+{
+ return container_of(ed, struct dc_ed_priv, ed);
+}
+
+static inline u32 dc_pec_ed_read(struct dc_ed *ed, unsigned int offset)
+{
+ struct dc_ed_priv *priv = to_ed_priv(ed);
+
+ return readl(priv->reg_pec + offset);
+}
+
+static inline void
+dc_pec_ed_write(struct dc_ed *ed, unsigned int offset, u32 value)
+{
+ struct dc_ed_priv *priv = to_ed_priv(ed);
+
+ writel(value, priv->reg_pec + offset);
+}
+
+static inline void
+dc_pec_ed_write_mask(struct dc_ed *ed, unsigned int offset, u32 mask, u32 value)
+{
+ u32 tmp;
+
+ tmp = dc_pec_ed_read(ed, offset);
+ tmp &= ~mask;
+ dc_pec_ed_write(ed, offset, tmp | value);
+}
+
+static inline u32 dc_ed_read(struct dc_ed *ed, unsigned int offset)
+{
+ struct dc_ed_priv *priv = to_ed_priv(ed);
+
+ return readl(priv->reg_cfg + offset);
+}
+
+static inline void dc_ed_write(struct dc_ed *ed, unsigned int offset, u32 value)
+{
+ struct dc_ed_priv *priv = to_ed_priv(ed);
+
+ writel(value, priv->reg_cfg + offset);
+}
+
+static inline void
+dc_ed_write_mask(struct dc_ed *ed, unsigned int offset, u32 mask, u32 value)
+{
+ u32 tmp;
+
+ tmp = dc_ed_read(ed, offset);
+ tmp &= ~mask;
+ dc_ed_write(ed, offset, tmp | value);
+}
+
+static void dc_ed_pec_enable_shden(struct dc_ed *ed)
+{
+ dc_pec_ed_write_mask(ed, PIXENGCFG_STATIC, SHDEN, SHDEN);
+}
+
+static void dc_ed_pec_poweron(struct dc_ed *ed)
+{
+ dc_pec_ed_write_mask(ed, PIXENGCFG_STATIC, POWERDOWN, 0);
+}
+
+static void dc_ed_pec_sync_mode_single(struct dc_ed *ed)
+{
+ dc_pec_ed_write_mask(ed, PIXENGCFG_STATIC, SYNC_MODE, SINGLE);
+}
+
+static void dc_ed_pec_div_reset(struct dc_ed *ed)
+{
+ dc_pec_ed_write_mask(ed, PIXENGCFG_STATIC, DIV_MASK, DIV(DIV_RESET));
+}
+
+void dc_ed_pec_src_sel(struct dc_ed *ed, enum dc_link_id src)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(src_sels); i++) {
+ if (src_sels[i] == src) {
+ dc_pec_ed_write(ed, PIXENGCFG_DYNAMIC, src);
+ return;
+ }
+ }
+}
+
+void dc_ed_pec_sync_trigger(struct dc_ed *ed)
+{
+ dc_pec_ed_write(ed, PIXENGCFG_TRIGGER, SYNC_TRIGGER);
+}
+
+static void dc_ed_enable_shden(struct dc_ed *ed)
+{
+ dc_ed_write_mask(ed, STATICCONTROL, SHDEN, SHDEN);
+}
+
+static void dc_ed_kick_mode_external(struct dc_ed *ed)
+{
+ dc_ed_write_mask(ed, STATICCONTROL, KICK_MODE, EXTERNAL);
+}
+
+static void dc_ed_disable_perfcountmode(struct dc_ed *ed)
+{
+ dc_ed_write_mask(ed, STATICCONTROL, PERFCOUNTMODE, 0);
+}
+
+static void dc_ed_disable_gamma_apply(struct dc_ed *ed)
+{
+ dc_ed_write_mask(ed, CONTROL, GAMMAAPPLYENABLE, 0);
+}
+
+void dc_ed_init(struct dc_ed *ed)
+{
+ dc_ed_pec_src_sel(ed, LINK_ID_NONE);
+ dc_ed_pec_enable_shden(ed);
+ dc_ed_pec_poweron(ed);
+ dc_ed_pec_sync_mode_single(ed);
+ dc_ed_pec_div_reset(ed);
+ dc_ed_enable_shden(ed);
+ dc_ed_disable_perfcountmode(ed);
+ dc_ed_kick_mode_external(ed);
+ dc_ed_disable_gamma_apply(ed);
+}
+
+static int dc_ed_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_pe *pe = dc_drm->pe;
+ struct dc_ed_priv *priv;
+ int ret;
+
+ priv = drmm_kzalloc(&dc_drm->base, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg_pec = devm_platform_ioremap_resource_byname(pdev, "pec");
+ if (IS_ERR(priv->reg_pec))
+ return PTR_ERR(priv->reg_pec);
+
+ priv->reg_cfg = devm_platform_ioremap_resource_byname(pdev, "cfg");
+ if (IS_ERR(priv->reg_cfg))
+ return PTR_ERR(priv->reg_cfg);
+
+ priv->ed.irq_shdld = platform_get_irq_byname(pdev, "shdload");
+ if (priv->ed.irq_shdld < 0)
+ return priv->ed.irq_shdld;
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-ed-id", &priv->id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ priv->ed.dev = dev;
+
+ switch (priv->id) {
+ case 0:
+ pe->ed_cont[0] = &priv->ed;
+ break;
+ case 1:
+ pe->ed_cont[1] = &priv->ed;
+ break;
+ case 4:
+ pe->ed_safe[0] = &priv->ed;
+ break;
+ case 5:
+ pe->ed_safe[1] = &priv->ed;
+ break;
+ }
+
+ return 0;
+}
+
+static const struct component_ops dc_ed_ops = {
+ .bind = dc_ed_bind,
+};
+
+static int dc_ed_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_ed_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_ed_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_ed_ops);
+}
+
+static const struct of_device_id dc_ed_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-extdst", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_ed_dt_ids);
+
+struct platform_driver dc_ed_driver = {
+ .probe = dc_ed_probe,
+ .remove_new = dc_ed_remove,
+ .driver = {
+ .name = "imx8-dc-extdst",
+ .of_match_table = dc_ed_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-fl.c b/drivers/gpu/drm/imx/dc/dc-fl.c
new file mode 100644
index 000000000000..c6b46595c864
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-fl.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_managed.h>
+#include <drm/drm_fourcc.h>
+
+#include "dc-drv.h"
+#include "dc-fu.h"
+#include "dc-pe.h"
+
+#define FRAMEDIMENSIONS 0x150
+
+struct dc_fl {
+ struct dc_fu fu;
+ u32 id;
+};
+
+static void
+dc_fl_set_fmt(struct dc_fu *fu, const struct drm_format_info *format)
+{
+ u32 bits = 0, shifts = 0;
+
+ dc_fu_set_src_bpp(fu, format->cpp[0] * 8);
+
+ dc_fu_write_mask(fu, LAYERPROPERTY(fu), YUVCONVERSIONMODE_MASK,
+ YUVCONVERSIONMODE(YUVCONVERSIONMODE_OFF));
+
+ dc_fu_get_pixel_format_bits(fu, format->format, &bits);
+ dc_fu_get_pixel_format_shifts(fu, format->format, &shifts);
+
+ dc_fu_write(fu, COLORCOMPONENTBITS(fu), bits);
+ dc_fu_write(fu, COLORCOMPONENTSHIFT(fu), shifts);
+}
+
+static void dc_fl_set_framedimensions(struct dc_fu *fu, int w, int h)
+{
+ dc_fu_write(fu, FRAMEDIMENSIONS, FRAMEWIDTH(w) | FRAMEHEIGHT(h));
+}
+
+static void dc_fl_init(struct dc_fu *fu)
+{
+ dc_fu_common_hw_init(fu);
+ dc_fu_shdldreq_sticky(fu, 0xff);
+}
+
+static void dc_fl_set_ops(struct dc_fu *fu)
+{
+ memcpy(&fu->ops, &dc_fu_common_ops, sizeof(dc_fu_common_ops));
+ fu->ops.init = dc_fl_init;
+ fu->ops.set_fmt = dc_fl_set_fmt;
+ fu->ops.set_framedimensions = dc_fl_set_framedimensions;
+}
+
+static int dc_fl_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_pe *pe = dc_drm->pe;
+ struct dc_fl *fl;
+ struct dc_fu *fu;
+ int ret;
+
+ fl = drmm_kzalloc(&dc_drm->base, sizeof(*fl), GFP_KERNEL);
+ if (!fl)
+ return -ENOMEM;
+
+ fu = &fl->fu;
+
+ fu->reg_pec = devm_platform_ioremap_resource_byname(pdev, "pec");
+ if (IS_ERR(fu->reg_pec))
+ return PTR_ERR(fu->reg_pec);
+
+ fu->reg_cfg = devm_platform_ioremap_resource_byname(pdev, "cfg");
+ if (IS_ERR(fu->reg_cfg))
+ return PTR_ERR(fu->reg_cfg);
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-fl-id", &fl->id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ fu->link_id = LINK_ID_FETCHLAYER0;
+ fu->id = DC_FETCHUNIT_FL0;
+ fu->sub_id = 0;
+ snprintf(fu->name, sizeof(fu->name), "FetchLayer%u", fl->id);
+
+ dc_fl_set_ops(fu);
+
+ pe->fu_disp[fu->id] = fu;
+
+ return 0;
+}
+
+static const struct component_ops dc_fl_ops = {
+ .bind = dc_fl_bind,
+};
+
+static int dc_fl_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_fl_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_fl_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_fl_ops);
+}
+
+static const struct of_device_id dc_fl_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-fetchlayer", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_fl_dt_ids);
+
+struct platform_driver dc_fl_driver = {
+ .probe = dc_fl_probe,
+ .remove_new = dc_fl_remove,
+ .driver = {
+ .name = "imx8-dc-fetchlayer",
+ .of_match_table = dc_fl_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-fu.c b/drivers/gpu/drm/imx/dc/dc-fu.c
new file mode 100644
index 000000000000..88793b2366fe
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-fu.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/bitops.h>
+#include <linux/math.h>
+
+#include "dc-fu.h"
+#include "dc-pe.h"
+
+#define STATICCONTROL 0x8
+#define SHDLDREQSTICKY(lm) (((lm) & 0xff) << 24)
+#define SHDLDREQSTICKY_MASK (0xff << 24)
+#define BASEADDRESSAUTOUPDATE(lm) (((lm) & 0xff) << 16)
+#define BASEADDRESSAUTOUPDATE_MASK (0xff << 16)
+
+#define BURSTBUFFERMANAGEMENT 0xc
+#define SETBURSTLENGTH(n) (((n) & 0x1f) << 8)
+#define SETBURSTLENGTH_MASK 0x1f00
+#define SETNUMBUFFERS(n) ((n) & 0xff)
+#define SETNUMBUFFERS_MASK 0xff
+#define LINEMODE_MASK 0x80000000
+#define LINEMODE_SHIFT 31
+
+#define BASEADDRESS(fu) (0x10 + SUBID_OFFSET + REG_OFFSET)
+
+#define SOURCEBUFFERATTRIBUTES(fu) (0x14 + SUBID_OFFSET + REG_OFFSET)
+#define BITSPERPIXEL_MASK 0x3f0000
+#define BITSPERPIXEL(bpp) (((bpp) & 0x3f) << 16)
+#define STRIDE_MASK 0xffff
+#define STRIDE(n) (((n) - 1) & 0xffff)
+
+#define LAYEROFFSET(fu) (0x24 + SUBID_OFFSET + REG_OFFSET)
+#define LAYERXOFFSET(x) ((x) & 0x7fff)
+#define LAYERYOFFSET(y) (((y) & 0x7fff) << 16)
+
+#define CLIPWINDOWOFFSET(fu) (0x28 + SUBID_OFFSET + REG_OFFSET)
+#define CLIPWINDOWXOFFSET(x) ((x) & 0x7fff)
+#define CLIPWINDOWYOFFSET(y) (((y) & 0x7fff) << 16)
+
+#define CLIPWINDOWDIMENSIONS(fu) (0x2c + SUBID_OFFSET + REG_OFFSET)
+#define CLIPWINDOWWIDTH(w) (((w) - 1) & 0x3fff)
+#define CLIPWINDOWHEIGHT(h) ((((h) - 1) & 0x3fff) << 16)
+
+#define CONSTANTCOLOR(fu) (0x30 + SUBID_OFFSET + REG_OFFSET)
+
+enum dc_linemode {
+ /*
+ * Mandatory setting for operation in the Display Controller.
+ * Works also for Blit Engine with marginal performance impact.
+ */
+ LINEMODE_DISPLAY = 0,
+};
+
+struct dc_fu_pixel_format {
+ u32 pixel_format;
+ u32 bits;
+ u32 shifts;
+};
+
+static const struct dc_fu_pixel_format pixel_formats[] = {
+ {
+ DRM_FORMAT_XRGB8888,
+ R_BITS(8) | G_BITS(8) | B_BITS(8) | A_BITS(0),
+ R_SHIFT(16) | G_SHIFT(8) | B_SHIFT(0) | A_SHIFT(0),
+ },
+};
+
+void dc_fu_get_pixel_format_bits(struct dc_fu *fu, u32 format, u32 *bits)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
+ if (pixel_formats[i].pixel_format == format) {
+ *bits = pixel_formats[i].bits;
+ return;
+ }
+ }
+}
+
+void
+dc_fu_get_pixel_format_shifts(struct dc_fu *fu, u32 format, u32 *shifts)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
+ if (pixel_formats[i].pixel_format == format) {
+ *shifts = pixel_formats[i].shifts;
+ return;
+ }
+ }
+}
+
+static void dc_fu_enable_shden(struct dc_fu *fu)
+{
+ dc_fu_write_mask(fu, STATICCONTROL, SHDEN, SHDEN);
+}
+
+static void dc_fu_baddr_autoupdate(struct dc_fu *fu, u8 layer_mask)
+{
+ dc_fu_write_mask(fu, STATICCONTROL, BASEADDRESSAUTOUPDATE_MASK,
+ BASEADDRESSAUTOUPDATE(layer_mask));
+}
+
+void dc_fu_shdldreq_sticky(struct dc_fu *fu, u8 layer_mask)
+{
+ dc_fu_write_mask(fu, STATICCONTROL, SHDLDREQSTICKY_MASK,
+ SHDLDREQSTICKY(layer_mask));
+}
+
+static void dc_fu_set_linemode(struct dc_fu *fu, enum dc_linemode mode)
+{
+ dc_fu_write_mask(fu, BURSTBUFFERMANAGEMENT, LINEMODE_MASK, mode);
+}
+
+static void dc_fu_set_numbuffers(struct dc_fu *fu, unsigned int num)
+{
+ dc_fu_write_mask(fu, BURSTBUFFERMANAGEMENT, SETNUMBUFFERS_MASK,
+ SETNUMBUFFERS(num));
+}
+
+static void dc_fu_set_burstlength(struct dc_fu *fu, dma_addr_t baddr)
+{
+ unsigned int burst_size, burst_length;
+
+ burst_size = 1 << __ffs(baddr);
+ burst_size = round_up(burst_size, 8);
+ burst_size = min(burst_size, 128U);
+ burst_length = burst_size / 8;
+
+ dc_fu_write_mask(fu, BURSTBUFFERMANAGEMENT, SETBURSTLENGTH_MASK,
+ SETBURSTLENGTH(burst_length));
+}
+
+static void dc_fu_set_baseaddress(struct dc_fu *fu, dma_addr_t baddr)
+{
+ dc_fu_write(fu, BASEADDRESS(fu), baddr);
+}
+
+void dc_fu_set_src_bpp(struct dc_fu *fu, unsigned int bpp)
+{
+ dc_fu_write_mask(fu, SOURCEBUFFERATTRIBUTES(fu), BITSPERPIXEL_MASK,
+ BITSPERPIXEL(bpp));
+}
+
+static void dc_fu_set_src_stride(struct dc_fu *fu, unsigned int stride)
+{
+ dc_fu_write_mask(fu, SOURCEBUFFERATTRIBUTES(fu), STRIDE_MASK,
+ STRIDE(stride));
+}
+
+static void dc_fu_set_src_buf_dimensions(struct dc_fu *fu, int w, int h)
+{
+ dc_fu_write(fu, SOURCEBUFFERDIMENSION(fu), LINEWIDTH(w) | LINECOUNT(h));
+}
+
+static void dc_fu_layeroffset(struct dc_fu *fu, unsigned int x, unsigned int y)
+{
+ dc_fu_write(fu, LAYEROFFSET(fu), LAYERXOFFSET(x) | LAYERYOFFSET(y));
+}
+
+static void dc_fu_clipoffset(struct dc_fu *fu, unsigned int x, unsigned int y)
+{
+ dc_fu_write(fu, CLIPWINDOWOFFSET(fu),
+ CLIPWINDOWXOFFSET(x) | CLIPWINDOWYOFFSET(y));
+}
+
+static void
+dc_fu_clipdimensions(struct dc_fu *fu, unsigned int w, unsigned int h)
+{
+ dc_fu_write(fu, CLIPWINDOWDIMENSIONS(fu),
+ CLIPWINDOWWIDTH(w) | CLIPWINDOWHEIGHT(h));
+}
+
+static void dc_fu_set_pixel_blend_mode(struct dc_fu *fu)
+{
+ dc_fu_write(fu, LAYERPROPERTY(fu), 0);
+ dc_fu_write(fu, CONSTANTCOLOR(fu), 0);
+}
+
+static void dc_fu_enable_src_buf(struct dc_fu *fu)
+{
+ dc_fu_write_mask(fu, LAYERPROPERTY(fu), SOURCEBUFFERENABLE,
+ SOURCEBUFFERENABLE);
+}
+
+static void dc_fu_disable_src_buf(struct dc_fu *fu)
+{
+ dc_fu_write_mask(fu, LAYERPROPERTY(fu), SOURCEBUFFERENABLE, 0);
+
+ if (fu->lb) {
+ dc_lb_pec_clken(fu->lb, CLKEN_DISABLE);
+ dc_lb_mode(fu->lb, LB_NEUTRAL);
+ }
+}
+
+static void dc_fu_set_layerblend(struct dc_fu *fu, struct dc_lb *lb)
+{
+ fu->lb = lb;
+}
+
+static enum dc_link_id dc_fu_get_link_id(struct dc_fu *fu)
+{
+ return fu->link_id;
+}
+
+static const char *dc_fu_get_name(struct dc_fu *fu)
+{
+ return fu->name;
+}
+
+const struct dc_fu_ops dc_fu_common_ops = {
+ .set_burstlength = dc_fu_set_burstlength,
+ .set_baseaddress = dc_fu_set_baseaddress,
+ .set_src_stride = dc_fu_set_src_stride,
+ .set_src_buf_dimensions = dc_fu_set_src_buf_dimensions,
+ .enable_src_buf = dc_fu_enable_src_buf,
+ .disable_src_buf = dc_fu_disable_src_buf,
+ .set_layerblend = dc_fu_set_layerblend,
+ .get_link_id = dc_fu_get_link_id,
+ .get_name = dc_fu_get_name,
+};
+
+const struct dc_fu_ops *dc_fu_get_ops(struct dc_fu *fu)
+{
+ return &fu->ops;
+}
+
+void dc_fu_common_hw_init(struct dc_fu *fu)
+{
+ dc_fu_baddr_autoupdate(fu, 0x0);
+ dc_fu_enable_shden(fu);
+ dc_fu_set_linemode(fu, LINEMODE_DISPLAY);
+ dc_fu_layeroffset(fu, 0x0, 0x0);
+ dc_fu_clipoffset(fu, 0x0, 0x0);
+ dc_fu_clipdimensions(fu, 0x0, 0x0);
+ dc_fu_set_numbuffers(fu, 16);
+ dc_fu_disable_src_buf(fu);
+ dc_fu_set_pixel_blend_mode(fu);
+}
diff --git a/drivers/gpu/drm/imx/dc/dc-fu.h b/drivers/gpu/drm/imx/dc/dc-fu.h
new file mode 100644
index 000000000000..c7c84db85d87
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-fu.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DC_FETCHUNIT_H__
+#define __DC_FETCHUNIT_H__
+
+#include <linux/io.h>
+#include <linux/types.h>
+
+#include <drm/drm_fourcc.h>
+
+#include "dc-pe.h"
+
+#define REG_OFFSET ((fu)->reg_offset)
+#define SUBID_OFFSET (((fu)->sub_id) * 0x28)
+
+#define SOURCEBUFFERDIMENSION(fu) (0x18 + SUBID_OFFSET + REG_OFFSET)
+#define LINEWIDTH(w) (((w) - 1) & 0x3fff)
+#define LINECOUNT(h) ((((h) - 1) & 0x3fff) << 16)
+
+#define COLORCOMPONENTBITS(fu) (0x1c + SUBID_OFFSET + REG_OFFSET)
+#define R_BITS(n) (((n) & 0xf) << 24)
+#define G_BITS(n) (((n) & 0xf) << 16)
+#define B_BITS(n) (((n) & 0xf) << 8)
+#define A_BITS(n) ((n) & 0xf)
+
+#define COLORCOMPONENTSHIFT(fu) (0x20 + SUBID_OFFSET + REG_OFFSET)
+#define R_SHIFT(n) (((n) & 0x1f) << 24)
+#define G_SHIFT(n) (((n) & 0x1f) << 16)
+#define B_SHIFT(n) (((n) & 0x1f) << 8)
+#define A_SHIFT(n) ((n) & 0x1f)
+
+#define LAYERPROPERTY(fu) (0x34 + SUBID_OFFSET + REG_OFFSET)
+#define YUVCONVERSIONMODE_MASK 0x60000
+#define YUVCONVERSIONMODE(m) (((m) & 0x3) << 17)
+#define SOURCEBUFFERENABLE BIT(31)
+#define FRAMEWIDTH(w) (((w) - 1) & 0x3fff)
+#define FRAMEHEIGHT(h) ((((h) - 1) & 0x3fff) << 16)
+#define INPUTSELECT_MASK 0x18
+#define INPUTSELECT(s) (((s) & 0x3) << 3)
+#define RASTERMODE_MASK 0x7
+#define RASTERMODE(m) ((m) & 0x7)
+
+enum dc_yuvconversionmode {
+ YUVCONVERSIONMODE_OFF,
+};
+
+enum dc_inputselect {
+ INPUTSELECT_INACTIVE,
+};
+
+enum dc_rastermode {
+ RASTERMODE_NORMAL,
+};
+
+enum {
+ DC_FETCHUNIT_FL0,
+ DC_FETCHUNIT_FW2,
+};
+
+struct dc_fu;
+struct dc_lb;
+
+struct dc_fu_ops {
+ void (*init)(struct dc_fu *fu);
+ void (*set_burstlength)(struct dc_fu *fu, dma_addr_t baddr);
+ void (*set_baseaddress)(struct dc_fu *fu, dma_addr_t baddr);
+ void (*set_src_stride)(struct dc_fu *fu, unsigned int stride);
+ void (*set_src_buf_dimensions)(struct dc_fu *fu, int w, int h);
+ void (*set_fmt)(struct dc_fu *fu, const struct drm_format_info *format);
+ void (*enable_src_buf)(struct dc_fu *fu);
+ void (*disable_src_buf)(struct dc_fu *fu);
+ void (*set_framedimensions)(struct dc_fu *fu, int w, int h);
+ void (*set_layerblend)(struct dc_fu *fu, struct dc_lb *lb);
+ enum dc_link_id (*get_link_id)(struct dc_fu *fu);
+ const char *(*get_name)(struct dc_fu *fu);
+};
+
+struct dc_fu {
+ void __iomem *reg_pec;
+ void __iomem *reg_cfg;
+ char name[13];
+ unsigned int reg_offset;
+ unsigned int id;
+ unsigned int sub_id; /* for fractional fetch units */
+ enum dc_link_id link_id;
+ struct dc_fu_ops ops;
+ struct dc_lb *lb;
+};
+
+extern const struct dc_fu_ops dc_fu_common_ops;
+
+static inline void
+dc_pec_fu_write(struct dc_fu *fu, unsigned int offset, u32 value)
+{
+ writel(value, fu->reg_pec + offset);
+}
+
+static inline u32 dc_fu_read(struct dc_fu *fu, unsigned int offset)
+{
+ return readl(fu->reg_cfg + offset);
+}
+
+static inline void dc_fu_write(struct dc_fu *fu, unsigned int offset, u32 value)
+{
+ writel(value, fu->reg_cfg + offset);
+}
+
+static inline void
+dc_fu_write_mask(struct dc_fu *fu, unsigned int offset, u32 mask, u32 value)
+{
+ u32 tmp;
+
+ tmp = dc_fu_read(fu, offset);
+ tmp &= ~mask;
+ dc_fu_write(fu, offset, tmp | value);
+}
+
+void dc_fu_get_pixel_format_bits(struct dc_fu *fu, u32 format, u32 *bits);
+void dc_fu_get_pixel_format_shifts(struct dc_fu *fu, u32 format, u32 *shifts);
+void dc_fu_shdldreq_sticky(struct dc_fu *fu, u8 layer_mask);
+void dc_fu_set_src_bpp(struct dc_fu *fu, unsigned int bpp);
+void dc_fu_common_hw_init(struct dc_fu *fu);
+
+const struct dc_fu_ops *dc_fu_get_ops(struct dc_fu *fu);
+
+#endif /* __DC_FETCHUNIT_H__ */
diff --git a/drivers/gpu/drm/imx/dc/dc-fw.c b/drivers/gpu/drm/imx/dc/dc-fw.c
new file mode 100644
index 000000000000..77258e59a7af
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-fw.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_managed.h>
+#include <drm/drm_fourcc.h>
+
+#include "dc-drv.h"
+#include "dc-fu.h"
+#include "dc-pe.h"
+
+#define PIXENGCFG_DYNAMIC 0x8
+
+#define FRAMEDIMENSIONS 0x150
+#define CONTROL 0x170
+
+struct dc_fw {
+ struct dc_fu fu;
+ u32 id;
+};
+
+static void
+dc_fw_set_fmt(struct dc_fu *fu, const struct drm_format_info *format)
+{
+ u32 val, bits = 0, shifts = 0;
+
+ dc_fu_set_src_bpp(fu, format->cpp[0] * 8);
+
+ val = dc_fu_read(fu, CONTROL);
+ val &= ~INPUTSELECT_MASK;
+ val &= ~RASTERMODE_MASK;
+ val |= INPUTSELECT(INPUTSELECT_INACTIVE);
+ val |= RASTERMODE(RASTERMODE_NORMAL);
+ dc_fu_write(fu, CONTROL, val);
+
+ val = dc_fu_read(fu, LAYERPROPERTY(fu));
+ val &= ~YUVCONVERSIONMODE_MASK;
+ val |= YUVCONVERSIONMODE(YUVCONVERSIONMODE_OFF);
+ dc_fu_write(fu, LAYERPROPERTY(fu), val);
+
+ dc_fu_get_pixel_format_bits(fu, format->format, &bits);
+ dc_fu_get_pixel_format_shifts(fu, format->format, &shifts);
+
+ dc_fu_write(fu, COLORCOMPONENTBITS(fu), bits);
+ dc_fu_write(fu, COLORCOMPONENTSHIFT(fu), shifts);
+}
+
+static void dc_fw_set_framedimensions(struct dc_fu *fu, int w, int h)
+{
+ dc_fu_write(fu, FRAMEDIMENSIONS, FRAMEWIDTH(w) | FRAMEHEIGHT(h));
+}
+
+static void dc_fw_init(struct dc_fu *fu)
+{
+ dc_pec_fu_write(fu, PIXENGCFG_DYNAMIC, LINK_ID_NONE);
+ dc_fu_common_hw_init(fu);
+ dc_fu_shdldreq_sticky(fu, 0xff);
+}
+
+static void dc_fw_set_ops(struct dc_fu *fu)
+{
+ memcpy(&fu->ops, &dc_fu_common_ops, sizeof(dc_fu_common_ops));
+ fu->ops.init = dc_fw_init;
+ fu->ops.set_fmt = dc_fw_set_fmt;
+ fu->ops.set_framedimensions = dc_fw_set_framedimensions;
+}
+
+static int dc_fw_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_pe *pe = dc_drm->pe;
+ struct dc_fw *fw;
+ struct dc_fu *fu;
+ int ret;
+
+ fw = drmm_kzalloc(&dc_drm->base, sizeof(*fw), GFP_KERNEL);
+ if (!fw)
+ return -ENOMEM;
+
+ fu = &fw->fu;
+
+ fu->reg_pec = devm_platform_ioremap_resource_byname(pdev, "pec");
+ if (IS_ERR(fu->reg_pec))
+ return PTR_ERR(fu->reg_pec);
+
+ fu->reg_cfg = devm_platform_ioremap_resource_byname(pdev, "cfg");
+ if (IS_ERR(fu->reg_cfg))
+ return PTR_ERR(fu->reg_cfg);
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-fw-id", &fw->id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ fu->link_id = LINK_ID_FETCHWARP2;
+ fu->id = DC_FETCHUNIT_FW2;
+ fu->sub_id = 0;
+ snprintf(fu->name, sizeof(fu->name), "FetchWarp%u", fw->id);
+
+ dc_fw_set_ops(fu);
+
+ pe->fu_disp[fu->id] = fu;
+
+ return 0;
+}
+
+static const struct component_ops dc_fw_ops = {
+ .bind = dc_fw_bind,
+};
+
+static int dc_fw_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_fw_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_fw_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_fw_ops);
+}
+
+static const struct of_device_id dc_fw_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-fetchwarp", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_fw_dt_ids);
+
+struct platform_driver dc_fw_driver = {
+ .probe = dc_fw_probe,
+ .remove_new = dc_fw_remove,
+ .driver = {
+ .name = "imx8-dc-fetchwarp",
+ .of_match_table = dc_fw_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-lb.c b/drivers/gpu/drm/imx/dc/dc-lb.c
new file mode 100644
index 000000000000..cd98777f68d1
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-lb.c
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/component.h>
+#include <linux/container_of.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_blend.h>
+#include <drm/drm_managed.h>
+
+#include "dc-drv.h"
+#include "dc-pe.h"
+
+#define PIXENGCFG_DYNAMIC 0x8
+#define PIXENGCFG_DYNAMIC_PRIM_SEL_MASK 0x3f
+#define PIXENGCFG_DYNAMIC_SEC_SEL_SHIFT 8
+#define PIXENGCFG_DYNAMIC_SEC_SEL_MASK 0x3f00
+
+#define STATICCONTROL 0x8
+#define SHDTOKSEL_MASK 0x18
+#define SHDTOKSEL(n) ((n) << 3)
+#define SHDLDSEL_MASK 0x6
+#define SHDLDSEL(n) ((n) << 1)
+
+#define CONTROL 0xc
+#define CTRL_MODE_MASK BIT(0)
+
+#define BLENDCONTROL 0x10
+#define ALPHA(a) (((a) & 0xff) << 16)
+#define PRIM_C_BLD_FUNC__ZERO 0x0
+#define SEC_C_BLD_FUNC__CONST_ALPHA (0x6 << 4)
+#define PRIM_A_BLD_FUNC__ZERO (0x0 << 8)
+#define SEC_A_BLD_FUNC__ZERO (0x0 << 12)
+
+#define POSITION 0x14
+#define XPOS(x) ((x) & 0x7fff)
+#define YPOS(y) (((y) & 0x7fff) << 16)
+
+struct dc_lb_priv {
+ struct dc_lb lb;
+ void __iomem *reg_pec;
+ void __iomem *reg_cfg;
+ enum dc_link_id link;
+};
+
+enum dc_lb_shadow_sel {
+ BOTH = 0x2,
+};
+
+static const enum dc_link_id lb_links[] = {
+ LINK_ID_LAYERBLEND0,
+ LINK_ID_LAYERBLEND1,
+ LINK_ID_LAYERBLEND2,
+ LINK_ID_LAYERBLEND3,
+};
+
+static const enum dc_link_id prim_sels[] = {
+ /* common options */
+ LINK_ID_NONE,
+ LINK_ID_CONSTFRAME0,
+ LINK_ID_CONSTFRAME1,
+ LINK_ID_CONSTFRAME4,
+ LINK_ID_CONSTFRAME5,
+ /*
+ * special options:
+ * layerblend(n) has n special options,
+ * from layerblend0 to layerblend(n - 1), e.g.,
+ * layerblend3 has 3 special options -
+ * layerblend0/1/2.
+ */
+ LINK_ID_LAYERBLEND0,
+ LINK_ID_LAYERBLEND1,
+ LINK_ID_LAYERBLEND2,
+ LINK_ID_LAYERBLEND3,
+};
+
+static const enum dc_link_id sec_sels[] = {
+ LINK_ID_NONE,
+ LINK_ID_FETCHWARP2,
+ LINK_ID_FETCHLAYER0,
+};
+
+static inline struct dc_lb_priv *to_lb_priv(struct dc_lb *lb)
+{
+ return container_of(lb, struct dc_lb_priv, lb);
+}
+
+static inline u32 dc_pec_lb_read(struct dc_lb *lb, unsigned int offset)
+{
+ struct dc_lb_priv *priv = to_lb_priv(lb);
+
+ return readl(priv->reg_pec + offset);
+}
+
+static inline void
+dc_pec_lb_write(struct dc_lb *lb, unsigned int offset, u32 value)
+{
+ struct dc_lb_priv *priv = to_lb_priv(lb);
+
+ writel(value, priv->reg_pec + offset);
+}
+
+static inline void
+dc_pec_lb_write_mask(struct dc_lb *lb, unsigned int offset, u32 mask, u32 value)
+{
+ u32 tmp;
+
+ tmp = dc_pec_lb_read(lb, offset);
+ tmp &= ~mask;
+ dc_pec_lb_write(lb, offset, tmp | value);
+}
+
+static inline u32 dc_lb_read(struct dc_lb *lb, unsigned int offset)
+{
+ struct dc_lb_priv *priv = to_lb_priv(lb);
+
+ return readl(priv->reg_cfg + offset);
+}
+
+static inline void dc_lb_write(struct dc_lb *lb, unsigned int offset, u32 value)
+{
+ struct dc_lb_priv *priv = to_lb_priv(lb);
+
+ writel(value, priv->reg_cfg + offset);
+}
+
+static inline void
+dc_lb_write_mask(struct dc_lb *lb, unsigned int offset, u32 mask, u32 value)
+{
+ u32 tmp;
+
+ tmp = dc_lb_read(lb, offset);
+ tmp &= ~mask;
+ dc_lb_write(lb, offset, tmp | value);
+}
+
+enum dc_link_id dc_lb_get_link_id(struct dc_lb *lb)
+{
+ struct dc_lb_priv *priv = to_lb_priv(lb);
+
+ return priv->link;
+}
+
+void dc_lb_pec_dynamic_prim_sel(struct dc_lb *lb, enum dc_link_id prim)
+{
+ struct dc_lb_priv *priv = to_lb_priv(lb);
+ int fixed_sels_num = ARRAY_SIZE(prim_sels) - 4;
+ int i;
+
+ for (i = 0; i < fixed_sels_num + priv->lb.id; i++) {
+ if (prim_sels[i] == prim) {
+ dc_pec_lb_write_mask(lb, PIXENGCFG_DYNAMIC,
+ PIXENGCFG_DYNAMIC_PRIM_SEL_MASK,
+ prim);
+ return;
+ }
+ }
+}
+
+void dc_lb_pec_dynamic_sec_sel(struct dc_lb *lb, enum dc_link_id sec)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sec_sels); i++) {
+ if (sec_sels[i] == sec) {
+ dc_pec_lb_write_mask(lb, PIXENGCFG_DYNAMIC,
+ PIXENGCFG_DYNAMIC_SEC_SEL_MASK,
+ sec << PIXENGCFG_DYNAMIC_SEC_SEL_SHIFT);
+ return;
+ }
+ }
+}
+
+void dc_lb_pec_clken(struct dc_lb *lb, enum dc_pec_clken clken)
+{
+ dc_pec_lb_write_mask(lb, PIXENGCFG_DYNAMIC, CLKEN_MASK, CLKEN(clken));
+}
+
+static void dc_lb_enable_shden(struct dc_lb *lb)
+{
+ dc_lb_write_mask(lb, STATICCONTROL, SHDEN, SHDEN);
+}
+
+static void dc_lb_shdtoksel(struct dc_lb *lb, enum dc_lb_shadow_sel sel)
+{
+ dc_lb_write_mask(lb, STATICCONTROL, SHDTOKSEL_MASK, SHDTOKSEL(sel));
+}
+
+static void dc_lb_shdldsel(struct dc_lb *lb, enum dc_lb_shadow_sel sel)
+{
+ dc_lb_write_mask(lb, STATICCONTROL, SHDLDSEL_MASK, SHDLDSEL(sel));
+}
+
+void dc_lb_mode(struct dc_lb *lb, enum dc_lb_mode mode)
+{
+ dc_lb_write_mask(lb, CONTROL, CTRL_MODE_MASK, mode);
+}
+
+void dc_lb_blendcontrol(struct dc_lb *lb)
+{
+ u32 val = PRIM_A_BLD_FUNC__ZERO | SEC_A_BLD_FUNC__ZERO |
+ PRIM_C_BLD_FUNC__ZERO | SEC_C_BLD_FUNC__CONST_ALPHA |
+ ALPHA(DRM_BLEND_ALPHA_OPAQUE >> 8);
+
+ dc_lb_write(lb, BLENDCONTROL, val);
+}
+
+void dc_lb_position(struct dc_lb *lb, int x, int y)
+{
+ dc_lb_write(lb, POSITION, XPOS(x) | YPOS(y));
+}
+
+unsigned int dc_lb_get_id(struct dc_lb *lb)
+{
+ return lb->id;
+}
+
+void dc_lb_init(struct dc_lb *lb)
+{
+ dc_lb_pec_dynamic_prim_sel(lb, LINK_ID_NONE);
+ dc_lb_pec_dynamic_sec_sel(lb, LINK_ID_NONE);
+ dc_lb_pec_clken(lb, CLKEN_DISABLE);
+ dc_lb_shdldsel(lb, BOTH);
+ dc_lb_shdtoksel(lb, BOTH);
+ dc_lb_enable_shden(lb);
+}
+
+static int dc_lb_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = data;
+ struct dc_pe *pe = dc_drm->pe;
+ struct dc_lb_priv *priv;
+ int ret;
+
+ priv = drmm_kzalloc(&dc_drm->base, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg_pec = devm_platform_ioremap_resource_byname(pdev, "pec");
+ if (IS_ERR(priv->reg_pec))
+ return PTR_ERR(priv->reg_pec);
+
+ priv->reg_cfg = devm_platform_ioremap_resource_byname(pdev, "cfg");
+ if (IS_ERR(priv->reg_cfg))
+ return PTR_ERR(priv->reg_cfg);
+
+ ret = of_property_read_u32(dev->of_node, "fsl,dc-lb-id", &priv->lb.id);
+ if (ret) {
+ dev_err(dev, "failed to get instance number: %d\n", ret);
+ return ret;
+ }
+
+ priv->link = lb_links[priv->lb.id];
+
+ pe->lb[priv->lb.id] = &priv->lb;
+
+ return 0;
+}
+
+static const struct component_ops dc_lb_ops = {
+ .bind = dc_lb_bind,
+};
+
+static int dc_lb_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_lb_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_lb_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_lb_ops);
+}
+
+static const struct of_device_id dc_lb_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-layerblend", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_lb_dt_ids);
+
+struct platform_driver dc_lb_driver = {
+ .probe = dc_lb_probe,
+ .remove_new = dc_lb_remove,
+ .driver = {
+ .name = "imx8-dc-layerblend",
+ .of_match_table = dc_lb_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-pe.c b/drivers/gpu/drm/imx/dc/dc-pe.c
new file mode 100644
index 000000000000..a20a5adab231
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-pe.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_managed.h>
+
+#include "dc-drv.h"
+#include "dc-fu.h"
+#include "dc-pe.h"
+
+struct dc_pe_priv {
+ struct dc_pe engine;
+ struct clk *clk_axi;
+};
+
+static int dc_pe_bind(struct device *dev, struct device *master, void *data)
+{
+ struct dc_drm_device *dc_drm = data;
+ struct dc_pe_priv *priv;
+ int ret;
+
+ priv = drmm_kzalloc(&dc_drm->base, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk_axi = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk_axi))
+ return dev_err_probe(dev, PTR_ERR(priv->clk_axi),
+ "failed to get AXI clock\n");
+
+ priv->engine.dev = dev;
+
+ dev_set_drvdata(dev, priv);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ dc_drm->pe = &priv->engine;
+
+ return 0;
+}
+
+static const struct component_ops dc_pe_ops = {
+ .bind = dc_pe_bind,
+};
+
+static int dc_pe_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = devm_of_platform_populate(&pdev->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = component_add(&pdev->dev, &dc_pe_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_pe_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_pe_ops);
+}
+
+static int dc_pe_runtime_suspend(struct device *dev)
+{
+ struct dc_pe_priv *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->clk_axi);
+
+ return 0;
+}
+
+static int dc_pe_runtime_resume(struct device *dev)
+{
+ struct dc_pe_priv *priv = dev_get_drvdata(dev);
+ struct dc_pe *engine = &priv->engine;
+ int i, ret;
+
+ ret = clk_prepare_enable(priv->clk_axi);
+ if (ret) {
+ dev_err(dev, "failed to enable AXI clock: %d\n", ret);
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(engine->cf_safe); i++)
+ dc_cf_init(engine->cf_safe[i]);
+
+ for (i = 0; i < ARRAY_SIZE(engine->cf_cont); i++)
+ dc_cf_init(engine->cf_cont[i]);
+
+ for (i = 0; i < ARRAY_SIZE(engine->ed_safe); i++)
+ dc_ed_init(engine->ed_safe[i]);
+
+ for (i = 0; i < ARRAY_SIZE(engine->ed_cont); i++)
+ dc_ed_init(engine->ed_cont[i]);
+
+ for (i = 0; i < ARRAY_SIZE(engine->fu_disp); i++)
+ engine->fu_disp[i]->ops.init(engine->fu_disp[i]);
+
+ for (i = 0; i < ARRAY_SIZE(engine->lb); i++)
+ dc_lb_init(engine->lb[i]);
+
+ return 0;
+}
+
+static const struct dev_pm_ops dc_pe_pm_ops = {
+ RUNTIME_PM_OPS(dc_pe_runtime_suspend, dc_pe_runtime_resume, NULL)
+};
+
+static const struct of_device_id dc_pe_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-pixel-engine", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_pe_dt_ids);
+
+struct platform_driver dc_pe_driver = {
+ .probe = dc_pe_probe,
+ .remove_new = dc_pe_remove,
+ .driver = {
+ .name = "imx8-dc-pixel-engine",
+ .of_match_table = dc_pe_dt_ids,
+ .pm = pm_sleep_ptr(&dc_pe_pm_ops),
+ },
+};
diff --git a/drivers/gpu/drm/imx/dc/dc-pe.h b/drivers/gpu/drm/imx/dc/dc-pe.h
new file mode 100644
index 000000000000..82fee7fe112d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-pe.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DC_PIXEL_ENGINE_H__
+#define __DC_PIXEL_ENGINE_H__
+
+#include <linux/device.h>
+
+#include "dc-de.h"
+
+#define SHDEN BIT(0)
+
+#define CLKEN_MASK_SHIFT 24
+#define CLKEN_MASK (0x3 << CLKEN_MASK_SHIFT)
+#define CLKEN(n) ((n) << CLKEN_MASK_SHIFT)
+
+#define DC_DISP_FETCHUNIT_CNT 2
+#define DC_LAYERBLEND_CNT 4
+
+enum dc_link_id {
+ LINK_ID_NONE = 0x00,
+ LINK_ID_CONSTFRAME0 = 0x0c,
+ LINK_ID_CONSTFRAME4 = 0x0e,
+ LINK_ID_CONSTFRAME1 = 0x10,
+ LINK_ID_CONSTFRAME5 = 0x12,
+ LINK_ID_FETCHWARP2 = 0x14,
+ LINK_ID_FETCHLAYER0 = 0x1a,
+ LINK_ID_LAYERBLEND0 = 0x21,
+ LINK_ID_LAYERBLEND1 = 0x22,
+ LINK_ID_LAYERBLEND2 = 0x23,
+ LINK_ID_LAYERBLEND3 = 0x24,
+};
+
+enum dc_lb_mode {
+ LB_NEUTRAL, /* Output is same as primary input. */
+ LB_BLEND,
+};
+
+enum dc_pec_clken {
+ CLKEN_DISABLE,
+ CLKEN_AUTOMATIC,
+};
+
+struct dc_cf {
+};
+
+struct dc_ed {
+ struct device *dev;
+ int irq_shdld;
+};
+
+struct dc_lb {
+ int id;
+};
+
+struct dc_pe {
+ struct device *dev;
+ struct dc_cf *cf_safe[DC_DISPLAYS];
+ struct dc_cf *cf_cont[DC_DISPLAYS];
+ struct dc_ed *ed_safe[DC_DISPLAYS];
+ struct dc_ed *ed_cont[DC_DISPLAYS];
+ struct dc_fu *fu_disp[DC_DISP_FETCHUNIT_CNT];
+ struct dc_lb *lb[DC_LAYERBLEND_CNT];
+};
+
+/* Constant Frame Unit */
+enum dc_link_id dc_cf_get_link_id(struct dc_cf *cf);
+void dc_cf_framedimensions(struct dc_cf *cf, unsigned int w, unsigned int h);
+void dc_cf_constantcolor_black(struct dc_cf *cf);
+void dc_cf_constantcolor_blue(struct dc_cf *cf);
+void dc_cf_init(struct dc_cf *cf);
+
+/* External Destination Unit */
+void dc_ed_pec_src_sel(struct dc_ed *ed, enum dc_link_id src);
+void dc_ed_pec_sync_trigger(struct dc_ed *ed);
+void dc_ed_init(struct dc_ed *ed);
+
+/* Layer Blend Unit */
+enum dc_link_id dc_lb_get_link_id(struct dc_lb *lb);
+void dc_lb_pec_dynamic_prim_sel(struct dc_lb *lb, enum dc_link_id prim);
+void dc_lb_pec_dynamic_sec_sel(struct dc_lb *lb, enum dc_link_id sec);
+void dc_lb_pec_clken(struct dc_lb *lb, enum dc_pec_clken clken);
+void dc_lb_mode(struct dc_lb *lb, enum dc_lb_mode mode);
+void dc_lb_blendcontrol(struct dc_lb *lb);
+void dc_lb_position(struct dc_lb *lb, int x, int y);
+unsigned int dc_lb_get_id(struct dc_lb *lb);
+void dc_lb_init(struct dc_lb *lb);
+
+#endif /* __DC_PIXEL_ENGINE_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH 08/10] drm/imx: Add i.MX8qxp Display Controller interrupt controller
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (6 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 07/10] drm/imx: Add i.MX8qxp Display Controller pixel engine Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-05 9:09 ` [PATCH 09/10] drm/imx: Add i.MX8qxp Display Controller KMS Liu Ying
` (2 subsequent siblings)
10 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/drm/imx/dc/Kconfig | 1 +
drivers/gpu/drm/imx/dc/Makefile | 2 +-
drivers/gpu/drm/imx/dc/dc-drv.c | 1 +
drivers/gpu/drm/imx/dc/dc-drv.h | 1 +
drivers/gpu/drm/imx/dc/dc-ic.c | 249 ++++++++++++++++++++++++++++++++
5 files changed, 253 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/imx/dc/dc-ic.c
diff --git a/drivers/gpu/drm/imx/dc/Kconfig b/drivers/gpu/drm/imx/dc/Kconfig
index 32d7471c49d0..b66b815fbdf1 100644
--- a/drivers/gpu/drm/imx/dc/Kconfig
+++ b/drivers/gpu/drm/imx/dc/Kconfig
@@ -1,5 +1,6 @@
config DRM_IMX8_DC
tristate "Freescale i.MX8 Display Controller Graphics"
depends on DRM && COMMON_CLK && OF && (ARCH_MXC || COMPILE_TEST)
+ select GENERIC_IRQ_CHIP
help
enable Freescale i.MX8 Display Controller(DC) graphics support
diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makefile
index 2942ae6fd5bd..1ce3e8a8db22 100644
--- a/drivers/gpu/drm/imx/dc/Makefile
+++ b/drivers/gpu/drm/imx/dc/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
imx8-dc-drm-objs := dc-cf.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o dc-fu.o \
- dc-fw.o dc-lb.o dc-pe.o dc-tc.o
+ dc-fw.o dc-ic.o dc-lb.o dc-pe.o dc-tc.o
obj-$(CONFIG_DRM_IMX8_DC) += imx8-dc-drm.o
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.c b/drivers/gpu/drm/imx/dc/dc-drv.c
index 7c64acc863ad..fd68861f770a 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.c
+++ b/drivers/gpu/drm/imx/dc/dc-drv.c
@@ -15,6 +15,7 @@ static struct platform_driver * const dc_drivers[] = {
&dc_fg_driver,
&dc_fl_driver,
&dc_fw_driver,
+ &dc_ic_driver,
&dc_lb_driver,
&dc_pe_driver,
&dc_tc_driver,
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.h b/drivers/gpu/drm/imx/dc/dc-drv.h
index c687a36b8153..3b11f4862c6c 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.h
+++ b/drivers/gpu/drm/imx/dc/dc-drv.h
@@ -25,6 +25,7 @@ extern struct platform_driver dc_de_driver;
extern struct platform_driver dc_fg_driver;
extern struct platform_driver dc_fl_driver;
extern struct platform_driver dc_fw_driver;
+extern struct platform_driver dc_ic_driver;
extern struct platform_driver dc_lb_driver;
extern struct platform_driver dc_pe_driver;
extern struct platform_driver dc_tc_driver;
diff --git a/drivers/gpu/drm/imx/dc/dc-ic.c b/drivers/gpu/drm/imx/dc/dc-ic.c
new file mode 100644
index 000000000000..8540a0414b39
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-ic.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_managed.h>
+
+#include "dc-drv.h"
+
+#define USERINTERRUPTMASK(n) (0x8 + 4 * (n))
+#define INTERRUPTENABLE(n) (0x10 + 4 * (n))
+#define INTERRUPTCLEAR(n) (0x20 + 4 * (n))
+#define INTERRUPTSTATUS(n) (0x28 + 4 * (n))
+#define USERINTERRUPTENABLE(n) (0x40 + 4 * (n))
+#define USERINTERRUPTCLEAR(n) (0x50 + 4 * (n))
+#define USERINTERRUPTSTATUS(n) (0x58 + 4 * (n))
+
+#define IRQ_COUNT 49
+#define IRQ_RESERVED 35
+#define REG_NUM 2
+
+struct dc_ic_data {
+ void __iomem *regs;
+ struct clk *clk_axi;
+ int irq[IRQ_COUNT];
+ struct irq_domain *domain;
+};
+
+struct dc_ic_entry {
+ struct dc_ic_data *data;
+ int irq;
+};
+
+static void dc_ic_irq_handler(struct irq_desc *desc)
+{
+ struct dc_ic_entry *entry = irq_desc_get_handler_data(desc);
+ struct dc_ic_data *data = entry->data;
+ unsigned int virq;
+ u32 status;
+
+ chained_irq_enter(irq_desc_get_chip(desc), desc);
+
+ status = readl(data->regs + USERINTERRUPTSTATUS(entry->irq / 32));
+ status &= readl(data->regs + USERINTERRUPTENABLE(entry->irq / 32));
+
+ if (status & BIT(entry->irq % 32)) {
+ virq = irq_linear_revmap(data->domain, entry->irq);
+ if (virq)
+ generic_handle_irq(virq);
+ }
+
+ chained_irq_exit(irq_desc_get_chip(desc), desc);
+}
+
+static const unsigned long unused_irq[REG_NUM] = {0x00000000, 0xfffe0008};
+
+static int
+dc_ic_bind(struct device *dev, struct device *master, void *master_data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dc_drm_device *dc_drm = master_data;
+ struct dc_ic_entry *entry;
+ struct irq_chip_generic *gc;
+ struct dc_ic_data *data;
+ struct irq_chip_type *ct;
+ int i, ret;
+
+ data = drmm_kzalloc(&dc_drm->base, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ entry = drmm_kcalloc(&dc_drm->base, IRQ_COUNT, sizeof(*entry),
+ GFP_KERNEL);
+ if (!entry)
+ return -ENOMEM;
+
+ data->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(data->regs)) {
+ dev_err(dev, "failed to initialize reg\n");
+ return PTR_ERR(data->regs);
+ }
+
+ data->clk_axi = devm_clk_get(dev, NULL);
+ if (IS_ERR(data->clk_axi))
+ return dev_err_probe(dev, PTR_ERR(data->clk_axi),
+ "failed to get AXI clock\n");
+
+ dev_set_drvdata(dev, data);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret < 0) {
+ dev_err(dev, "failed to get runtime PM sync: %d\n", ret);
+ return ret;
+ }
+
+ for (i = 0; i < REG_NUM; i++) {
+ /* mask and clear all interrupts */
+ writel(0x0, data->regs + USERINTERRUPTENABLE(i));
+ writel(0x0, data->regs + INTERRUPTENABLE(i));
+ writel(0xffffffff, data->regs + USERINTERRUPTCLEAR(i));
+ writel(0xffffffff, data->regs + INTERRUPTCLEAR(i));
+
+ /* set all interrupts to user mode */
+ writel(0xffffffff, data->regs + USERINTERRUPTMASK(i));
+ }
+
+ data->domain = irq_domain_add_linear(dev->of_node, IRQ_COUNT,
+ &irq_generic_chip_ops, data);
+ if (!data->domain) {
+ dev_err(dev, "failed to create IRQ domain\n");
+ pm_runtime_put(dev);
+ return -ENOMEM;
+ }
+ irq_domain_set_pm_device(data->domain, &pdev->dev);
+
+ ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, "DC",
+ handle_level_irq, 0, 0, 0);
+ if (ret) {
+ dev_err(dev, "failed to alloc generic IRQ chips: %d\n", ret);
+ irq_domain_remove(data->domain);
+ pm_runtime_put(dev);
+ return ret;
+ }
+
+ for (i = 0; i < IRQ_COUNT; i += 32) {
+ gc = irq_get_domain_generic_chip(data->domain, i);
+ gc->reg_base = data->regs;
+ gc->unused = unused_irq[i / 32];
+ ct = gc->chip_types;
+ ct->chip.irq_ack = irq_gc_ack_set_bit;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ct->regs.ack = USERINTERRUPTCLEAR(i / 32);
+ ct->regs.mask = USERINTERRUPTENABLE(i / 32);
+ }
+
+ for (i = 0; i < IRQ_COUNT; i++) {
+ /* skip the reserved IRQ */
+ if (i == IRQ_RESERVED)
+ continue;
+
+ data->irq[i] = irq_of_parse_and_map(dev->of_node, i);
+
+ entry[i].data = data;
+ entry[i].irq = i;
+
+ irq_set_chained_handler_and_data(data->irq[i],
+ dc_ic_irq_handler, &entry[i]);
+ }
+
+ return 0;
+}
+
+static void
+dc_ic_unbind(struct device *dev, struct device *master, void *master_data)
+{
+ struct dc_ic_data *data = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < IRQ_COUNT; i++) {
+ if (i == IRQ_RESERVED)
+ continue;
+
+ irq_set_chained_handler_and_data(data->irq[i], NULL, NULL);
+ }
+
+ irq_domain_remove(data->domain);
+
+ pm_runtime_put_sync(dev);
+}
+
+static const struct component_ops dc_ic_ops = {
+ .bind = dc_ic_bind,
+ .unbind = dc_ic_unbind,
+};
+
+static int dc_ic_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = component_add(&pdev->dev, &dc_ic_ops);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component\n");
+
+ return 0;
+}
+
+static void dc_ic_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &dc_ic_ops);
+}
+
+static int dc_ic_runtime_suspend(struct device *dev)
+{
+ struct dc_ic_data *data = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(data->clk_axi);
+
+ return 0;
+}
+
+static int dc_ic_runtime_resume(struct device *dev)
+{
+ struct dc_ic_data *data = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(data->clk_axi);
+ if (ret)
+ dev_err(dev, "failed to enable AXI clock: %d\n", ret);
+
+ return ret;
+}
+
+static const struct dev_pm_ops dc_ic_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ RUNTIME_PM_OPS(dc_ic_runtime_suspend, dc_ic_runtime_resume, NULL)
+};
+
+static const struct of_device_id dc_ic_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc-intc", },
+ { /* sentinel */ }
+};
+
+struct platform_driver dc_ic_driver = {
+ .probe = dc_ic_probe,
+ .remove_new = dc_ic_remove,
+ .driver = {
+ .name = "imx8-dc-intc",
+ .of_match_table = dc_ic_dt_ids,
+ .pm = pm_sleep_ptr(&dc_ic_pm_ops),
+ },
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH 09/10] drm/imx: Add i.MX8qxp Display Controller KMS
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (7 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 08/10] drm/imx: Add i.MX8qxp Display Controller interrupt controller Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-07 19:16 ` Markus Elfring
2024-07-05 9:09 ` [PATCH 10/10] MAINTAINERS: Add maintainer for i.MX8qxp Display Controller Liu Ying
2024-07-05 12:57 ` [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Francesco Dolcini
10 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer. Add kernel
mode setting support for the display controller part with two CRTCs and
two primary planes(backed by FetchLayer and FetchWarp respectively). The
registers of the display controller is accessed without command sequencer
involved, instead just by using CPU. The command sequencer is supposed to
be used by the blit engine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/drm/imx/dc/Kconfig | 2 +
drivers/gpu/drm/imx/dc/Makefile | 5 +-
drivers/gpu/drm/imx/dc/dc-crtc.c | 578 ++++++++++++++++++++++++++++++
drivers/gpu/drm/imx/dc/dc-crtc.h | 67 ++++
drivers/gpu/drm/imx/dc/dc-de.h | 3 +
drivers/gpu/drm/imx/dc/dc-drv.c | 241 +++++++++++++
drivers/gpu/drm/imx/dc/dc-drv.h | 21 ++
drivers/gpu/drm/imx/dc/dc-kms.c | 143 ++++++++
drivers/gpu/drm/imx/dc/dc-kms.h | 15 +
drivers/gpu/drm/imx/dc/dc-plane.c | 227 ++++++++++++
drivers/gpu/drm/imx/dc/dc-plane.h | 37 ++
11 files changed, 1337 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/imx/dc/dc-crtc.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-crtc.h
create mode 100644 drivers/gpu/drm/imx/dc/dc-kms.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-kms.h
create mode 100644 drivers/gpu/drm/imx/dc/dc-plane.c
create mode 100644 drivers/gpu/drm/imx/dc/dc-plane.h
diff --git a/drivers/gpu/drm/imx/dc/Kconfig b/drivers/gpu/drm/imx/dc/Kconfig
index b66b815fbdf1..dac0de009273 100644
--- a/drivers/gpu/drm/imx/dc/Kconfig
+++ b/drivers/gpu/drm/imx/dc/Kconfig
@@ -1,6 +1,8 @@
config DRM_IMX8_DC
tristate "Freescale i.MX8 Display Controller Graphics"
depends on DRM && COMMON_CLK && OF && (ARCH_MXC || COMPILE_TEST)
+ select DRM_GEM_DMA_HELPER
+ select DRM_KMS_HELPER
select GENERIC_IRQ_CHIP
help
enable Freescale i.MX8 Display Controller(DC) graphics support
diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makefile
index 1ce3e8a8db22..b9d33c074984 100644
--- a/drivers/gpu/drm/imx/dc/Makefile
+++ b/drivers/gpu/drm/imx/dc/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
-imx8-dc-drm-objs := dc-cf.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o dc-fu.o \
- dc-fw.o dc-ic.o dc-lb.o dc-pe.o dc-tc.o
+imx8-dc-drm-objs := dc-cf.o dc-crtc.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o \
+ dc-fu.o dc-fw.o dc-ic.o dc-kms.o dc-lb.o dc-pe.o \
+ dc-plane.o dc-tc.o
obj-$(CONFIG_DRM_IMX8_DC) += imx8-dc-drm.o
diff --git a/drivers/gpu/drm/imx/dc/dc-crtc.c b/drivers/gpu/drm/imx/dc/dc-crtc.c
new file mode 100644
index 000000000000..e151e14a6677
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-crtc.c
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/pm_runtime.h>
+#include <linux/spinlock.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_modeset_helper_vtables.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_vblank.h>
+
+#include "dc-crtc.h"
+#include "dc-de.h"
+#include "dc-drv.h"
+#include "dc-pe.h"
+#include "dc-plane.h"
+
+#define DC_CRTC_WAIT_FOR_COMPLETION_TIMEOUT(c) \
+do { \
+ unsigned long ret; \
+ ret = wait_for_completion_timeout(&dc_crtc->c, HZ); \
+ if (ret == 0) \
+ dc_crtc_err(crtc, "%s: wait for " #c " timeout\n", \
+ __func__); \
+} while (0)
+
+#define DC_CRTC_CHECK_FRAMEGEN_FIFO(fg) \
+do { \
+ typeof(fg) _fg = (fg); \
+ if (dc_fg_secondary_requests_to_read_empty_fifo(_fg)) { \
+ dc_fg_secondary_clear_channel_status(_fg); \
+ dc_crtc_err(crtc, "%s: FrameGen FIFO empty\n", \
+ __func__); \
+ } \
+} while (0)
+
+#define DC_CRTC_WAIT_FOR_FRAMEGEN_SECONDARY_SYNCUP(fg) \
+do { \
+ if (dc_fg_wait_for_secondary_syncup(fg)) \
+ dc_crtc_err(crtc, \
+ "%s: FrameGen secondary channel isn't syncup\n",\
+ __func__); \
+} while (0)
+
+static u32 dc_crtc_get_vblank_counter(struct drm_crtc *crtc)
+{
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+
+ return dc_fg_get_frame_index(dc_crtc->fg);
+}
+
+static int dc_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+
+ enable_irq(dc_crtc->irq_dec_framecomplete);
+
+ return 0;
+}
+
+static void dc_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+
+ disable_irq_nosync(dc_crtc->irq_dec_framecomplete);
+}
+
+static irqreturn_t
+dc_crtc_dec_framecomplete_irq_handler(int irq, void *dev_id)
+{
+ struct dc_crtc *dc_crtc = dev_id;
+ struct drm_crtc *crtc = &dc_crtc->base;
+ unsigned long flags;
+
+ drm_crtc_handle_vblank(crtc);
+
+ spin_lock_irqsave(&crtc->dev->event_lock, flags);
+ if (dc_crtc->event) {
+ drm_crtc_send_vblank_event(crtc, dc_crtc->event);
+ dc_crtc->event = NULL;
+ drm_crtc_vblank_put(crtc);
+ }
+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t dc_crtc_common_irq_handler(int irq, void *dev_id)
+{
+ struct dc_crtc *dc_crtc = dev_id;
+ struct drm_crtc *crtc = &dc_crtc->base;
+
+ if (irq == dc_crtc->irq_dec_seqcomplete) {
+ complete(&dc_crtc->dec_seqcomplete_done);
+ } else if (irq == dc_crtc->irq_dec_shdld) {
+ complete(&dc_crtc->dec_shdld_done);
+ } else if (irq == dc_crtc->irq_ed_cont_shdld) {
+ complete(&dc_crtc->ed_cont_shdld_done);
+ } else if (irq == dc_crtc->irq_ed_safe_shdld) {
+ complete(&dc_crtc->ed_safe_shdld_done);
+ } else {
+ dc_crtc_err(crtc, "invalid CRTC irq(%u)\n", irq);
+ return IRQ_NONE;
+ }
+
+ return IRQ_HANDLED;
+}
+
+static const struct drm_crtc_funcs dc_crtc_funcs = {
+ .reset = drm_atomic_helper_crtc_reset,
+ .destroy = drm_crtc_cleanup,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+ .get_vblank_counter = dc_crtc_get_vblank_counter,
+ .enable_vblank = dc_crtc_enable_vblank,
+ .disable_vblank = dc_crtc_disable_vblank,
+ .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+};
+
+static void dc_crtc_queue_state_event(struct drm_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->crtc;
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (crtc_state->event) {
+ WARN_ON(drm_crtc_vblank_get(crtc));
+ WARN_ON(dc_crtc->event);
+ dc_crtc->event = crtc_state->event;
+ crtc_state->event = NULL;
+ }
+ spin_unlock_irq(&crtc->dev->event_lock);
+}
+
+static enum drm_mode_status
+dc_crtc_check_clock(struct dc_crtc *dc_crtc, int clk_khz)
+{
+ return dc_fg_check_clock(dc_crtc->fg, clk_khz);
+}
+
+static enum drm_mode_status
+dc_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
+{
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ enum drm_mode_status status;
+
+ status = dc_crtc_check_clock(dc_crtc, mode->clock);
+ if (status != MODE_OK)
+ return status;
+
+ if (mode->crtc_clock > DC_FRAMEGEN_MAX_CLOCK_KHZ)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static int
+dc_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *new_crtc_state =
+ drm_atomic_get_new_crtc_state(state, crtc);
+ struct drm_display_mode *adj = &new_crtc_state->adjusted_mode;
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ enum drm_mode_status status;
+
+ status = dc_crtc_check_clock(dc_crtc, adj->clock);
+ if (status != MODE_OK)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void
+dc_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *new_crtc_state =
+ drm_atomic_get_new_crtc_state(state, crtc);
+ struct dc_drm_device *dc_drm = to_dc_drm_device(crtc->dev);
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ int idx, ret;
+
+ if (!drm_atomic_crtc_needs_modeset(new_crtc_state) ||
+ !new_crtc_state->active)
+ return;
+
+ if (!drm_dev_enter(crtc->dev, &idx))
+ return;
+
+ /* request pixel engine power-on when CRTC starts to be active */
+ ret = pm_runtime_resume_and_get(dc_crtc->pe->dev);
+ if (ret)
+ dc_crtc_err(crtc, "failed to get DC pixel engine RPM: %d\n",
+ ret);
+
+ atomic_inc(&dc_drm->pe_rpm_count);
+
+ drm_dev_exit(idx);
+}
+
+static void
+dc_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *old_crtc_state =
+ drm_atomic_get_old_crtc_state(state, crtc);
+ struct drm_crtc_state *new_crtc_state =
+ drm_atomic_get_new_crtc_state(state, crtc);
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ int idx;
+
+ if (drm_atomic_crtc_needs_modeset(new_crtc_state) ||
+ (!old_crtc_state->active && !new_crtc_state->active))
+ return;
+
+ if (!drm_dev_enter(crtc->dev, &idx))
+ goto out;
+
+ enable_irq(dc_crtc->irq_ed_cont_shdld);
+
+ /* flush plane update out to display */
+ dc_ed_pec_sync_trigger(dc_crtc->ed_cont);
+
+ DC_CRTC_WAIT_FOR_COMPLETION_TIMEOUT(ed_cont_shdld_done);
+
+ disable_irq(dc_crtc->irq_ed_cont_shdld);
+
+ DC_CRTC_CHECK_FRAMEGEN_FIFO(dc_crtc->fg);
+
+ drm_dev_exit(idx);
+
+out:
+ dc_crtc_queue_state_event(new_crtc_state);
+}
+
+static void
+dc_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *new_crtc_state =
+ drm_atomic_get_new_crtc_state(state, crtc);
+ struct drm_display_mode *adj = &new_crtc_state->adjusted_mode;
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ enum dc_link_id cf_link;
+ int idx, ret;
+
+ dc_crtc_dbg(crtc, "mode " DRM_MODE_FMT "\n", DRM_MODE_ARG(adj));
+
+ drm_crtc_vblank_on(crtc);
+
+ if (!drm_dev_enter(crtc->dev, &idx))
+ goto out;
+
+ /* request display engine power-on when CRTC is enabled */
+ ret = pm_runtime_resume_and_get(dc_crtc->de->dev);
+ if (ret < 0)
+ dc_crtc_err(crtc, "failed to get DC display engine RPM: %d\n",
+ ret);
+
+ enable_irq(dc_crtc->irq_dec_shdld);
+ enable_irq(dc_crtc->irq_ed_cont_shdld);
+ enable_irq(dc_crtc->irq_ed_safe_shdld);
+
+ dc_fg_displaymode(dc_crtc->fg, FG_DM_SEC_ON_TOP);
+ dc_fg_panic_displaymode(dc_crtc->fg, FG_DM_CONSTCOL);
+ dc_fg_cfg_videomode(dc_crtc->fg, adj);
+
+ dc_cf_framedimensions(dc_crtc->cf_cont,
+ adj->crtc_hdisplay, adj->crtc_vdisplay);
+ dc_cf_framedimensions(dc_crtc->cf_safe,
+ adj->crtc_hdisplay, adj->crtc_vdisplay);
+
+ /* constframe in safety stream shows blue frame */
+ dc_cf_constantcolor_blue(dc_crtc->cf_safe);
+ cf_link = dc_cf_get_link_id(dc_crtc->cf_safe);
+ dc_ed_pec_src_sel(dc_crtc->ed_safe, cf_link);
+
+ /* show CRTC background if no plane is enabled */
+ if (new_crtc_state->plane_mask == 0) {
+ /* constframe in content stream shows black frame */
+ dc_cf_constantcolor_black(dc_crtc->cf_cont);
+
+ cf_link = dc_cf_get_link_id(dc_crtc->cf_cont);
+ dc_ed_pec_src_sel(dc_crtc->ed_cont, cf_link);
+ }
+
+ dc_fg_enable_clock(dc_crtc->fg);
+ dc_ed_pec_sync_trigger(dc_crtc->ed_cont);
+ dc_ed_pec_sync_trigger(dc_crtc->ed_safe);
+ dc_fg_shdtokgen(dc_crtc->fg);
+ dc_fg_enable(dc_crtc->fg);
+
+ DC_CRTC_WAIT_FOR_COMPLETION_TIMEOUT(ed_safe_shdld_done);
+ DC_CRTC_WAIT_FOR_COMPLETION_TIMEOUT(ed_cont_shdld_done);
+ DC_CRTC_WAIT_FOR_COMPLETION_TIMEOUT(dec_shdld_done);
+
+ disable_irq(dc_crtc->irq_ed_safe_shdld);
+ disable_irq(dc_crtc->irq_ed_cont_shdld);
+ disable_irq(dc_crtc->irq_dec_shdld);
+
+ DC_CRTC_WAIT_FOR_FRAMEGEN_SECONDARY_SYNCUP(dc_crtc->fg);
+
+ DC_CRTC_CHECK_FRAMEGEN_FIFO(dc_crtc->fg);
+
+ drm_dev_exit(idx);
+
+out:
+ dc_crtc_queue_state_event(new_crtc_state);
+}
+
+static void
+dc_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *new_crtc_state =
+ drm_atomic_get_new_crtc_state(state, crtc);
+ struct dc_drm_device *dc_drm = to_dc_drm_device(crtc->dev);
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ int idx, ret;
+
+ if (!drm_dev_enter(crtc->dev, &idx))
+ goto out;
+
+ enable_irq(dc_crtc->irq_dec_seqcomplete);
+ dc_fg_disable(dc_crtc->fg);
+ DC_CRTC_WAIT_FOR_COMPLETION_TIMEOUT(dec_seqcomplete_done);
+ disable_irq(dc_crtc->irq_dec_seqcomplete);
+
+ dc_fg_disable_clock(dc_crtc->fg);
+
+ /* request pixel engine power-off as plane is off too */
+ ret = pm_runtime_put(dc_crtc->pe->dev);
+ if (ret)
+ dc_crtc_err(crtc, "failed to put DC pixel engine RPM: %d\n",
+ ret);
+
+ atomic_dec(&dc_drm->pe_rpm_count);
+
+ /* request display engine power-off when CRTC is disabled */
+ ret = pm_runtime_put(dc_crtc->de->dev);
+ if (ret < 0)
+ dc_crtc_err(crtc, "failed to put DC display engine RPM: %d\n",
+ ret);
+
+ drm_dev_exit(idx);
+
+out:
+ drm_crtc_vblank_off(crtc);
+
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (new_crtc_state->event && !new_crtc_state->active) {
+ drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
+ new_crtc_state->event = NULL;
+ }
+ spin_unlock_irq(&crtc->dev->event_lock);
+}
+
+void dc_crtc_disable_at_unbind(struct drm_crtc *crtc)
+{
+ struct dc_drm_device *dc_drm = to_dc_drm_device(crtc->dev);
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ int ret;
+
+ if (atomic_dec_if_positive(&dc_drm->pe_rpm_count) >= 0) {
+ ret = pm_runtime_put_sync(dc_crtc->pe->dev);
+ if (ret)
+ dc_crtc_err(crtc, "failed to put DC pixel engine RPM: %d\n",
+ ret);
+ }
+
+ if (!dc_fg_wait_for_frame_index_moving(dc_crtc->fg))
+ return;
+
+ dc_fg_disable_clock(dc_crtc->fg);
+
+ ret = pm_runtime_put_sync(dc_crtc->de->dev);
+ if (ret < 0)
+ dc_crtc_err(crtc, "failed to put DC display engine RPM: %d\n",
+ ret);
+}
+
+static bool dc_crtc_get_scanout_position(struct drm_crtc *crtc,
+ bool in_vblank_irq,
+ int *vpos, int *hpos,
+ ktime_t *stime, ktime_t *etime,
+ const struct drm_display_mode *mode)
+{
+ struct dc_crtc *dc_crtc = to_dc_crtc(crtc);
+ int vdisplay = mode->crtc_vdisplay;
+ int vtotal = mode->crtc_vtotal;
+ bool reliable;
+ int line;
+ int idx;
+
+ if (stime)
+ *stime = ktime_get();
+
+ if (!drm_dev_enter(crtc->dev, &idx)) {
+ reliable = false;
+ *vpos = 0;
+ *hpos = 0;
+ goto out;
+ }
+
+ /* line index starts with 0 for the first active output line */
+ line = dc_fg_get_line_index(dc_crtc->fg);
+
+ if (line < vdisplay)
+ /* active scanout area - positive */
+ *vpos = line + 1;
+ else
+ /* inside vblank - negative */
+ *vpos = line - (vtotal - 1);
+
+ *hpos = 0;
+
+ reliable = true;
+
+ drm_dev_exit(idx);
+out:
+ if (etime)
+ *etime = ktime_get();
+
+ return reliable;
+}
+
+static const struct drm_crtc_helper_funcs dc_helper_funcs = {
+ .mode_valid = dc_crtc_mode_valid,
+ .atomic_check = dc_crtc_atomic_check,
+ .atomic_begin = dc_crtc_atomic_begin,
+ .atomic_flush = dc_crtc_atomic_flush,
+ .atomic_enable = dc_crtc_atomic_enable,
+ .atomic_disable = dc_crtc_atomic_disable,
+ .get_scanout_position = dc_crtc_get_scanout_position,
+};
+
+static void dc_crtc_free_irq(struct drm_device *drm, void *ptr)
+{
+ struct dc_crtc_irq *irq = ptr;
+
+ free_irq(irq->irq, irq->dc_crtc);
+}
+
+static int
+dc_crtc_request_irq(struct dc_crtc *dc_crtc, struct device *dev,
+ unsigned int irq,
+ irqreturn_t (*irq_handler)(int irq, void *dev_id))
+{
+ int ret;
+
+ ret = request_irq(irq, irq_handler, IRQF_NO_AUTOEN, dev_name(dev),
+ dc_crtc);
+ if (ret < 0)
+ dev_err(dev, "failed to request irq(%u): %d\n", irq, ret);
+
+ return ret;
+}
+
+static int dc_crtc_request_irqs(struct drm_device *drm, struct dc_crtc *dc_crtc)
+{
+ struct {
+ struct device *dev;
+ unsigned int irq;
+ irqreturn_t (*irq_handler)(int irq, void *dev_id);
+ } irqs[] = {
+ {
+ dc_crtc->de->dev,
+ dc_crtc->irq_dec_framecomplete,
+ dc_crtc_dec_framecomplete_irq_handler,
+ }, {
+ dc_crtc->de->dev,
+ dc_crtc->irq_dec_seqcomplete,
+ dc_crtc_common_irq_handler,
+ }, {
+ dc_crtc->de->dev,
+ dc_crtc->irq_dec_shdld,
+ dc_crtc_common_irq_handler,
+ }, {
+ dc_crtc->ed_cont->dev,
+ dc_crtc->irq_ed_cont_shdld,
+ dc_crtc_common_irq_handler,
+ }, {
+ dc_crtc->ed_safe->dev,
+ dc_crtc->irq_ed_safe_shdld,
+ dc_crtc_common_irq_handler,
+ },
+ };
+ struct drm_crtc *crtc = &dc_crtc->base;
+ int i, ret;
+
+ dc_crtc->irqs = drmm_kcalloc(drm, ARRAY_SIZE(irqs),
+ sizeof(*dc_crtc->irqs), GFP_KERNEL);
+ if (!dc_crtc->irqs) {
+ dev_err(drm->dev, "failed to allocate CRTC%u irqs\n",
+ crtc->index);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(irqs); i++) {
+ struct dc_crtc_irq *irq = &dc_crtc->irqs[i];
+
+ ret = dc_crtc_request_irq(dc_crtc, irqs[i].dev, irqs[i].irq,
+ irqs[i].irq_handler);
+ if (ret)
+ return ret;
+
+ irq->dc_crtc = dc_crtc;
+ irq->irq = irqs[i].irq;
+
+ ret = drmm_add_action_or_reset(drm, dc_crtc_free_irq, irq);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int dc_crtc_init(struct dc_drm_device *dc_drm, int crtc_index)
+{
+ struct dc_crtc *dc_crtc = &dc_drm->dc_crtc[crtc_index];
+ struct drm_device *drm = &dc_drm->base;
+ struct dc_de *de = dc_drm->de[crtc_index];
+ struct dc_pe *pe = dc_drm->pe;
+ struct dc_plane *dc_primary;
+ int ret;
+
+ dc_crtc->de = de;
+ dc_crtc->pe = pe;
+
+ init_completion(&dc_crtc->dec_seqcomplete_done);
+ init_completion(&dc_crtc->dec_shdld_done);
+ init_completion(&dc_crtc->ed_cont_shdld_done);
+ init_completion(&dc_crtc->ed_safe_shdld_done);
+
+ dc_crtc->cf_cont = pe->cf_cont[crtc_index];
+ dc_crtc->cf_safe = pe->cf_safe[crtc_index];
+ dc_crtc->ed_cont = pe->ed_cont[crtc_index];
+ dc_crtc->ed_safe = pe->ed_safe[crtc_index];
+ dc_crtc->fg = de->fg;
+
+ dc_crtc->irq_dec_framecomplete = de->irq_framecomplete;
+ dc_crtc->irq_dec_seqcomplete = de->irq_seqcomplete;
+ dc_crtc->irq_dec_shdld = de->irq_shdld;
+ dc_crtc->irq_ed_safe_shdld = dc_crtc->ed_safe->irq_shdld;
+ dc_crtc->irq_ed_cont_shdld = dc_crtc->ed_cont->irq_shdld;
+
+ dc_primary = &dc_drm->dc_primary[crtc_index];
+ ret = dc_plane_init(dc_drm, dc_primary);
+ if (ret) {
+ dev_err(drm->dev,
+ "failed to init primary plane for display engine%u: %d\n",
+ de->id, ret);
+ return ret;
+ }
+
+ drm_crtc_helper_add(&dc_crtc->base, &dc_helper_funcs);
+
+ ret = drm_crtc_init_with_planes(drm, &dc_crtc->base, &dc_primary->base,
+ NULL, &dc_crtc_funcs, NULL);
+ if (ret) {
+ dev_err(drm->dev,
+ "failed to add CRTC for display engine%u: %d\n",
+ de->id, ret);
+ return ret;
+ }
+
+ return dc_crtc_request_irqs(drm, dc_crtc);
+}
diff --git a/drivers/gpu/drm/imx/dc/dc-crtc.h b/drivers/gpu/drm/imx/dc/dc-crtc.h
new file mode 100644
index 000000000000..9f28d0d4d712
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-crtc.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DC_CRTC_H__
+#define __DC_CRTC_H__
+
+#include <linux/completion.h>
+#include <linux/container_of.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_print.h>
+#include <drm/drm_vblank.h>
+
+#include "dc-de.h"
+#include "dc-pe.h"
+
+#define dc_crtc_dbg(crtc, fmt, ...) \
+do { \
+ typeof(crtc) _crtc = (crtc); \
+ drm_dbg_kms(_crtc->dev, "[CRTC:%d:%s] " fmt, \
+ _crtc->base.id, _crtc->name, ##__VA_ARGS__); \
+} while (0)
+
+#define dc_crtc_err(crtc, fmt, ...) \
+do { \
+ typeof(crtc) _crtc = (crtc); \
+ drm_err(_crtc->dev, "[CRTC:%d:%s] " fmt, \
+ _crtc->base.id, _crtc->name, ##__VA_ARGS__); \
+} while (0)
+
+struct dc_crtc {
+ struct drm_crtc base;
+ struct dc_de *de;
+ struct dc_pe *pe;
+ struct dc_cf *cf_cont;
+ struct dc_cf *cf_safe;
+ struct dc_ed *ed_cont;
+ struct dc_ed *ed_safe;
+ struct dc_fg *fg;
+ unsigned int irq_dec_framecomplete;
+ unsigned int irq_dec_seqcomplete;
+ unsigned int irq_dec_shdld;
+ unsigned int irq_ed_cont_shdld;
+ unsigned int irq_ed_safe_shdld;
+ struct completion dec_seqcomplete_done;
+ struct completion dec_shdld_done;
+ struct completion ed_safe_shdld_done;
+ struct completion ed_cont_shdld_done;
+ struct drm_pending_vblank_event *event;
+ struct dc_crtc_irq *irqs;
+};
+
+struct dc_crtc_irq {
+ struct dc_crtc *dc_crtc;
+ unsigned int irq;
+};
+
+static inline struct dc_crtc *to_dc_crtc(struct drm_crtc *crtc)
+{
+ return container_of(crtc, struct dc_crtc, base);
+}
+
+void dc_crtc_disable_at_unbind(struct drm_crtc *crtc);
+
+#endif /* __DC_CRTC_H__ */
diff --git a/drivers/gpu/drm/imx/dc/dc-de.h b/drivers/gpu/drm/imx/dc/dc-de.h
index 5fe340c88f91..a4d9afe6fe8f 100644
--- a/drivers/gpu/drm/imx/dc/dc-de.h
+++ b/drivers/gpu/drm/imx/dc/dc-de.h
@@ -11,6 +11,9 @@
#define DC_DISPLAYS 2
+#define DC_FRAMEGEN_MAX_FRAME_INDEX 0x3ffff
+#define DC_FRAMEGEN_MAX_CLOCK_KHZ 300000
+
enum dc_fg_syncmode {
FG_SYNCMODE_OFF, /* No side-by-side synchronization. */
};
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.c b/drivers/gpu/drm/imx/dc/dc-drv.c
index fd68861f770a..6869816e48bc 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.c
+++ b/drivers/gpu/drm/imx/dc/dc-drv.c
@@ -3,11 +3,251 @@
* Copyright 2024 NXP
*/
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fbdev_dma.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_modeset_helper.h>
+#include <drm/drm_module.h>
+#include <drm/drm_of.h>
+
+#include "dc-crtc.h"
+#include "dc-de.h"
#include "dc-drv.h"
+struct dc_priv {
+ struct drm_device *drm;
+ struct clk *clk_cfg;
+};
+
+DEFINE_DRM_GEM_DMA_FOPS(dc_drm_driver_fops);
+
+static struct drm_driver dc_drm_driver = {
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
+ DRM_GEM_DMA_DRIVER_OPS,
+ .fops = &dc_drm_driver_fops,
+ .name = "imx8-dc",
+ .desc = "i.MX8 DC DRM graphics",
+ .date = "20240530",
+ .major = 1,
+ .minor = 0,
+ .patchlevel = 0,
+};
+
+static void
+dc_add_components(struct device *dev, struct component_match **matchptr)
+{
+ struct device_node *child, *grandchild;
+
+ for_each_available_child_of_node(dev->of_node, child) {
+ drm_of_component_match_add(dev, matchptr, component_compare_of,
+ child);
+
+ for_each_available_child_of_node(child, grandchild) {
+ if (of_node_name_eq(grandchild, "port"))
+ continue;
+
+ drm_of_component_match_add(dev, matchptr,
+ component_compare_of,
+ grandchild);
+ }
+ }
+}
+
+static void dc_drm_component_unbind_all(struct drm_device *drm, void *ptr)
+{
+ struct dc_drm_device *dc_drm = ptr;
+
+ component_unbind_all(drm->dev, dc_drm);
+}
+
+static int dc_drm_bind(struct device *dev)
+{
+ struct dc_priv *priv = dev_get_drvdata(dev);
+ struct dc_drm_device *dc_drm;
+ struct drm_device *drm;
+ int ret;
+
+ dc_drm = devm_drm_dev_alloc(dev, &dc_drm_driver, struct dc_drm_device,
+ base);
+ if (IS_ERR(dc_drm))
+ return PTR_ERR(dc_drm);
+
+ drm = &dc_drm->base;
+
+ ret = component_bind_all(dev, dc_drm);
+ if (ret)
+ return ret;
+
+ ret = drmm_add_action_or_reset(drm, dc_drm_component_unbind_all,
+ dc_drm);
+ if (ret)
+ return ret;
+
+ ret = dc_kms_init(dc_drm);
+ if (ret)
+ return ret;
+
+ ret = drm_dev_register(drm, 0);
+ if (ret) {
+ dev_err(dev, "failed to register drm device: %d\n", ret);
+ goto err;
+ }
+
+ drm_fbdev_dma_setup(drm, 32);
+
+ priv->drm = drm;
+
+ return 0;
+
+err:
+ dc_kms_uninit(dc_drm);
+
+ return ret;
+}
+
+static void dc_drm_unbind(struct device *dev)
+{
+ struct dc_priv *priv = dev_get_drvdata(dev);
+ struct dc_drm_device *dc_drm = to_dc_drm_device(priv->drm);
+ struct drm_device *drm = &dc_drm->base;
+ struct drm_crtc *crtc;
+
+ priv->drm = NULL;
+ drm_dev_unplug(drm);
+ dc_kms_uninit(dc_drm);
+ drm_atomic_helper_shutdown(drm);
+
+ drm_for_each_crtc(crtc, drm)
+ dc_crtc_disable_at_unbind(crtc);
+}
+
+static const struct component_master_ops dc_drm_ops = {
+ .bind = dc_drm_bind,
+ .unbind = dc_drm_unbind,
+};
+
+static int dc_probe(struct platform_device *pdev)
+{
+ struct component_match *match = NULL;
+ struct dc_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk_cfg = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(priv->clk_cfg))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cfg),
+ "failed to get cfg clock\n");
+
+ dev_set_drvdata(&pdev->dev, priv);
+
+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret)
+ return ret;
+
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret)
+ return ret;
+
+ ret = devm_of_platform_populate(&pdev->dev);
+ if (ret)
+ return ret;
+
+ dc_add_components(&pdev->dev, &match);
+
+ ret = component_master_add_with_match(&pdev->dev, &dc_drm_ops, match);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to add component master\n");
+
+ return 0;
+}
+
+static void dc_remove(struct platform_device *pdev)
+{
+ component_master_del(&pdev->dev, &dc_drm_ops);
+}
+
+static int dc_runtime_suspend(struct device *dev)
+{
+ struct dc_priv *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->clk_cfg);
+
+ return 0;
+}
+
+static int dc_runtime_resume(struct device *dev)
+{
+ struct dc_priv *priv = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk_cfg);
+ if (ret)
+ dev_err(dev, "failed to enable cfg clock: %d\n", ret);
+
+ return ret;
+}
+
+static int dc_suspend(struct device *dev)
+{
+ struct dc_priv *priv = dev_get_drvdata(dev);
+
+ return drm_mode_config_helper_suspend(priv->drm);
+}
+
+static int dc_resume(struct device *dev)
+{
+ struct dc_priv *priv = dev_get_drvdata(dev);
+
+ return drm_mode_config_helper_resume(priv->drm);
+}
+
+static void dc_shutdown(struct platform_device *pdev)
+{
+ struct dc_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ drm_atomic_helper_shutdown(priv->drm);
+}
+
+static const struct dev_pm_ops dc_pm_ops = {
+ RUNTIME_PM_OPS(dc_runtime_suspend, dc_runtime_resume, NULL)
+ SYSTEM_SLEEP_PM_OPS(dc_suspend, dc_resume)
+};
+
+static const struct of_device_id dc_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-dc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dc_dt_ids);
+
+static struct platform_driver dc_driver = {
+ .probe = dc_probe,
+ .remove_new = dc_remove,
+ .shutdown = dc_shutdown,
+ .driver = {
+ .name = "imx8-dc",
+ .of_match_table = dc_dt_ids,
+ .pm = pm_sleep_ptr(&dc_pm_ops),
+ },
+};
+
static struct platform_driver * const dc_drivers[] = {
&dc_cf_driver,
&dc_de_driver,
@@ -19,6 +259,7 @@ static struct platform_driver * const dc_drivers[] = {
&dc_lb_driver,
&dc_pe_driver,
&dc_tc_driver,
+ &dc_driver,
};
static int __init dc_drm_init(void)
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.h b/drivers/gpu/drm/imx/dc/dc-drv.h
index 3b11f4862c6c..827318f1dbf3 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.h
+++ b/drivers/gpu/drm/imx/dc/dc-drv.h
@@ -6,19 +6,40 @@
#ifndef __DC_DRV_H__
#define __DC_DRV_H__
+#include <linux/container_of.h>
#include <linux/platform_device.h>
#include <drm/drm_device.h>
+#include <drm/drm_encoder.h>
+#include "dc-crtc.h"
#include "dc-de.h"
+#include "dc-kms.h"
#include "dc-pe.h"
+#include "dc-plane.h"
struct dc_drm_device {
struct drm_device base;
+ struct dc_crtc dc_crtc[DC_CRTCS];
+ struct dc_plane dc_primary[DC_PRIMARYS];
+ struct drm_encoder encoder[DC_ENCODERS];
struct dc_de *de[DC_DISPLAYS];
struct dc_pe *pe;
+ atomic_t pe_rpm_count;
};
+static inline struct dc_drm_device *to_dc_drm_device(struct drm_device *drm)
+{
+ return container_of(drm, struct dc_drm_device, base);
+}
+
+int dc_crtc_init(struct dc_drm_device *dc_drm, int crtc_index);
+
+int dc_kms_init(struct dc_drm_device *dc_drm);
+void dc_kms_uninit(struct dc_drm_device *dc_drm);
+
+int dc_plane_init(struct dc_drm_device *dc_drm, struct dc_plane *dc_plane);
+
extern struct platform_driver dc_cf_driver;
extern struct platform_driver dc_ed_driver;
extern struct platform_driver dc_de_driver;
diff --git a/drivers/gpu/drm/imx/dc/dc-kms.c b/drivers/gpu/drm/imx/dc/dc-kms.c
new file mode 100644
index 000000000000..f629696ca451
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-kms.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/of.h>
+#include <linux/of_graph.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_bridge_connector.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_mode_config.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "dc-crtc.h"
+#include "dc-de.h"
+#include "dc-drv.h"
+#include "dc-kms.h"
+
+static const struct drm_mode_config_funcs dc_drm_mode_config_funcs = {
+ .fb_create = drm_gem_fb_create,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
+};
+
+static int dc_kms_init_encoder_per_crtc(struct dc_drm_device *dc_drm,
+ int crtc_index)
+{
+ struct dc_crtc *dc_crtc = &dc_drm->dc_crtc[crtc_index];
+ struct drm_device *drm = &dc_drm->base;
+ struct drm_crtc *crtc = &dc_crtc->base;
+ struct drm_connector *connector;
+ struct device *dev = drm->dev;
+ struct drm_encoder *encoder;
+ struct device_node *remote;
+ struct drm_bridge *bridge;
+ int ret = 0;
+
+ remote = of_graph_get_remote_node(dc_crtc->de->dev->of_node, 0, -1);
+ if (!of_device_is_available(remote))
+ goto out;
+
+ bridge = of_drm_find_bridge(remote);
+ if (!bridge) {
+ ret = -EPROBE_DEFER;
+ dev_err_probe(dev, ret, "failed to find bridge for CRTC%u\n",
+ crtc->index);
+ goto out;
+ }
+
+ encoder = &dc_drm->encoder[crtc_index];
+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_NONE);
+ if (ret) {
+ dev_err(dev, "failed to initialize encoder for CRTC%u: %d\n",
+ crtc->index, ret);
+ goto out;
+ }
+
+ encoder->possible_crtcs = drm_crtc_mask(crtc);
+
+ ret = drm_bridge_attach(encoder, bridge, NULL,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ if (ret) {
+ dev_err(dev,
+ "failed to attach bridge to encoder for CRTC%u: %d\n",
+ crtc->index, ret);
+ goto out;
+ }
+
+ connector = drm_bridge_connector_init(drm, encoder);
+ if (IS_ERR(connector)) {
+ ret = PTR_ERR(connector);
+ dev_err(dev, "failed to init bridge connector for CRTC%u: %d\n",
+ crtc->index, ret);
+ goto out;
+ }
+
+ ret = drm_connector_attach_encoder(connector, encoder);
+ if (ret)
+ dev_err(dev,
+ "failed to attach encoder to connector for CRTC%u: %d\n",
+ crtc->index, ret);
+
+out:
+ of_node_put(remote);
+ return ret;
+}
+
+int dc_kms_init(struct dc_drm_device *dc_drm)
+{
+ struct drm_device *drm = &dc_drm->base;
+ int ret, i;
+
+ ret = drmm_mode_config_init(drm);
+ if (ret)
+ return ret;
+
+ atomic_set(&dc_drm->pe_rpm_count, 0);
+
+ drm->mode_config.min_width = 60;
+ drm->mode_config.min_height = 60;
+ drm->mode_config.max_width = 8192;
+ drm->mode_config.max_height = 8192;
+ drm->mode_config.funcs = &dc_drm_mode_config_funcs;
+
+ drm->vblank_disable_immediate = true;
+ drm->max_vblank_count = DC_FRAMEGEN_MAX_FRAME_INDEX;
+
+ for (i = 0; i < DC_CRTCS; i++) {
+ ret = dc_crtc_init(dc_drm, i);
+ if (ret)
+ return ret;
+
+ ret = dc_kms_init_encoder_per_crtc(dc_drm, i);
+ if (ret)
+ return ret;
+ }
+
+ ret = drm_vblank_init(drm, DC_CRTCS);
+ if (ret) {
+ dev_err(drm->dev, "failed to init vblank support: %d\n", ret);
+ return ret;
+ }
+
+ drm_mode_config_reset(drm);
+
+ drm_kms_helper_poll_init(drm);
+
+ return 0;
+}
+
+void dc_kms_uninit(struct dc_drm_device *dc_drm)
+{
+ drm_kms_helper_poll_fini(&dc_drm->base);
+}
diff --git a/drivers/gpu/drm/imx/dc/dc-kms.h b/drivers/gpu/drm/imx/dc/dc-kms.h
new file mode 100644
index 000000000000..4f66b11c106a
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-kms.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DC_KMS_H__
+#define __DC_KMS_H__
+
+#include "dc-de.h"
+
+#define DC_CRTCS DC_DISPLAYS
+#define DC_ENCODERS DC_DISPLAYS
+#define DC_PRIMARYS DC_DISPLAYS
+
+#endif /* __DC_KMS_H__ */
diff --git a/drivers/gpu/drm/imx/dc/dc-plane.c b/drivers/gpu/drm/imx/dc/dc-plane.c
new file mode 100644
index 000000000000..a49b043ca167
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-plane.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fb_dma_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include <drm/drm_plane_helper.h>
+
+#include "dc-drv.h"
+#include "dc-fu.h"
+#include "dc-plane.h"
+
+#define DC_PLANE_MAX_PITCH 0x10000
+#define DC_PLANE_MAX_PIX_CNT 8192
+
+static const uint32_t dc_plane_formats[] = {
+ DRM_FORMAT_XRGB8888,
+};
+
+static const struct drm_plane_funcs dc_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = drm_plane_cleanup,
+ .reset = drm_atomic_helper_plane_reset,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static int dc_plane_check_no_off_screen(struct drm_plane_state *state,
+ struct drm_crtc_state *crtc_state)
+{
+ if (state->dst.x1 < 0 || state->dst.y1 < 0 ||
+ state->dst.x2 > crtc_state->adjusted_mode.hdisplay ||
+ state->dst.y2 > crtc_state->adjusted_mode.vdisplay) {
+ dc_plane_dbg(state->plane, "no off screen\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int dc_plane_check_max_source_resolution(struct drm_plane_state *state)
+{
+ int src_h = drm_rect_height(&state->src) >> 16;
+ int src_w = drm_rect_width(&state->src) >> 16;
+
+ if (src_w > DC_PLANE_MAX_PIX_CNT || src_h > DC_PLANE_MAX_PIX_CNT) {
+ dc_plane_dbg(state->plane, "invalid source resolution\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int dc_plane_check_fb(struct drm_plane_state *state)
+{
+ struct drm_framebuffer *fb = state->fb;
+ dma_addr_t baseaddr = drm_fb_dma_get_gem_addr(fb, state, 0);
+
+ /* base address alignment */
+ if (baseaddr & 0x3) {
+ dc_plane_dbg(state->plane, "fb bad baddr alignment\n");
+ return -EINVAL;
+ }
+
+ /* pitches[0] range */
+ if (fb->pitches[0] > DC_PLANE_MAX_PITCH) {
+ dc_plane_dbg(state->plane, "fb pitches[0] is out of range\n");
+ return -EINVAL;
+ }
+
+ /* pitches[0] alignment */
+ if (fb->pitches[0] & 0x3) {
+ dc_plane_dbg(state->plane, "fb bad pitches[0] alignment\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+dc_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state)
+{
+ struct drm_plane_state *plane_state =
+ drm_atomic_get_new_plane_state(state, plane);
+ struct drm_crtc_state *crtc_state;
+ int ret;
+
+ /* ok to disable */
+ if (!plane_state->fb)
+ return 0;
+
+ if (!plane_state->crtc) {
+ dc_plane_dbg(plane, "no CRTC in plane state\n");
+ return -EINVAL;
+ }
+
+ crtc_state =
+ drm_atomic_get_existing_crtc_state(state, plane_state->crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ true, false);
+ if (ret) {
+ dc_plane_dbg(plane, "failed to check plane state: %d\n", ret);
+ return ret;
+ }
+
+ ret = dc_plane_check_no_off_screen(plane_state, crtc_state);
+ if (ret)
+ return ret;
+
+ ret = dc_plane_check_max_source_resolution(plane_state);
+ if (ret)
+ return ret;
+
+ return dc_plane_check_fb(plane_state);
+}
+
+static void
+dc_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state)
+{
+ struct drm_plane_state *new_state =
+ drm_atomic_get_new_plane_state(state, plane);
+ struct dc_plane *dplane = to_dc_plane(plane);
+ struct drm_framebuffer *fb = new_state->fb;
+ const struct dc_fu_ops *fu_ops;
+ struct dc_lb *lb = dplane->lb;
+ struct dc_fu *fu = dplane->fu;
+ dma_addr_t baseaddr;
+ int src_w, src_h;
+ int idx;
+
+ if (!drm_dev_enter(plane->dev, &idx))
+ return;
+
+ src_w = drm_rect_width(&new_state->src) >> 16;
+ src_h = drm_rect_height(&new_state->src) >> 16;
+
+ baseaddr = drm_fb_dma_get_gem_addr(fb, new_state, 0);
+
+ fu_ops = dc_fu_get_ops(dplane->fu);
+
+ fu_ops->set_layerblend(fu, lb);
+ fu_ops->set_burstlength(fu, baseaddr);
+ fu_ops->set_src_stride(fu, fb->pitches[0]);
+ fu_ops->set_src_buf_dimensions(fu, src_w, src_h);
+ fu_ops->set_fmt(fu, fb->format);
+ fu_ops->set_framedimensions(fu, src_w, src_h);
+ fu_ops->set_baseaddress(fu, baseaddr);
+ fu_ops->enable_src_buf(fu);
+
+ dc_plane_dbg(plane, "uses %s\n", fu_ops->get_name(fu));
+
+ dc_lb_pec_dynamic_prim_sel(lb, dc_cf_get_link_id(dplane->cf));
+ dc_lb_pec_dynamic_sec_sel(lb, fu_ops->get_link_id(fu));
+ dc_lb_mode(lb, LB_BLEND);
+ dc_lb_blendcontrol(lb);
+ dc_lb_position(lb, new_state->dst.x1, new_state->dst.y1);
+ dc_lb_pec_clken(lb, CLKEN_AUTOMATIC);
+
+ dc_plane_dbg(plane, "uses LayerBlend%u\n", dc_lb_get_id(lb));
+
+ /* set ExtDst's source to LayerBlend */
+ dc_ed_pec_src_sel(dplane->ed, dc_lb_get_link_id(lb));
+
+ drm_dev_exit(idx);
+}
+
+static void dc_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+ struct dc_plane *dplane = to_dc_plane(plane);
+ const struct dc_fu_ops *fu_ops;
+ int idx;
+
+ if (!drm_dev_enter(plane->dev, &idx))
+ return;
+
+ /* disable fetchunit in shadow */
+ fu_ops = dc_fu_get_ops(dplane->fu);
+ fu_ops->disable_src_buf(dplane->fu);
+
+ /* set ExtDst's source to ConstFrame */
+ dc_ed_pec_src_sel(dplane->ed, dc_cf_get_link_id(dplane->cf));
+
+ drm_dev_exit(idx);
+}
+
+static const struct drm_plane_helper_funcs dc_plane_helper_funcs = {
+ .atomic_check = dc_plane_atomic_check,
+ .atomic_update = dc_plane_atomic_update,
+ .atomic_disable = dc_plane_atomic_disable,
+};
+
+int dc_plane_init(struct dc_drm_device *dc_drm, struct dc_plane *dc_plane)
+{
+ struct drm_plane *plane = &dc_plane->base;
+ int ret;
+
+ ret = drm_universal_plane_init(&dc_drm->base, plane, 0, &dc_plane_funcs,
+ dc_plane_formats,
+ ARRAY_SIZE(dc_plane_formats),
+ NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
+ if (ret)
+ return ret;
+
+ drm_plane_helper_add(plane, &dc_plane_helper_funcs);
+
+ dc_plane->fu = dc_drm->pe->fu_disp[plane->index];
+ dc_plane->cf = dc_drm->pe->cf_cont[plane->index];
+ dc_plane->lb = dc_drm->pe->lb[plane->index];
+ dc_plane->ed = dc_drm->pe->ed_cont[plane->index];
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/imx/dc/dc-plane.h b/drivers/gpu/drm/imx/dc/dc-plane.h
new file mode 100644
index 000000000000..e72c3a7cb66f
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-plane.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DC_PLANE_H__
+#define __DC_PLANE_H__
+
+#include <linux/container_of.h>
+
+#include <drm/drm_plane.h>
+#include <drm/drm_print.h>
+
+#include "dc-fu.h"
+#include "dc-pe.h"
+
+#define dc_plane_dbg(plane, fmt, ...) \
+do { \
+ typeof(plane) _plane = (plane); \
+ drm_dbg_kms(_plane->dev, "[PLANE:%d:%s] " fmt, \
+ _plane->base.id, _plane->name, ##__VA_ARGS__); \
+} while (0)
+
+struct dc_plane {
+ struct drm_plane base;
+ struct dc_fu *fu;
+ struct dc_cf *cf;
+ struct dc_lb *lb;
+ struct dc_ed *ed;
+};
+
+static inline struct dc_plane *to_dc_plane(struct drm_plane *plane)
+{
+ return container_of(plane, struct dc_plane, base);
+}
+
+#endif /* __DC_PLANE_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH 09/10] drm/imx: Add i.MX8qxp Display Controller KMS
2024-07-05 9:09 ` [PATCH 09/10] drm/imx: Add i.MX8qxp Display Controller KMS Liu Ying
@ 2024-07-07 19:16 ` Markus Elfring
2024-07-08 6:21 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Markus Elfring @ 2024-07-07 19:16 UTC (permalink / raw)
To: Liu Ying, dri-devel, imx, linux-arm-kernel, kernel, devicetree
Cc: LKML, Conor Dooley, Daniel Vetter, David Airlie, Fabio Estevam,
Krzysztof Kozlowski, Maarten Lankhorst, Maxime Ripard,
Philipp Zabel, Rob Herring, Sascha Hauer, Shawn Guo,
Thomas Gleixner, Thomas Zimmermann
…
> registers of the display controller is accessed without command sequencer
…
Wording suggestion:
The registers of … are …
…
> +++ b/drivers/gpu/drm/imx/dc/dc-crtc.c
> @@ -0,0 +1,578 @@
…
> +static irqreturn_t
> +dc_crtc_dec_framecomplete_irq_handler(int irq, void *dev_id)
> +{
…
> + spin_lock_irqsave(&crtc->dev->event_lock, flags);
> + if (dc_crtc->event) {
…
> + }
> + spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
> +
> + return IRQ_HANDLED;
> +}
…
Under which circumstances would you become interested to apply a statement
like “guard(spinlock_irqsave)(&crtc->dev->event_lock);”?
https://elixir.bootlin.com/linux/v6.10-rc6/source/include/linux/spinlock.h#L574
Regards,
Markus
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH 09/10] drm/imx: Add i.MX8qxp Display Controller KMS
2024-07-07 19:16 ` Markus Elfring
@ 2024-07-08 6:21 ` Liu Ying
2024-07-08 7:09 ` [09/10] " Markus Elfring
0 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-08 6:21 UTC (permalink / raw)
To: Markus Elfring, dri-devel, imx, linux-arm-kernel, kernel,
devicetree
Cc: LKML, Conor Dooley, Daniel Vetter, David Airlie, Fabio Estevam,
Krzysztof Kozlowski, Maarten Lankhorst, Maxime Ripard,
Philipp Zabel, Rob Herring, Sascha Hauer, Shawn Guo,
Thomas Gleixner, Thomas Zimmermann
On 07/08/2024, Markus Elfring wrote:
> …
>> registers of the display controller is accessed without command sequencer
> …
>
> Wording suggestion:
> The registers of … are …
Will do.
>
>
> …
>> +++ b/drivers/gpu/drm/imx/dc/dc-crtc.c
>> @@ -0,0 +1,578 @@
> …
>> +static irqreturn_t
>> +dc_crtc_dec_framecomplete_irq_handler(int irq, void *dev_id)
>> +{
> …
>> + spin_lock_irqsave(&crtc->dev->event_lock, flags);
>> + if (dc_crtc->event) {
> …
>> + }
>> + spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
>> +
>> + return IRQ_HANDLED;
>> +}
> …
>
> Under which circumstances would you become interested to apply a statement
> like “guard(spinlock_irqsave)(&crtc->dev->event_lock);”?
I just follow the kerneldoc of drm_crtc_send_vblank_event() to
hold event lock like many other drivers do.
https://elixir.bootlin.com/linux/v6.10-rc6/source/drivers/gpu/drm/drm_vblank.c#L1120
> https://elixir.bootlin.com/linux/v6.10-rc6/source/include/linux/spinlock.h#L574
>
> Regards,
> Markus
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [09/10] drm/imx: Add i.MX8qxp Display Controller KMS
2024-07-08 6:21 ` Liu Ying
@ 2024-07-08 7:09 ` Markus Elfring
2024-07-08 7:33 ` Krzysztof Kozlowski
0 siblings, 1 reply; 39+ messages in thread
From: Markus Elfring @ 2024-07-08 7:09 UTC (permalink / raw)
To: Liu Ying, dri-devel, imx, linux-arm-kernel, kernel, devicetree
Cc: LKML, Conor Dooley, Daniel Vetter, David Airlie, Fabio Estevam,
Krzysztof Kozlowski, Maarten Lankhorst, Maxime Ripard,
Philipp Zabel, Rob Herring, Sascha Hauer, Shawn Guo,
Thomas Gleixner, Thomas Zimmermann
>> Under which circumstances would you become interested to apply a statement
>> like “guard(spinlock_irqsave)(&crtc->dev->event_lock);”?
>
> I just follow the kerneldoc of drm_crtc_send_vblank_event() to
> hold event lock like many other drivers do.
Please take another look at software design possibilities to benefit more
from further applications of scope-based resource management.
Regards,
Markus
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [09/10] drm/imx: Add i.MX8qxp Display Controller KMS
2024-07-08 7:09 ` [09/10] " Markus Elfring
@ 2024-07-08 7:33 ` Krzysztof Kozlowski
0 siblings, 0 replies; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-08 7:33 UTC (permalink / raw)
To: Liu Ying, dri-devel, imx, linux-arm-kernel, kernel, devicetree
Cc: LKML, Conor Dooley, Daniel Vetter, David Airlie, Fabio Estevam,
Krzysztof Kozlowski, Maarten Lankhorst, Maxime Ripard,
Philipp Zabel, Rob Herring, Sascha Hauer, Shawn Guo,
Thomas Gleixner, Thomas Zimmermann
On 08/07/2024 09:09, Markus Elfring wrote:
>>> Under which circumstances would you become interested to apply a statement
>>> like “guard(spinlock_irqsave)(&crtc->dev->event_lock);”?
>>
>> I just follow the kerneldoc of drm_crtc_send_vblank_event() to
>> hold event lock like many other drivers do.
>
> Please take another look at software design possibilities to benefit more
> from further applications of scope-based resource management.
<form letter>
Feel free to ignore all comments from Markus, regardless whether the
suggestion is reasonable or not. This person is banned from LKML and
several maintainers ignore Markus' feedback, because it is just a waste
of time.
</form letter>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 10/10] MAINTAINERS: Add maintainer for i.MX8qxp Display Controller
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (8 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 09/10] drm/imx: Add i.MX8qxp Display Controller KMS Liu Ying
@ 2024-07-05 9:09 ` Liu Ying
2024-07-05 19:02 ` Frank Li
2024-07-05 12:57 ` [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Francesco Dolcini
10 siblings, 1 reply; 39+ messages in thread
From: Liu Ying @ 2024-07-05 9:09 UTC (permalink / raw)
To: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel
Cc: p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
MAINTAINERS | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 35db18d26c11..29c9d52e74d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7379,6 +7379,25 @@ F: Documentation/devicetree/bindings/display/imx/
F: drivers/gpu/drm/imx/ipuv3/
F: drivers/gpu/ipu-v3/
+DRM DRIVERS FOR FREESCALE IMX8 DISPLAY CONTROLLER
+M: Liu Ying <victor.liu@nxp.com>
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-intc.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
+F: drivers/gpu/drm/imx/dc/
+
DRM DRIVERS FOR FREESCALE IMX BRIDGE
M: Liu Ying <victor.liu@nxp.com>
L: dri-devel@lists.freedesktop.org
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH 10/10] MAINTAINERS: Add maintainer for i.MX8qxp Display Controller
2024-07-05 9:09 ` [PATCH 10/10] MAINTAINERS: Add maintainer for i.MX8qxp Display Controller Liu Ying
@ 2024-07-05 19:02 ` Frank Li
2024-07-08 6:14 ` Liu Ying
0 siblings, 1 reply; 39+ messages in thread
From: Frank Li @ 2024-07-05 19:02 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel,
p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On Fri, Jul 05, 2024 at 05:09:32PM +0800, Liu Ying wrote:
> Add myself as the maintainer of i.MX8qxp Display Controller.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> MAINTAINERS | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 35db18d26c11..29c9d52e74d1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7379,6 +7379,25 @@ F: Documentation/devicetree/bindings/display/imx/
> F: drivers/gpu/drm/imx/ipuv3/
> F: drivers/gpu/ipu-v3/
>
> +DRM DRIVERS FOR FREESCALE IMX8 DISPLAY CONTROLLER
> +M: Liu Ying <victor.liu@nxp.com>
> +L: dri-devel@lists.freedesktop.org
> +S: Maintained
> +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-intc.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
How about
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc*.yaml
Frank
> +F: drivers/gpu/drm/imx/dc/
> +
> DRM DRIVERS FOR FREESCALE IMX BRIDGE
> M: Liu Ying <victor.liu@nxp.com>
> L: dri-devel@lists.freedesktop.org
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 10/10] MAINTAINERS: Add maintainer for i.MX8qxp Display Controller
2024-07-05 19:02 ` Frank Li
@ 2024-07-08 6:14 ` Liu Ying
0 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-08 6:14 UTC (permalink / raw)
To: Frank Li
Cc: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel,
p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/06/2024, Frank Li wrote:
> On Fri, Jul 05, 2024 at 05:09:32PM +0800, Liu Ying wrote:
>> Add myself as the maintainer of i.MX8qxp Display Controller.
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>> MAINTAINERS | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 35db18d26c11..29c9d52e74d1 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -7379,6 +7379,25 @@ F: Documentation/devicetree/bindings/display/imx/
>> F: drivers/gpu/drm/imx/ipuv3/
>> F: drivers/gpu/ipu-v3/
>>
>> +DRM DRIVERS FOR FREESCALE IMX8 DISPLAY CONTROLLER
>> +M: Liu Ying <victor.liu@nxp.com>
>> +L: dri-devel@lists.freedesktop.org
>> +S: Maintained
>> +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-intc.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
>> +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
>
> How about
> Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc*.yaml
Ok, will use this. Thanks.
>
> Frank
>
>> +F: drivers/gpu/drm/imx/dc/
>> +
>> DRM DRIVERS FOR FREESCALE IMX BRIDGE
>> M: Liu Ying <victor.liu@nxp.com>
>> L: dri-devel@lists.freedesktop.org
>> --
>> 2.34.1
>>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support
2024-07-05 9:09 [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Liu Ying
` (9 preceding siblings ...)
2024-07-05 9:09 ` [PATCH 10/10] MAINTAINERS: Add maintainer for i.MX8qxp Display Controller Liu Ying
@ 2024-07-05 12:57 ` Francesco Dolcini
2024-07-08 7:03 ` Liu Ying
10 siblings, 1 reply; 39+ messages in thread
From: Francesco Dolcini @ 2024-07-05 12:57 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel,
p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
Hello Liu,
On Fri, Jul 05, 2024 at 05:09:22PM +0800, Liu Ying wrote:
> This patch series aims to add Freescale i.MX8qxp Display Controller support.
I really appreciate your work here, I am looking forward for a better
support in mainline Linux for both i.MX8QXP and i.MX8QP.
With that said, would be possible to add to this patch series also the
required changes on the DTSI/DTS file to facilitate testing this?
Worst case you can just add those as RFC / DO NOT MERGE at the end of
this series when you'll send a v2.
Francesco
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support
2024-07-05 12:57 ` [PATCH 00/10] Add Freescale i.MX8qxp Display Controller support Francesco Dolcini
@ 2024-07-08 7:03 ` Liu Ying
0 siblings, 0 replies; 39+ messages in thread
From: Liu Ying @ 2024-07-08 7:03 UTC (permalink / raw)
To: Francesco Dolcini
Cc: dri-devel, devicetree, imx, linux-arm-kernel, linux-kernel,
p.zabel, airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
tglx
On 07/05/2024, Francesco Dolcini wrote:
> Hello Liu,
Hello Francesco,
>
> On Fri, Jul 05, 2024 at 05:09:22PM +0800, Liu Ying wrote:
>> This patch series aims to add Freescale i.MX8qxp Display Controller support.
>
> I really appreciate your work here, I am looking forward for a better
> support in mainline Linux for both i.MX8QXP and i.MX8QP.
>
> With that said, would be possible to add to this patch series also the
> required changes on the DTSI/DTS file to facilitate testing this?
> Worst case you can just add those as RFC / DO NOT MERGE at the end of
> this series when you'll send a v2.
Will try to do so.
>
> Francesco
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 39+ messages in thread