[PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[Thomas Bonnefille]

The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
minimal device tree files for this board to make it boot to a basic
shell.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
Changes in v4:
- Add correct bindings configuration for SG2002 sdhci
- Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
  has already been merged in Daniel Lezcano git tree.
- Link to v3: https://lore.kernel.org/r/20240709-sg2002-v3-0-af779c3d139d@bootlin.com

Changes in v3:
- Remove /dts-v1/ directive from sg2002.dtsi file
- Add disable-wp property to sdhci node to avoid having a write
  protected SD card
- Drop changes in cv18xx.dtsi and cv1800b.dtsi
- Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
- Link to v2: https://lore.kernel.org/r/20240612-sg2002-v2-0-19a585af6846@bootlin.com

Changes in v2:
- Add SDHCI support
- Change device tree name to match the Makefile
- Add oscillator frequency
- Add aliases to other UARTs
- Add aliases to GPIOs
- Move compatible for SDHCI from common DT to specific DT 
- Link to v1: https://lore.kernel.org/r/20240527-sg2002-v1-0-1b6cb38ce8f4@bootlin.com

---
Thomas Bonnefille (4):
      dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
      dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
      riscv: dts: sophgo: Add initial SG2002 SoC device tree
      riscv: dts: sophgo: Add LicheeRV Nano board device tree

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
 .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
 arch/riscv/boot/dts/sophgo/Makefile                |  1 +
 .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
 5 files changed, 93 insertions(+)
---
base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
change-id: 20240515-sg2002-93dce1d263be

Best regards,
-- 
Thomas Bonnefille <thomas.bonnefille@bootlin.com>

[PATCH v4 1/4] dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic

[Thomas Bonnefille]

Add compatible string for SOPHGO SG2002 Platform-Level Interruter
Controller.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 709b2211276b..7e1451f9786a 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -67,6 +67,7 @@ properties:
               - allwinner,sun20i-d1-plic
               - sophgo,cv1800b-plic
               - sophgo,cv1812h-plic
+              - sophgo,sg2002-plic
               - sophgo,sg2042-plic
               - thead,th1520-plic
           - const: thead,c900-plic

-- 
2.45.2

[PATCH v4 2/4] dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles

[Thomas Bonnefille]

Document the compatible strings for the Sipeed LicheeRV Nano B board which
uses the SOPHGO SG2002 SoC.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/sophgo.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
index 9bc813dad098..a14cb10ff3f0 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -26,6 +26,11 @@ properties:
           - enum:
               - sophgo,huashan-pi
           - const: sophgo,cv1812h
+      - items:
+          - enum:
+              - sipeed,licheerv-nano-b
+          - const: sipeed,licheerv-nano
+          - const: sophgo,sg2002
       - items:
           - enum:
               - milkv,pioneer

-- 
2.45.2

[PATCH v4 3/4] riscv: dts: sophgo: Add initial SG2002 SoC device tree

[Thomas Bonnefille]

Add initial device tree for the SG2002 RISC-V SoC by SOPHGO.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
The commit adding the bindings for the compatible "sophgo,sg2002-clint"
has been applied to Daniel Lezcano git tree. This commit may trigger the
bots because of this missing binding.
---
 arch/riscv/boot/dts/sophgo/sg2002.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
new file mode 100644
index 000000000000..22eb99d1abf7
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+	compatible = "sophgo,sg2002";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+};
+
+&plic {
+	compatible = "sophgo,sg2002-plic", "thead,c900-plic";
+};
+
+&clint {
+	compatible = "sophgo,sg2002-clint", "thead,c900-clint";
+};
+
+&clk {
+	compatible = "sophgo,sg2000-clk";
+};
+
+&sdhci0 {
+	compatible = "sophgo,sg2002-dwcmshc";
+};

-- 
2.45.2

[PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree

[Thomas Bonnefille]

LicheeRV Nano B [1] is an embedded development platform based on the SOPHGO
SG2002 chip, the B(ase) version is deprived of Wifi/Bluetooth and Ethernet.

Add only support for UART and SDHCI.

Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html [1]

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 arch/riscv/boot/dts/sophgo/Makefile                |  1 +
 .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
 2 files changed, 55 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 57ad82a61ea6..47d4243a8f35 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
 dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
 dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
diff --git a/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
new file mode 100644
index 000000000000..fc98b6a0ddf7
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ */
+
+/dts-v1/;
+
+#include "sg2002.dtsi"
+
+/ {
+	model = "LicheeRV Nano B";
+	compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&osc {
+	clock-frequency = <25000000>;
+};
+
+&sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	no-mmc;
+	no-sdio;
+	disable-wp;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};

-- 
2.45.2

Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[Inochi Amaoto]

On Thu, Jul 11, 2024 at 12:01:27PM GMT, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>

Reviewed-by: Inochi Amaoto <inochiama@outlook.com>

> ---
> Changes in v4:
> - Add correct bindings configuration for SG2002 sdhci
> - Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
>   has already been merged in Daniel Lezcano git tree.
> - Link to v3: https://lore.kernel.org/r/20240709-sg2002-v3-0-af779c3d139d@bootlin.com
> 
> Changes in v3:
> - Remove /dts-v1/ directive from sg2002.dtsi file
> - Add disable-wp property to sdhci node to avoid having a write
>   protected SD card
> - Drop changes in cv18xx.dtsi and cv1800b.dtsi
> - Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
> - Link to v2: https://lore.kernel.org/r/20240612-sg2002-v2-0-19a585af6846@bootlin.com
> 
> Changes in v2:
> - Add SDHCI support
> - Change device tree name to match the Makefile
> - Add oscillator frequency
> - Add aliases to other UARTs
> - Add aliases to GPIOs
> - Move compatible for SDHCI from common DT to specific DT 
> - Link to v1: https://lore.kernel.org/r/20240527-sg2002-v1-0-1b6cb38ce8f4@bootlin.com
> 
> ---
> Thomas Bonnefille (4):
>       dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
>       dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
>       riscv: dts: sophgo: Add initial SG2002 SoC device tree
>       riscv: dts: sophgo: Add LicheeRV Nano board device tree
> 
>  .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>  .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>  arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>  .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>  5 files changed, 93 insertions(+)
> ---
> base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
> change-id: 20240515-sg2002-93dce1d263be
> 
> Best regards,
> -- 
> Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> 

Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[Chen Wang]

On 2024/7/11 18:01, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
>
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
> Changes in v4:
> - Add correct bindings configuration for SG2002 sdhci
> - Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
>    has already been merged in Daniel Lezcano git tree.
> - Link to v3: https://lore.kernel.org/r/20240709-sg2002-v3-0-af779c3d139d@bootlin.com
>
> Changes in v3:
> - Remove /dts-v1/ directive from sg2002.dtsi file
> - Add disable-wp property to sdhci node to avoid having a write
>    protected SD card
> - Drop changes in cv18xx.dtsi and cv1800b.dtsi
> - Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
> - Link to v2: https://lore.kernel.org/r/20240612-sg2002-v2-0-19a585af6846@bootlin.com
>
> Changes in v2:
> - Add SDHCI support
> - Change device tree name to match the Makefile
> - Add oscillator frequency
> - Add aliases to other UARTs
> - Add aliases to GPIOs
> - Move compatible for SDHCI from common DT to specific DT
> - Link to v1: https://lore.kernel.org/r/20240527-sg2002-v1-0-1b6cb38ce8f4@bootlin.com
>
> ---
> Thomas Bonnefille (4):
>        dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
>        dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
>        riscv: dts: sophgo: Add initial SG2002 SoC device tree
>        riscv: dts: sophgo: Add LicheeRV Nano board device tree
>
>   .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>   .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>   .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>   arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>   5 files changed, 93 insertions(+)
> ---
> base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
> change-id: 20240515-sg2002-93dce1d263be
>
> Best regards,
Hi, Thomas,

This stuff is already too late for 6.11 as I already sent my PRs. I will 
handle this next period.

Cheers,

Chen

Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[Chen Wang]

hi, Conor,

How about letting me PR all the four patches in this patchset? Because 
they are all related to sophgo, it would be better to PR them together 
to avoid confusion.
Especially about the change of sifive,plic-1.0.0.yaml, my original 
understanding was that it should be handled by you.

Regards,

Chen

On 2024/7/11 18:01, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
>
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
> Changes in v4:
> - Add correct bindings configuration for SG2002 sdhci
> - Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
>    has already been merged in Daniel Lezcano git tree.
> - Link to v3: https://lore.kernel.org/r/20240709-sg2002-v3-0-af779c3d139d@bootlin.com
>
> Changes in v3:
> - Remove /dts-v1/ directive from sg2002.dtsi file
> - Add disable-wp property to sdhci node to avoid having a write
>    protected SD card
> - Drop changes in cv18xx.dtsi and cv1800b.dtsi
> - Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
> - Link to v2: https://lore.kernel.org/r/20240612-sg2002-v2-0-19a585af6846@bootlin.com
>
> Changes in v2:
> - Add SDHCI support
> - Change device tree name to match the Makefile
> - Add oscillator frequency
> - Add aliases to other UARTs
> - Add aliases to GPIOs
> - Move compatible for SDHCI from common DT to specific DT
> - Link to v1: https://lore.kernel.org/r/20240527-sg2002-v1-0-1b6cb38ce8f4@bootlin.com
>
> ---
> Thomas Bonnefille (4):
>        dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
>        dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
>        riscv: dts: sophgo: Add initial SG2002 SoC device tree
>        riscv: dts: sophgo: Add LicheeRV Nano board device tree
>
>   .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>   .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>   .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>   arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>   5 files changed, 93 insertions(+)
> ---
> base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
> change-id: 20240515-sg2002-93dce1d263be
>
> Best regards,

Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1207 bytes --]

On Fri, Jul 12, 2024 at 09:33:46AM +0800, Chen Wang wrote:
> >   .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
> >   .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
> >   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
> >   .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
> >   arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
> >   5 files changed, 93 insertions(+)
> 
> How about letting me PR all the four patches in this patchset? Because they
> are all related to sophgo, it would be better to PR them together to avoid
> confusion.
> Especially about the change of sifive,plic-1.0.0.yaml, my original
> understanding was that it should be handled by you.

No, stuff like the plic should really be handled by Thomas as he is the
interrupt controller maintainer, not by me. Usually though, neither the
timer or interrupt controller maintainers seem to care about these sorts
of binding patches which is why they ended up going with the dts.
Ideally the plic patch would go through the tip tree, but I think
there's unlikely to be sleep lost over a trivial binding change going
with the dts user.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[Chen Wang]

On 2024/7/12 22:15, Conor Dooley wrote:
> On Fri, Jul 12, 2024 at 09:33:46AM +0800, Chen Wang wrote:
>>>    .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>>>    .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>>>    arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>>>    .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>>>    arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>>>    5 files changed, 93 insertions(+)
>> How about letting me PR all the four patches in this patchset? Because they
>> are all related to sophgo, it would be better to PR them together to avoid
>> confusion.
>> Especially about the change of sifive,plic-1.0.0.yaml, my original
>> understanding was that it should be handled by you.
> No, stuff like the plic should really be handled by Thomas as he is the
> interrupt controller maintainer, not by me. Usually though, neither the
> timer or interrupt controller maintainers seem to care about these sorts
> of binding patches which is why they ended up going with the dts.
> Ideally the plic patch would go through the tip tree, but I think
> there's unlikely to be sleep lost over a trivial binding change going
> with the dts user.

Thank you Cornor for your input, I will handle these patches together 
with dts.

Regards,

Chen

Re: [PATCH v4 1/4] dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic

[Inochi Amaoto]

On Thu, Jul 11, 2024 at 12:01:28PM GMT, Thomas Bonnefille wrote:
> Add compatible string for SOPHGO SG2002 Platform-Level Interruter
> Controller.
> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 709b2211276b..7e1451f9786a 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -67,6 +67,7 @@ properties:
>                - allwinner,sun20i-d1-plic
>                - sophgo,cv1800b-plic
>                - sophgo,cv1812h-plic
> +              - sophgo,sg2002-plic
>                - sophgo,sg2042-plic
>                - thead,th1520-plic
>            - const: thead,c900-plic
> 
> -- 
> 2.45.2
> 

Hi Thomas,

Could you take this patch?
It will be good to take this series early so we can test new submitted
driver with this platform.

Regard,
Inochi.

Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano

[Inochi Amaoto]

On Thu, 11 Jul 2024 12:01:27 +0200, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
> 
> 

Applied to cv18xx/for-next, thanks!

[1/4] dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
      https://github.com/sophgo/linux/commit/866e86d73f0a1bc4e482162276c4e9765597362c
[2/4] dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
      https://github.com/sophgo/linux/commit/4ecff14f1a45f82c60ec77d2662e439d088fefd6
[3/4] riscv: dts: sophgo: Add initial SG2002 SoC device tree
      https://github.com/sophgo/linux/commit/05949703b659b138a9ade02e456ddfe112581457
[4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree
      https://github.com/sophgo/linux/commit/c919edd074714f53763cbfeb8bdc9f1accfa7f52

Thanks,
Inochi

Re: [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree

[Inochi Amaoto]

On Thu, Jul 11, 2024 at 12:01:31PM GMT, Thomas Bonnefille wrote:
> LicheeRV Nano B [1] is an embedded development platform based on the SOPHGO
> SG2002 chip, the B(ase) version is deprived of Wifi/Bluetooth and Ethernet.
> 
> Add only support for UART and SDHCI.
> 
> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html [1]
> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
>  arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>  .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>  2 files changed, 55 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 57ad82a61ea6..47d4243a8f35 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
>  dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
>  dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
> new file mode 100644
> index 000000000000..fc98b6a0ddf7
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "sg2002.dtsi"
> +
> +/ {
> +	model = "LicheeRV Nano B";
> +	compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002";
> +
> +	aliases {
> +		gpio0 = &gpio0;
> +		gpio1 = &gpio1;
> +		gpio2 = &gpio2;
> +		gpio3 = &gpio3;
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&osc {
> +	clock-frequency = <25000000>;
> +};
> +
> +&sdhci0 {
> +	status = "okay";
> +	bus-width = <4>;
> +	no-1-8-v;
> +	no-mmc;
> +	no-sdio;
> +	disable-wp;
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> 
> -- 
> 2.45.2
> 

Have you test you patch with a real board? Especially
for device "uart1" and "i2c0", I suspect your 
configuartion does not work by default.

Re: [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree

[Chen Wang]

On 2024/8/29 13:52, Inochi Amaoto wrote:
> On Thu, Jul 11, 2024 at 12:01:31PM GMT, Thomas Bonnefille wrote:
>> LicheeRV Nano B [1] is an embedded development platform based on the SOPHGO
>> SG2002 chip, the B(ase) version is deprived of Wifi/Bluetooth and Ethernet.
>>
>> Add only support for UART and SDHCI.
>>
>> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html [1]
>>
>> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
>> ---
>>   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>>   .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>>   2 files changed, 55 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
>> index 57ad82a61ea6..47d4243a8f35 100644
>> --- a/arch/riscv/boot/dts/sophgo/Makefile
>> +++ b/arch/riscv/boot/dts/sophgo/Makefile
>> @@ -1,4 +1,5 @@
>>   # SPDX-License-Identifier: GPL-2.0
>>   dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
>>   dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
>> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
>>   dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
>> diff --git a/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
>> new file mode 100644
>> index 000000000000..fc98b6a0ddf7
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
>> @@ -0,0 +1,54 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/*
>> + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "sg2002.dtsi"
>> +
>> +/ {
>> +	model = "LicheeRV Nano B";
>> +	compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002";
>> +
>> +	aliases {
>> +		gpio0 = &gpio0;
>> +		gpio1 = &gpio1;
>> +		gpio2 = &gpio2;
>> +		gpio3 = &gpio3;
>> +		serial0 = &uart0;
>> +		serial1 = &uart1;
>> +		serial2 = &uart2;
>> +		serial3 = &uart3;
>> +		serial4 = &uart4;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&osc {
>> +	clock-frequency = <25000000>;
>> +};
>> +
>> +&sdhci0 {
>> +	status = "okay";
>> +	bus-width = <4>;
>> +	no-1-8-v;
>> +	no-mmc;
>> +	no-sdio;
>> +	disable-wp;
>> +};
>> +
>> +&uart0 {
>> +	status = "okay";
>> +};
>> +
>> +&uart1 {
>> +	status = "okay";
>> +};
>> +
>> +&i2c0 {
>> +	status = "okay";
>> +};
>>
>> -- 
>> 2.45.2
>>
> Have you test you patch with a real board? Especially
> for device "uart1" and "i2c0", I suspect your
> configuartion does not work by default.

Hi, Thomas Bonnefille,

Can you please double check and feedback, I want to confirm this before 
acking this change.

As you know, rc6 will come next week and I'm planning a pr next week.

Regards,

Chen

Re: [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree

[Thomas Bonnefille]

>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "sg2002.dtsi"
>>> +
>>> +/ {
>>> +    model = "LicheeRV Nano B";
>>> +    compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", 
>>> "sophgo,sg2002";
>>> +
>>> +    aliases {
>>> +        gpio0 = &gpio0;
>>> +        gpio1 = &gpio1;
>>> +        gpio2 = &gpio2;
>>> +        gpio3 = &gpio3;
>>> +        serial0 = &uart0;
>>> +        serial1 = &uart1;
>>> +        serial2 = &uart2;
>>> +        serial3 = &uart3;
>>> +        serial4 = &uart4;
>>> +    };
>>> +
>>> +    chosen {
>>> +        stdout-path = "serial0:115200n8";
>>> +    };
>>> +};
>>> +
>>> +&osc {
>>> +    clock-frequency = <25000000>;
>>> +};
>>> +
>>> +&sdhci0 {
>>> +    status = "okay";
>>> +    bus-width = <4>;
>>> +    no-1-8-v;
>>> +    no-mmc;
>>> +    no-sdio;
>>> +    disable-wp;
>>> +};
>>> +
>>> +&uart0 {
>>> +    status = "okay";
>>> +};
>>> +
>>> +&uart1 {
>>> +    status = "okay";
>>> +};
>>> +
>>> +&i2c0 {
>>> +    status = "okay";
>>> +};
>>>
>>> -- 
>>> 2.45.2
>>>
>> Have you test you patch with a real board? Especially
>> for device "uart1" and "i2c0", I suspect your
>> configuartion does not work by default.
> 
> Hi, Thomas Bonnefille,
> 
> Can you please double check and feedback, I want to confirm this before 
> acking this change.
> 
> As you know, rc6 will come next week and I'm planning a pr next week.
> 
> Regards,
> 
> Chen
> 
Hello Chen and Inochi,

I'm really sorry, indeed, those nodes certainly don't work, it was a 
mistake on my side introduced between v1 and v2.
However, I can ensure that "uart0" and "sdhci0" are working fine.
May I suggest to remove those two nodes? I can send a new iteration if 
it's easier for you to handle?

Re: [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree

[Chen Wang]

On 2024/8/30 16:06, Thomas Bonnefille wrote:
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/*
>>>> + * Copyright (C) 2024 Thomas Bonnefille 
>>>> <thomas.bonnefille@bootlin.com>
>>>> + */
>>>> +
>>>> +/dts-v1/;
>>>> +
>>>> +#include "sg2002.dtsi"
>>>> +
>>>> +/ {
>>>> +    model = "LicheeRV Nano B";
>>>> +    compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", 
>>>> "sophgo,sg2002";
>>>> +
>>>> +    aliases {
>>>> +        gpio0 = &gpio0;
>>>> +        gpio1 = &gpio1;
>>>> +        gpio2 = &gpio2;
>>>> +        gpio3 = &gpio3;
>>>> +        serial0 = &uart0;
>>>> +        serial1 = &uart1;
>>>> +        serial2 = &uart2;
>>>> +        serial3 = &uart3;
>>>> +        serial4 = &uart4;
>>>> +    };
>>>> +
>>>> +    chosen {
>>>> +        stdout-path = "serial0:115200n8";
>>>> +    };
>>>> +};
>>>> +
>>>> +&osc {
>>>> +    clock-frequency = <25000000>;
>>>> +};
>>>> +
>>>> +&sdhci0 {
>>>> +    status = "okay";
>>>> +    bus-width = <4>;
>>>> +    no-1-8-v;
>>>> +    no-mmc;
>>>> +    no-sdio;
>>>> +    disable-wp;
>>>> +};
>>>> +
>>>> +&uart0 {
>>>> +    status = "okay";
>>>> +};
>>>> +
>>>> +&uart1 {
>>>> +    status = "okay";
>>>> +};
>>>> +
>>>> +&i2c0 {
>>>> +    status = "okay";
>>>> +};
>>>>
>>>> -- 
>>>> 2.45.2
>>>>
>>> Have you test you patch with a real board? Especially
>>> for device "uart1" and "i2c0", I suspect your
>>> configuartion does not work by default.
>>
>> Hi, Thomas Bonnefille,
>>
>> Can you please double check and feedback, I want to confirm this 
>> before acking this change.
>>
>> As you know, rc6 will come next week and I'm planning a pr next week.
>>
>> Regards,
>>
>> Chen
>>
> Hello Chen and Inochi,
>
> I'm really sorry, indeed, those nodes certainly don't work, it was a 
> mistake on my side introduced between v1 and v2.
> However, I can ensure that "uart0" and "sdhci0" are working fine.
> May I suggest to remove those two nodes? I can send a new iteration if 
> it's easier for you to handle?

I'm fine with this, just go ahead please.

Thanks,

Chen

Re: [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree

[Inochi Amaoto]

On Fri, Aug 30, 2024 at 10:06:45AM GMT, Thomas Bonnefille wrote:
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include "sg2002.dtsi"
> > > > +
> > > > +/ {
> > > > +    model = "LicheeRV Nano B";
> > > > +    compatible = "sipeed,licheerv-nano-b",
> > > > "sipeed,licheerv-nano", "sophgo,sg2002";
> > > > +
> > > > +    aliases {
> > > > +        gpio0 = &gpio0;
> > > > +        gpio1 = &gpio1;
> > > > +        gpio2 = &gpio2;
> > > > +        gpio3 = &gpio3;
> > > > +        serial0 = &uart0;
> > > > +        serial1 = &uart1;
> > > > +        serial2 = &uart2;
> > > > +        serial3 = &uart3;
> > > > +        serial4 = &uart4;
> > > > +    };
> > > > +
> > > > +    chosen {
> > > > +        stdout-path = "serial0:115200n8";
> > > > +    };
> > > > +};
> > > > +
> > > > +&osc {
> > > > +    clock-frequency = <25000000>;
> > > > +};
> > > > +
> > > > +&sdhci0 {
> > > > +    status = "okay";
> > > > +    bus-width = <4>;
> > > > +    no-1-8-v;
> > > > +    no-mmc;
> > > > +    no-sdio;
> > > > +    disable-wp;
> > > > +};
> > > > +
> > > > +&uart0 {
> > > > +    status = "okay";
> > > > +};
> > > > +
> > > > +&uart1 {
> > > > +    status = "okay";
> > > > +};
> > > > +
> > > > +&i2c0 {
> > > > +    status = "okay";
> > > > +};
> > > > 
> > > > -- 
> > > > 2.45.2
> > > > 
> > > Have you test you patch with a real board? Especially
> > > for device "uart1" and "i2c0", I suspect your
> > > configuartion does not work by default.
> > 
> > Hi, Thomas Bonnefille,
> > 
> > Can you please double check and feedback, I want to confirm this before
> > acking this change.
> > 
> > As you know, rc6 will come next week and I'm planning a pr next week.
> > 
> > Regards,
> > 
> > Chen
> > 
> Hello Chen and Inochi,
> 
> I'm really sorry, indeed, those nodes certainly don't work, it was a mistake
> on my side introduced between v1 and v2.
> However, I can ensure that "uart0" and "sdhci0" are working fine.
> May I suggest to remove those two nodes? I can send a new iteration if it's
> easier for you to handle?

As you need a new version, please add pinctrl node and necessary pin
configuration. And I will take the first two binding patch. So there
is no need to add them anymore.

The pinctrl patch (note it also needs a dependency):
https://lore.kernel.org/all/IA1PR20MB4953DC78BB0FE0C57EA94F91BBB32@IA1PR20MB4953.namprd20.prod.outlook.com/

Regard,
Inochi

Re: [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree

[Chen Wang]

On 2024/8/30 19:20, Inochi Amaoto wrote:
> On Fri, Aug 30, 2024 at 10:06:45AM GMT, Thomas Bonnefille wrote:
[......]
>>>> Have you test you patch with a real board? Especially
>>>> for device "uart1" and "i2c0", I suspect your
>>>> configuartion does not work by default.
>>> Hi, Thomas Bonnefille,
>>>
>>> Can you please double check and feedback, I want to confirm this before
>>> acking this change.
>>>
>>> As you know, rc6 will come next week and I'm planning a pr next week.
>>>
>>> Regards,
>>>
>>> Chen
>>>
>> Hello Chen and Inochi,
>>
>> I'm really sorry, indeed, those nodes certainly don't work, it was a mistake
>> on my side introduced between v1 and v2.
>> However, I can ensure that "uart0" and "sdhci0" are working fine.
>> May I suggest to remove those two nodes? I can send a new iteration if it's
>> easier for you to handle?
> As you need a new version, please add pinctrl node and necessary pin
> configuration. And I will take the first two binding patch. So there
> is no need to add them anymore.
>
> The pinctrl patch (note it also needs a dependency):
> https://lore.kernel.org/all/IA1PR20MB4953DC78BB0FE0C57EA94F91BBB32@IA1PR20MB4953.namprd20.prod.outlook.com/
>
> Regard,
> Inochi

FYI, 
https://lore.kernel.org/linux-riscv/MA0P287MB28228F4FC59B057DF57D9A11FE9C2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM/, 
I have raised a PR and included the two bindings related patches.

Thomas Bonnefille, for other DTS part, please go ahead and post new 
version with your changes, I will raise PR after your update.

Regards,

Chen