From: Conor Dooley <conor@kernel.org>
To: Chen Wang <unicorn_wang@outlook.com>
Cc: "Thomas Bonnefille" <thomas.bonnefille@bootlin.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Inochi Amaoto" <inochiama@outlook.com>,
"Chao Wei" <chao.wei@sophgo.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Miquèl Raynal" <miquel.raynal@bootlin.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org,
"Conor Dooley" <conor.dooley@microchip.com>
Subject: Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano
Date: Fri, 12 Jul 2024 15:15:51 +0100 [thread overview]
Message-ID: <20240712-bacon-untruth-5230df76fdad@spud> (raw)
In-Reply-To: <MA0P287MB2822C4E2EEFB67F82458C390FEA62@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
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On Fri, Jul 12, 2024 at 09:33:46AM +0800, Chen Wang wrote:
> > .../interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
> > .../devicetree/bindings/riscv/sophgo.yaml | 5 ++
> > arch/riscv/boot/dts/sophgo/Makefile | 1 +
> > .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts | 54 ++++++++++++++++++++++
> > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 32 +++++++++++++
> > 5 files changed, 93 insertions(+)
>
> How about letting me PR all the four patches in this patchset? Because they
> are all related to sophgo, it would be better to PR them together to avoid
> confusion.
> Especially about the change of sifive,plic-1.0.0.yaml, my original
> understanding was that it should be handled by you.
No, stuff like the plic should really be handled by Thomas as he is the
interrupt controller maintainer, not by me. Usually though, neither the
timer or interrupt controller maintainers seem to care about these sorts
of binding patches which is why they ended up going with the dts.
Ideally the plic patch would go through the tip tree, but I think
there's unlikely to be sleep lost over a trivial binding change going
with the dts user.
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next prev parent reply other threads:[~2024-07-12 14:15 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-11 10:01 [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano Thomas Bonnefille
2024-07-11 10:01 ` [PATCH v4 1/4] dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic Thomas Bonnefille
2024-07-30 6:34 ` Inochi Amaoto
2024-07-11 10:01 ` [PATCH v4 2/4] dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles Thomas Bonnefille
2024-07-11 10:01 ` [PATCH v4 3/4] riscv: dts: sophgo: Add initial SG2002 SoC device tree Thomas Bonnefille
2024-07-11 10:01 ` [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board " Thomas Bonnefille
2024-08-29 5:52 ` Inochi Amaoto
2024-08-30 0:37 ` Chen Wang
2024-08-30 8:06 ` Thomas Bonnefille
2024-08-30 9:22 ` Chen Wang
2024-08-30 11:20 ` Inochi Amaoto
2024-09-04 1:02 ` Chen Wang
2024-07-12 0:31 ` [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano Inochi Amaoto
2024-07-12 1:27 ` Chen Wang
2024-07-12 1:33 ` Chen Wang
2024-07-12 14:15 ` Conor Dooley [this message]
2024-07-13 0:13 ` Chen Wang
2024-08-26 2:55 ` Inochi Amaoto
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