From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2299317591; Sat, 13 Jul 2024 12:00:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720872040; cv=none; b=JS59GNeCbpIDZrWZ5K4o9+fL3EooMhm9iK3HtFsDLIZVqP2xS/Vm46W5gCbEOPznXkO2OlC2WQY6n5TMgN0cA4CBMezMdNGDs+JUrGKiXiHao+hMYjsBtMsOhyVaSosDAJ5TfvhZcBQvBkM9sUG57aHy6r/ZqlTUFa3gtI5tBRs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720872040; c=relaxed/simple; bh=iEq4hTsrFfGTbieTameYcuSA/DAZG32Kq1bRZTpIBFU=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ntUKDp8gD5ltyVzEIZ+GVSVbpRiuVaJ7c+q/Xm0nI7v/kOZf9iMNIKQAMPRXxuF6WDUnGll6kooZrRDWnpMzZkkHyiLu/qVJJ0nTp5euo32aiPxfd6GVros+7OdAGOGMj4pAkZ89JKWNgEhRBPgO6CZXassCyWRq9H25NFDMBMY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Yu8rXhC8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Yu8rXhC8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A321C32781; Sat, 13 Jul 2024 12:00:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720872039; bh=iEq4hTsrFfGTbieTameYcuSA/DAZG32Kq1bRZTpIBFU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Yu8rXhC8OJeD1ormOIiwXYd+oF+Esx1LkSFAR1JKhPenOyG+1zci8FyOQKcDvB2Bs hMRLZk6thpQWIJy5MKc8W0dkW2/HXw9aReE2M2TztN/5BnE2FUknzvCljctb9VZ4Sr xYd3miqCbC3JSYcmxtoGCpPFfjmNjT8naCGSJNiGXACrCQCW/R2hoaUrmp4ByIDqU/ hu1gKSSnxY6yRHdhCRFm+nEo+Ylstc+OaJWQPpMRKSrxhVdL0zAbvrYJcDq08+Ovga bQhXJKUdXULEVbBITPOd5qGtSDIy+Tsn4xnzy04obfOqyI37iIn9dov40QxPWDNuWQ IkKSjOCnFjcVw== Date: Sat, 13 Jul 2024 13:00:24 +0100 From: Jonathan Cameron To: Satya Priya Kakitapalli Cc: Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Amit Kucheria , "Thara Gopinath" , Bjorn Andersson , Konrad Dybcio , Kamal Wadhwa , Taniya Das , Jishnu Prakash , , , , , , Ajit Pandey , "Imran Shaik" , Jagadeesh Kona Subject: Re: [PATCH 1/5] dt-bindings: iio: adc: Add ADC5 GEN3 Channel info for pm8775 PMIC Message-ID: <20240713130024.27b9d8e5@jic23-huawei> In-Reply-To: <20240712-mbg-tm-support-v1-1-7d78bec920ca@quicinc.com> References: <20240712-mbg-tm-support-v1-0-7d78bec920ca@quicinc.com> <20240712-mbg-tm-support-v1-1-7d78bec920ca@quicinc.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 12 Jul 2024 18:13:28 +0530 Satya Priya Kakitapalli wrote: > Add definitions for ADC5 GEN3 virtual channels(combination of ADC channel > number and PMIC SID number) used by PM8775. > > Signed-off-by: Satya Priya Kakitapalli Acked-by: Jonathan Cameron as I presume this will go with the rest via the thermal tree. > --- > .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h | 42 ++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h > new file mode 100644 > index 000000000000..84ab07ed73cc > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h > @@ -0,0 +1,42 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H > + > +#include > + > +/* ADC channels for PM8775_ADC for PMIC5 Gen3 */ > +#define PM8775_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) > +#define PM8775_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) > +#define PM8775_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) > +#define PM8775_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) > + > +#define PM8775_ADC5_GEN3_AMUX1_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM) > +#define PM8775_ADC5_GEN3_AMUX2_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM) > +#define PM8775_ADC5_GEN3_AMUX3_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM) > +#define PM8775_ADC5_GEN3_AMUX4_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM) > +#define PM8775_ADC5_GEN3_AMUX5_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM) > +#define PM8775_ADC5_GEN3_AMUX6_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM) > +#define PM8775_ADC5_GEN3_AMUX1_GPIO9(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO) > +#define PM8775_ADC5_GEN3_AMUX2_GPIO10(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO) > +#define PM8775_ADC5_GEN3_AMUX3_GPIO11(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO) > +#define PM8775_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO) > + > +/* 100k pull-up2 */ > +#define PM8775_ADC5_GEN3_AMUX1_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX2_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX3_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX4_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX5_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX6_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX1_GPIO9_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX2_GPIO10_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX3_GPIO11_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) > +#define PM8775_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) > + > +#define PM8775_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */ >