From: Manivannan Sadhasivam via B4 Relay <devnull+manivannan.sadhasivam.linaro.org@kernel.org>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>
Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 14/14] arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node
Date: Mon, 15 Jul 2024 23:03:56 +0530 [thread overview]
Message-ID: <20240715-pci-qcom-hotplug-v1-14-5f3765cc873a@linaro.org> (raw)
In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org>
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPUs. This interrupt can be used by the device driver to
identify events such as PCIe link specific events, safety events, etc...
Hence, add it to the PCIe RC node along with the existing MSI interrupts.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 9bafb3b350ff..90d16cb83669 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1780,7 +1780,8 @@ pcie0: pcie@1c00000 {
msi-map = <0x0 &gic_its 0x5980 0x1>,
<0x100 &gic_its 0x5981 0x1>;
msi-map-mask = <0xff00>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
@@ -1788,7 +1789,8 @@ pcie0: pcie@1c00000 {
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi0",
+ interrupt-names = "global",
+ "msi0",
"msi1",
"msi2",
"msi3",
@@ -1942,7 +1944,8 @@ pcie1: pcie@1c08000 {
msi-map = <0x0 &gic_its 0x5a00 0x1>,
<0x100 &gic_its 0x5a01 0x1>;
msi-map-mask = <0xff00>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
@@ -1950,7 +1953,8 @@ pcie1: pcie@1c08000 {
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi0",
+ interrupt-names = "global",
+ "msi0",
"msi1",
"msi2",
"msi3",
--
2.25.1
next prev parent reply other threads:[~2024-07-15 17:33 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-15 17:33 [PATCH 00/14] PCI: qcom: Simulate PCIe hotplug using 'global' interrupt Manivannan Sadhasivam via B4 Relay
2024-07-15 17:33 ` [PATCH 01/14] PCI: qcom-ep: Drop the redundant masking of global IRQ events Manivannan Sadhasivam via B4 Relay
2024-07-15 19:57 ` Konrad Dybcio
2024-07-15 17:33 ` [PATCH 02/14] PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event Manivannan Sadhasivam via B4 Relay
2024-07-15 19:58 ` Konrad Dybcio
2024-07-15 17:33 ` [PATCH 03/14] dt-bindings: PCI: pci-ep: Update Maintainers Manivannan Sadhasivam via B4 Relay
2024-07-15 17:33 ` [PATCH 04/14] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property Manivannan Sadhasivam via B4 Relay
2024-07-15 19:59 ` Konrad Dybcio
2024-07-16 4:05 ` Manivannan Sadhasivam
2024-07-22 23:51 ` Rob Herring
2024-07-15 17:33 ` [PATCH 05/14] dt-bindings: PCI: qcom-ep: Document "linux,pci-domain" property Manivannan Sadhasivam via B4 Relay
2024-07-16 8:41 ` neil.armstrong
2024-07-22 23:50 ` Rob Herring
2024-07-15 17:33 ` [PATCH 06/14] PCI: endpoint: Assign PCI domain number for endpoint controllers Manivannan Sadhasivam via B4 Relay
2024-07-15 20:02 ` Konrad Dybcio
2024-07-16 4:14 ` Manivannan Sadhasivam
2024-07-16 15:41 ` kernel test robot
2024-07-16 16:47 ` kernel test robot
2024-07-15 17:33 ` [PATCH 07/14] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Manivannan Sadhasivam via B4 Relay
2024-07-15 17:33 ` [PATCH 08/14] ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node Manivannan Sadhasivam via B4 Relay
2024-07-15 20:03 ` Konrad Dybcio
2024-07-15 17:33 ` [PATCH 09/14] ARM: dts: qcom: sdx65: " Manivannan Sadhasivam via B4 Relay
2024-07-15 20:03 ` Konrad Dybcio
2024-07-15 17:33 ` [PATCH 10/14] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Manivannan Sadhasivam via B4 Relay
2024-07-15 20:04 ` Konrad Dybcio
2024-07-15 17:33 ` [PATCH 11/14] dt-bindings: PCI: qcom: Add 'global' interrupt Manivannan Sadhasivam via B4 Relay
2024-07-15 17:33 ` [PATCH 12/14] dt-bindings: PCI: qcom,pcie-sm8450: " Manivannan Sadhasivam via B4 Relay
2024-07-15 17:33 ` [PATCH 13/14] PCI: qcom: Simulate PCIe hotplug using " Manivannan Sadhasivam via B4 Relay
2024-07-15 20:06 ` Konrad Dybcio
2024-07-16 4:04 ` Krishna Chaitanya Chundru
2024-07-16 4:18 ` Manivannan Sadhasivam
2024-07-16 4:24 ` Krishna Chaitanya Chundru
2024-07-16 5:54 ` Manivannan Sadhasivam
2024-07-16 8:40 ` neil.armstrong
2024-07-16 10:20 ` Manivannan Sadhasivam
2024-07-15 17:33 ` Manivannan Sadhasivam via B4 Relay [this message]
2024-07-15 20:10 ` [PATCH 00/14] " Konrad Dybcio
2024-07-16 3:59 ` Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240715-pci-qcom-hotplug-v1-14-5f3765cc873a@linaro.org \
--to=devnull+manivannan.sadhasivam.linaro.org@kernel.org \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=kishon@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).