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From: Manivannan Sadhasivam via B4 Relay <devnull+manivannan.sadhasivam.linaro.org@kernel.org>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>
Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	 linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v2 13/13] arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node
Date: Wed, 17 Jul 2024 22:33:18 +0530	[thread overview]
Message-ID: <20240717-pci-qcom-hotplug-v2-13-71d304b817f8@linaro.org> (raw)
In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org>

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPUs. This interrupt can be used by the device driver to
identify events such as PCIe link specific events, safety events, etc...

Hence, add it to the PCIe RC node along with the existing MSI interrupts.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 9bafb3b350ff..90d16cb83669 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1780,7 +1780,8 @@ pcie0: pcie@1c00000 {
 			msi-map = <0x0 &gic_its 0x5980 0x1>,
 				  <0x100 &gic_its 0x5981 0x1>;
 			msi-map-mask = <0xff00>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
@@ -1788,7 +1789,8 @@ pcie0: pcie@1c00000 {
 				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "msi0",
+			interrupt-names = "global",
+					  "msi0",
 					  "msi1",
 					  "msi2",
 					  "msi3",
@@ -1942,7 +1944,8 @@ pcie1: pcie@1c08000 {
 			msi-map = <0x0 &gic_its 0x5a00 0x1>,
 				  <0x100 &gic_its 0x5a01 0x1>;
 			msi-map-mask = <0xff00>;
-			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
@@ -1950,7 +1953,8 @@ pcie1: pcie@1c08000 {
 				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "msi0",
+			interrupt-names = "global",
+					  "msi0",
 					  "msi1",
 					  "msi2",
 					  "msi3",

-- 
2.25.1



      parent reply	other threads:[~2024-07-17 17:03 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-17 17:03 [PATCH v2 00/13] PCI: qcom: Simulate PCIe hotplug using 'global' interrupt Manivannan Sadhasivam via B4 Relay
2024-07-17 17:03 ` [PATCH v2 01/13] PCI: qcom-ep: Drop the redundant masking of global IRQ events Manivannan Sadhasivam via B4 Relay
2024-07-17 17:03 ` [PATCH v2 02/13] PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event Manivannan Sadhasivam via B4 Relay
2024-07-17 17:03 ` [PATCH v2 03/13] dt-bindings: PCI: pci-ep: Update Maintainers Manivannan Sadhasivam via B4 Relay
2024-07-23  2:32   ` Rob Herring (Arm)
2024-07-17 17:03 ` [PATCH v2 04/13] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property Manivannan Sadhasivam via B4 Relay
2024-07-23  2:33   ` Rob Herring (Arm)
2024-07-17 17:03 ` [PATCH v2 05/13] PCI: endpoint: Assign PCI domain number for endpoint controllers Manivannan Sadhasivam via B4 Relay
2024-07-18 12:11   ` Konrad Dybcio
2024-07-18 15:01     ` Manivannan Sadhasivam
2024-07-18 15:04   ` kernel test robot
2024-07-18 15:32     ` Manivannan Sadhasivam
2024-07-18 15:37   ` kernel test robot
2024-07-17 17:03 ` [PATCH v2 06/13] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Manivannan Sadhasivam via B4 Relay
2024-07-18 12:12   ` Konrad Dybcio
2024-07-17 17:03 ` [PATCH v2 07/13] ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node Manivannan Sadhasivam via B4 Relay
2024-07-17 17:03 ` [PATCH v2 08/13] ARM: dts: qcom: sdx65: " Manivannan Sadhasivam via B4 Relay
2024-07-17 17:03 ` [PATCH v2 09/13] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Manivannan Sadhasivam via B4 Relay
2024-07-17 17:03 ` [PATCH v2 10/13] dt-bindings: PCI: qcom: Add 'global' interrupt Manivannan Sadhasivam via B4 Relay
2024-07-17 17:03 ` [PATCH v2 11/13] dt-bindings: PCI: qcom,pcie-sm8450: " Manivannan Sadhasivam via B4 Relay
2024-07-23  2:35   ` Rob Herring
2024-07-17 17:03 ` [PATCH v2 12/13] PCI: qcom: Simulate PCIe hotplug using " Manivannan Sadhasivam via B4 Relay
2024-07-17 22:57   ` Mayank Rana
2024-07-18 10:29     ` Manivannan Sadhasivam
2024-07-18 17:15       ` Mayank Rana
2024-07-18 17:23         ` Manivannan Sadhasivam
2024-07-19 23:32   ` Frank Li
2024-07-21  7:34     ` Manivannan Sadhasivam
2024-07-17 17:03 ` Manivannan Sadhasivam via B4 Relay [this message]

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