From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Samuel Holland <samuel.holland@sifive.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
Andy Chiu <andy.chiu@sifive.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v6 06/13] RISC-V: define the elements of the VCSR vector CSR
Date: Mon, 22 Jul 2024 14:58:10 -0700 [thread overview]
Message-ID: <20240722-xtheadvector-v6-6-c9af0130fa00@rivosinc.com> (raw)
In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com>
From: Heiko Stuebner <heiko@sntech.de>
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
Define constants for those to access the elements in a readable way.
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 25966995da04..3eeb07d73065 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -300,6 +300,10 @@
#define CSR_STIMECMP 0x14D
#define CSR_STIMECMPH 0x15D
+#define VCSR_VXRM_MASK 3
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXSAT_MASK 1
+
/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
#define CSR_SISELECT 0x150
#define CSR_SIREG 0x151
--
2.44.0
next prev parent reply other threads:[~2024-07-22 21:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-22 21:58 [PATCH v6 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 02/13] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-07-23 3:54 ` Chen-Yu Tsai
2024-07-22 21:58 ` [PATCH v6 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-07-22 21:58 ` Charlie Jenkins [this message]
2024-07-22 21:58 ` [PATCH v6 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-07-22 21:58 ` [PATCH v6 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
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