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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acadb807dsm511195366b.201.2024.07.29.07.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 07:01:03 -0700 (PDT) Date: Mon, 29 Jul 2024 16:01:02 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor.dooley@microchip.com, anup@brainfault.org, atishp@atishpatra.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, christoph.muellner@vrull.eu, heiko@sntech.de, charlie@rivosinc.com, David.Laight@aculab.com, parri.andrea@gmail.com, luxu.kernel@bytedance.com Subject: Re: [PATCH v3 3/6] riscv: Add Zawrs support for spinlocks Message-ID: <20240729-b6707d037c0546c2c2f8da25@orel> References: <20240426100820.14762-8-ajones@ventanamicro.com> <20240426100820.14762-11-ajones@ventanamicro.com> <4de22b20-8a6a-47d0-a4e9-74343c45411c@ghiti.fr> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4de22b20-8a6a-47d0-a4e9-74343c45411c@ghiti.fr> On Mon, Jul 29, 2024 at 03:43:30PM GMT, Alexandre Ghiti wrote: ... > > +static __always_inline void __cmpwait(volatile void *ptr, > > + unsigned long val, > > + int size) > > +{ > > + unsigned long tmp; > > + > > + asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop", > > + 0, RISCV_ISA_EXT_ZAWRS, 1) > > + : : : : no_zawrs); > > + > > + switch (size) { > > + case 4: > > + asm volatile( > > + " lr.w %0, %1\n" > > + " xor %0, %0, %2\n" > > + " bnez %0, 1f\n" > > + ZAWRS_WRS_NTO "\n" > > + "1:" > > + : "=&r" (tmp), "+A" (*(u32 *)ptr) > > + : "r" (val)); > > + break; > > +#if __riscv_xlen == 64 > > + case 8: > > + asm volatile( > > + " lr.d %0, %1\n" > > + " xor %0, %0, %2\n" > > + " bnez %0, 1f\n" > > + ZAWRS_WRS_NTO "\n" > > + "1:" > > + : "=&r" (tmp), "+A" (*(u64 *)ptr) > > + : "r" (val)); > > + break; > > +#endif > > + default: > > + BUILD_BUG(); > > + } > > + > > + return; > > + > > +no_zawrs: > > + asm volatile(RISCV_PAUSE : : : "memory"); > > > Shouldn't we fallback to the previous implementation (cpu_relax()) here? Not > sure this is really important, but I want to make sure it was not an > oversight. > Hi Alex, It was intentional. We can't easily call cpu_relax() from here because asm/vdso/processor.h includes asm/barrier.h which includes asm/cmpxchg.h. We've mostly reproduced cpu_relax() here since we're only skipping the div, and, as __cmpwait will be used in loops which load memory for the comparison, I didn't think we needed the extra div stalls. Thanks, drew