devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Herve Codina <herve.codina@bootlin.com>
To: Herve Codina <herve.codina@bootlin.com>,
	Christophe Leroy <christophe.leroy@csgroup.eu>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
	Mark Brown <broonie@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: [PATCH v1 27/36] soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their CPM1 version
Date: Mon, 29 Jul 2024 16:20:56 +0200	[thread overview]
Message-ID: <20240729142107.104574-28-herve.codina@bootlin.com> (raw)
In-Reply-To: <20240729142107.104574-1-herve.codina@bootlin.com>

Current code handles the CPM1 version of QMC and initialize the QMC used
SCC. The QUICC Engine (QE) version uses an UCC (Unified Communication
Controllers) instead of the SCC (Serial Communication Controllers) used
in the CPM1 version. These controllers serve the same purpose and are
used in the same way but their inializations are slightly different.

In order to prepare the support for QE version of QMC, introduce
qmc_init_xcc() to initialize theses controllers (UCC in QE and SCC in
CPM1) and isolate the CPM1 specific SCC initialization in a specific
function.

Also introduce qmc_exit_xcc() for consistency to revert operations done
in qmc_init_xcc().

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 drivers/soc/fsl/qe/qmc.c | 66 +++++++++++++++++++++++++++-------------
 1 file changed, 45 insertions(+), 21 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index eacc7dd2be53..b95227378f97 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -1621,6 +1621,41 @@ static int qmc_init_resources(struct qmc *qmc, struct platform_device *pdev)
 	return qmc_cpm1_init_resources(qmc, pdev);
 }
 
+static int qmc_cpm1_init_scc(struct qmc *qmc)
+{
+	u32 val;
+	int ret;
+
+	/* Connect the serial (SCC) to TSA */
+	ret = tsa_serial_connect(qmc->tsa_serial);
+	if (ret)
+		return dev_err_probe(qmc->dev, ret, "Failed to connect TSA serial\n");
+
+	/* Init GMSR_H and GMSR_L registers */
+	val = SCC_GSMRH_CDS | SCC_GSMRH_CTSS | SCC_GSMRH_CDP | SCC_GSMRH_CTSP;
+	qmc_write32(qmc->scc_regs + SCC_GSMRH, val);
+
+	/* enable QMC mode */
+	qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC);
+
+	/* Disable and clear interrupts */
+	qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);
+	qmc_write16(qmc->scc_regs + SCC_SCCE, 0x000F);
+
+	return 0;
+}
+
+static int qmc_init_xcc(struct qmc *qmc)
+{
+	return qmc_cpm1_init_scc(qmc);
+}
+
+static void qmc_exit_xcc(struct qmc *qmc)
+{
+	/* Disconnect the serial from TSA */
+	tsa_serial_disconnect(qmc->tsa_serial);
+}
+
 static int qmc_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -1711,29 +1746,18 @@ static int qmc_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	/* Connect the serial (SCC) to TSA */
-	ret = tsa_serial_connect(qmc->tsa_serial);
-	if (ret) {
-		dev_err(qmc->dev, "Failed to connect TSA serial\n");
+	/* Init SCC */
+	ret = qmc_init_xcc(qmc);
+	if (ret)
 		return ret;
-	}
 
-	/* Init GMSR_H and GMSR_L registers */
-	qmc_write32(qmc->scc_regs + SCC_GSMRH,
-		    SCC_GSMRH_CDS | SCC_GSMRH_CTSS | SCC_GSMRH_CDP | SCC_GSMRH_CTSP);
-
-	/* enable QMC mode */
-	qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC);
-
-	/* Disable and clear interrupts,  set the irq handler */
-	qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);
-	qmc_write16(qmc->scc_regs + SCC_SCCE, 0x000F);
+	/* Set the irq handler */
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
-		goto err_tsa_serial_disconnect;
+		goto err_exit_xcc;
 	ret = devm_request_irq(qmc->dev, irq, qmc_irq_handler, 0, "qmc", qmc);
 	if (ret < 0)
-		goto err_tsa_serial_disconnect;
+		goto err_exit_xcc;
 
 	/* Enable interrupts */
 	qmc_write16(qmc->scc_regs + SCC_SCCM,
@@ -1761,8 +1785,8 @@ static int qmc_probe(struct platform_device *pdev)
 err_disable_intr:
 	qmc_write16(qmc->scc_regs + SCC_SCCM, 0);
 
-err_tsa_serial_disconnect:
-	tsa_serial_disconnect(qmc->tsa_serial);
+err_exit_xcc:
+	qmc_exit_xcc(qmc);
 	return ret;
 }
 
@@ -1776,8 +1800,8 @@ static void qmc_remove(struct platform_device *pdev)
 	/* Disable interrupts */
 	qmc_write16(qmc->scc_regs + SCC_SCCM, 0);
 
-	/* Disconnect the serial from TSA */
-	tsa_serial_disconnect(qmc->tsa_serial);
+	/* Exit SCC */
+	qmc_exit_xcc(qmc);
 }
 
 static const struct qmc_data qmc_data_cpm1 = {
-- 
2.45.0


  parent reply	other threads:[~2024-07-29 14:21 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-29 14:20 [PATCH v1 00/36] soc: fsl: Add support for QUICC Engine TSA and QMC Herve Codina
2024-07-29 14:20 ` [PATCH v1 01/36] soc: fsl: cpm1: qmc: Update TRNSYNC only in transparent mode Herve Codina
2024-07-29 14:20 ` [PATCH v1 02/36] soc: fsl: cpm1: qmc: Enable TRNSYNC only when needed Herve Codina
2024-07-29 14:20 ` [PATCH v1 03/36] soc: fsl: cpm1: tsa: Fix tsa_write8() Herve Codina
2024-07-29 14:20 ` [PATCH v1 04/36] soc: fsl: cpm1: tsa: Use BIT(), GENMASK() and FIELD_PREP() macros Herve Codina
2024-07-29 14:20 ` [PATCH v1 05/36] soc: fsl: cpm1: tsa: Fix blank line and spaces Herve Codina
2024-07-29 14:20 ` [PATCH v1 06/36] soc: fsl: cpm1: tsa: Add missing spinlock comment Herve Codina
2024-07-29 14:20 ` [PATCH v1 07/36] dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller Herve Codina
2024-07-30 19:29   ` Rob Herring
2024-07-29 14:20 ` [PATCH v1 08/36] soc: fsl: cpm1: tsa: Remove unused registers offset definition Herve Codina
2024-07-29 14:20 ` [PATCH v1 09/36] soc: fsl: cpm1: tsa: Use ARRAY_SIZE() instead of hardcoded integer values Herve Codina
2024-07-29 14:20 ` [PATCH v1 10/36] soc: fsl: cpm1: tsa: Make SIRAM entries specific to CPM1 Herve Codina
2024-07-29 14:20 ` [PATCH v1 11/36] soc: fsl: cpm1: tsa: Introduce tsa_setup() and its CPM1 compatible version Herve Codina
2024-07-29 14:20 ` [PATCH v1 12/36] soc: fsl: cpm1: tsa: Isolate specific CPM1 part from tsa_serial_{dis}connect() Herve Codina
2024-07-29 14:20 ` [PATCH v1 13/36] soc: fsl: cpm1: tsa: Introduce tsa_version Herve Codina
2024-07-29 14:20 ` [PATCH v1 14/36] soc: fsl: cpm1: tsa: Add support for QUICC Engine (QE) implementation Herve Codina
2024-07-30  1:43   ` kernel test robot
2024-07-30  9:25   ` [PATCH " Markus Elfring
2024-07-29 14:20 ` [PATCH v1 15/36] MAINTAINERS: Add QE files related to the Freescale TSA controller Herve Codina
2024-07-29 14:20 ` [PATCH v1 16/36] soc: fsl: cpm1: tsa: Introduce tsa_serial_get_num() Herve Codina
2024-07-29 14:20 ` [PATCH v1 17/36] soc: fsl: cpm1: qmc: Rename QMC_TSA_MASK Herve Codina
2024-07-29 14:20 ` [PATCH v1 18/36] soc: fsl: cpm1: qmc: Use BIT(), GENMASK() and FIELD_PREP() macros Herve Codina
2024-07-29 14:20 ` [PATCH v1 19/36] soc: fsl: cpm1: qmc: Fix blank line and spaces Herve Codina
2024-07-29 14:20 ` [PATCH v1 20/36] soc: fsl: cpm1: qmc: Remove unneeded parenthesis Herve Codina
2024-07-29 14:20 ` [PATCH v1 21/36] soc: fsl: cpm1: qmc: Fix 'transmiter' typo Herve Codina
2024-07-29 14:20 ` [PATCH v1 22/36] soc: fsl: cpm1: qmc: Add missing spinlock comment Herve Codina
2024-07-29 14:20 ` [PATCH v1 23/36] dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) QMC controller Herve Codina
2024-07-30 19:36   ` Rob Herring
2024-08-05  6:43     ` Herve Codina
2024-07-29 14:20 ` [PATCH v1 24/36] soc: fsl: cpm1: qmc: Introduce qmc_data structure Herve Codina
2024-07-29 14:20 ` [PATCH v1 25/36] soc: fsl: cpm1: qmc: Re-order probe() operations Herve Codina
2024-07-29 14:20 ` [PATCH v1 26/36] soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 version Herve Codina
2024-07-29 14:20 ` Herve Codina [this message]
2024-07-29 14:20 ` [PATCH v1 28/36] soc: fsl: cpm1: qmc: Rename qmc_chan_command() Herve Codina
2024-07-29 14:20 ` [PATCH v1 29/36] soc: fsl: cpm1: qmc: Handle RPACK initialization Herve Codina
2024-07-29 14:20 ` [PATCH v1 30/36] soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC Herve Codina
2024-07-29 14:21 ` [PATCH v1 31/36] soc: fsl: cpm1: qmc: Introduce qmc_version Herve Codina
2024-07-29 14:21 ` [PATCH v1 32/36] soc: fsl: qe: Add resource-managed muram allocators Herve Codina
2024-07-30  2:46   ` kernel test robot
2024-07-30  3:10   ` kernel test robot
2024-07-29 14:21 ` [PATCH v1 33/36] soc: fsl: qe: Add missing PUSHSCHED command Herve Codina
2024-07-29 14:21 ` [PATCH v1 34/36] soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE) implementation Herve Codina
2024-07-29 14:21 ` [PATCH v1 35/36] soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware Herve Codina
2024-07-29 14:21 ` [PATCH v1 36/36] MAINTAINERS: Add QE files related to the Freescale QMC controller Herve Codina

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240729142107.104574-28-herve.codina@bootlin.com \
    --to=herve.codina@bootlin.com \
    --cc=broonie@kernel.org \
    --cc=christophe.leroy@csgroup.eu \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=krzk+dt@kernel.org \
    --cc=leoyang.li@nxp.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linuxppc-dev@lists.ozlabs.org \
    --cc=qiang.zhao@nxp.com \
    --cc=robh@kernel.org \
    --cc=thomas.petazzoni@bootlin.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).