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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acad416basm772297966b.104.2024.07.31.07.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 07:10:08 -0700 (PDT) Date: Wed, 31 Jul 2024 16:10:07 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Andrea Parri , Nathan Chancellor , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , Guo Ren , linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v4 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs Message-ID: <20240731-56ba72420d7f745dacb66fd8@orel> References: <20240731072405.197046-1-alexghiti@rivosinc.com> <20240731072405.197046-3-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240731072405.197046-3-alexghiti@rivosinc.com> On Wed, Jul 31, 2024 at 09:23:54AM GMT, Alexandre Ghiti wrote: > riscv does not have lr instructions on byte and halfword but the > qspinlock implementation actually uses such atomics provided by the > Zabha extension, so those sizes are legitimate. We currently always come to __cmpwait() through smp_cond_load_relaxed() and queued_spin_lock_slowpath() adds another invocation. However, isn't the reason we're hitting the BUILD_BUG() because the switch fails to find a case for 16, not because it fails to find cases for 1 or 2? The new invocation passes a pointer to a struct mcs_spinlock, which looks like it has size 16. We need to ensure that when ptr points to a pointer that we pass the size of uintptr_t. > > Then instead of failing to build, just fallback to the !Zawrs path. No matter what sizes we're failing on, if we do this then queued_spin_lock_slowpath() won't be able to take advantage of Zawrs. Thanks, drew > > Signed-off-by: Alexandre Ghiti > --- > arch/riscv/include/asm/cmpxchg.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index ebbce134917c..9ba497ea18a5 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -268,7 +268,8 @@ static __always_inline void __cmpwait(volatile void *ptr, > break; > #endif > default: > - BUILD_BUG(); > + /* RISC-V doesn't have lr instructions on byte and half-word. */ > + goto no_zawrs; > } > > return; > -- > 2.39.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv