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From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Andrea Parri <parri.andrea@gmail.com>,
	 Nathan Chancellor <nathan@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	 Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
	Waiman Long <longman@redhat.com>,
	 Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
	 Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
	linux-doc@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	 linux-arch@vger.kernel.org
Subject: Re: [PATCH v4 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs
Date: Wed, 31 Jul 2024 18:14:44 +0200	[thread overview]
Message-ID: <20240731-676154f31336c78bafea57d0@orel> (raw)
In-Reply-To: <CAHVXubjrrWVnw1ufXRJh_5N9M5UiOVZseb0C78fjLaYhNKF7eA@mail.gmail.com>

On Wed, Jul 31, 2024 at 05:52:46PM GMT, Alexandre Ghiti wrote:
> Hi Drew,
> 
> On Wed, Jul 31, 2024 at 4:10 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > On Wed, Jul 31, 2024 at 09:23:54AM GMT, Alexandre Ghiti wrote:
> > > riscv does not have lr instructions on byte and halfword but the
> > > qspinlock implementation actually uses such atomics provided by the
> > > Zabha extension, so those sizes are legitimate.
> >
> > We currently always come to __cmpwait() through smp_cond_load_relaxed()
> > and queued_spin_lock_slowpath() adds another invocation.
> 
> atomic_cond_read_relaxed() and smp_cond_load_acquire() also call
> smp_cond_load_relaxed()
> 
> And here https://elixir.bootlin.com/linux/v6.11-rc1/source/kernel/locking/qspinlock.c#L380,
> the size passed is 1.

Oh, I see.

> 
> > However, isn't
> > the reason we're hitting the BUILD_BUG() because the switch fails to find
> > a case for 16, not because it fails to find cases for 1 or 2? The new
> > invocation passes a pointer to a struct mcs_spinlock, which looks like
> > it has size 16. We need to ensure that when ptr points to a pointer that
> > we pass the size of uintptr_t.
> 
> I guess you're refering to this call here
> https://elixir.bootlin.com/linux/v6.11-rc1/source/kernel/locking/qspinlock.c#L551,
> but it's a pointer to a pointer, which will then pass a size 8.

Ah, missed that '&'...

> 
> And the build error that I get is the following:
> 
> In function '__cmpwait',
>     inlined from 'queued_spin_lock_slowpath' at
> ../kernel/locking/qspinlock.c:380:3:
> ./../include/linux/compiler_types.h:510:45: error: call to
> '__compiletime_assert_2' declared with attribute error: BUILD_BUG
> failed
>   510 |         _compiletime_assert(condition, msg,
> __compiletime_assert_, __COUNTER__)
>       |                                             ^
> ./../include/linux/compiler_types.h:491:25: note: in definition of
> macro '__compiletime_assert'
>   491 |                         prefix ## suffix();
>          \
>       |                         ^~~~~~
> ./../include/linux/compiler_types.h:510:9: note: in expansion of macro
> '_compiletime_assert'
>   510 |         _compiletime_assert(condition, msg,
> __compiletime_assert_, __COUNTER__)
>       |         ^~~~~~~~~~~~~~~~~~~
> ../include/linux/build_bug.h:39:37: note: in expansion of macro
> 'compiletime_assert'
>    39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
>       |                                     ^~~~~~~~~~~~~~~~~~
> ../include/linux/build_bug.h:59:21: note: in expansion of macro
> 'BUILD_BUG_ON_MSG'
>    59 | #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed")
>       |                     ^~~~~~~~~~~~~~~~
> ../arch/riscv/include/asm/cmpxchg.h:376:17: note: in expansion of
> macro 'BUILD_BUG'
>   376 |                 BUILD_BUG();
> 
> which points to the first smp_cond_load_relaxed() I mentioned above.
> 

OK, you've got me straightened out now, but can we only add the fallback
for sizes 1 and 2 and leave the default as a BUILD_BUG()?

Thanks,
drew

  reply	other threads:[~2024-07-31 16:14 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-31  7:23 [PATCH v4 00/13] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-07-31  7:23 ` [PATCH v4 01/13] riscv: Move cpufeature.h macros into their own header Alexandre Ghiti
2024-07-31  9:10   ` Andrew Jones
2024-07-31  7:23 ` [PATCH v4 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs Alexandre Ghiti
2024-07-31 14:10   ` Andrew Jones
2024-07-31 15:52     ` Alexandre Ghiti
2024-07-31 16:14       ` Andrew Jones [this message]
2024-08-01  6:30         ` Alexandre Ghiti
2024-07-31 16:27   ` Waiman Long
2024-07-31 21:51     ` Guo Ren
2024-07-31  7:23 ` [PATCH v4 03/13] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-07-31  9:21   ` Andrew Jones
2024-07-31  7:23 ` [PATCH v4 04/13] dt-bindings: riscv: Add Zabha ISA extension description Alexandre Ghiti
2024-08-01 14:53   ` Conor Dooley
2024-07-31  7:23 ` [PATCH v4 05/13] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-07-31  9:27   ` Andrew Jones
2024-07-31  7:23 ` [PATCH v4 06/13] riscv: Improve zacas fully-ordered cmpxchg() Alexandre Ghiti
2024-07-31  9:59   ` Andrew Jones
2024-07-31 10:33     ` Andrea Parri
2024-08-01  6:15     ` Alexandre Ghiti
2024-07-31  7:23 ` [PATCH v4 07/13] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-07-31 15:41   ` Andrew Jones
2024-07-31  7:24 ` [PATCH v4 08/13] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-07-31 12:20   ` Andrew Jones
2024-07-31  7:24 ` [PATCH v4 09/13] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-07-31  7:24 ` [PATCH v4 10/13] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-07-31  7:24 ` [PATCH v4 11/13] riscv: Add ISA extension parsing for Ziccrse Alexandre Ghiti
2024-07-31  7:24 ` [PATCH v4 12/13] dt-bindings: riscv: Add Ziccrse ISA extension description Alexandre Ghiti
2024-08-01 14:44   ` Conor Dooley
2024-08-02  8:14     ` Alexandre Ghiti
2024-08-02 14:46       ` Conor Dooley
2024-07-31  7:24 ` [PATCH v4 13/13] riscv: Add qspinlock support Alexandre Ghiti
2024-07-31 15:29   ` Andrew Jones
2024-08-01  6:53     ` Alexandre Ghiti
2024-08-01  7:48       ` Andrew Jones
2024-08-02  8:31         ` Alexandre Ghiti
2024-08-15 13:27       ` Alexandre Ghiti
2024-08-15 13:34         ` Andrew Jones
2024-08-17  5:08         ` Guo Ren
2024-08-21 12:18           ` Andrew Jones
2024-08-27  8:02             ` Alexandre Ghiti
2024-08-27  8:03           ` Alexandre Ghiti
2024-08-01  8:43     ` Alexandre Ghiti
2024-08-01 10:15       ` Andrew Jones
2024-08-02  8:58         ` Alexandre Ghiti
2024-08-01  9:48     ` Andrea Parri
2024-08-01 14:15 ` [PATCH v4 00/13] Zacas/Zabha support and qspinlocks Peter Zijlstra

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